CN108206159B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN108206159B
CN108206159B CN201611168702.6A CN201611168702A CN108206159B CN 108206159 B CN108206159 B CN 108206159B CN 201611168702 A CN201611168702 A CN 201611168702A CN 108206159 B CN108206159 B CN 108206159B
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isolation
forming
fin
layer
isolation structure
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CN108206159A (en
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王青鹏
毛刚
赵海
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The invention provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises an isolation region and device regions positioned on two sides of the isolation region, an opening is formed in the fin part isolation region, and the opening penetrates through the fin part in a direction perpendicular to the extending direction of the fin part; forming an initial isolation structure on the substrate and in the opening, wherein the initial isolation structure covers the side wall of the fin part; etching the initial isolation structure, reducing the thickness of the initial isolation structure, and forming an isolation structure, wherein the surface of the isolation structure is lower than the surface of the top of the fin part; an isolation layer is formed on the isolation structure in the opening. The selection of the etching process of the etching treatment is flexible, so that the loss of the fin part in the etching treatment process can be reduced by selecting proper etching reactants and etching process parameters, and the performance of the formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimensions of transistors are continuously shrinking. However, with the rapid decrease of the transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A fin part is formed by the protrusion of the channel of the FinFET out of the surface of the substrate, and the grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin part. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In addition, in order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. The technical field of semiconductors introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the fin parts on two sides of the grid structure; and forming a source drain doped region in the groove by an epitaxial growth process. In order to reduce the exposure of the isolation structure around the fin part in the process of forming the groove at the edge of the fin part and ensure that the structure of the formed source-drain doped region is incomplete, so that the stress on a channel is reduced, and a pseudo-gate structure is formed at the edge of the fin part before the groove is formed. In order to improve the integration of the semiconductor structure, a dummy gate structure is generally formed on the edge of the adjacent fin and the isolation structure.
However, the performance of the semiconductor structure formed by the conventional method for forming the semiconductor structure is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises an isolation region and device regions positioned on two sides of the isolation region, an opening is formed in the fin part isolation region, and the opening penetrates through the fin part in a direction perpendicular to the extending direction of the fin part; forming an initial isolation structure on the substrate and in the opening, wherein the initial isolation structure covers the side wall of the fin part; etching the initial isolation structure, reducing the thickness of the initial isolation structure, and forming an isolation structure, wherein the surface of the isolation structure is lower than the surface of the top of the fin part; an isolation layer is formed on the isolation structure in the opening.
Optionally, the initial isolation structure surface is higher than or flush with the fin top surface.
Optionally, the etching process includes an isotropic dry etching process or a wet etching process.
Optionally, the etching process includes an isotropic dry etching process; the technological parameters of the etching treatment comprise: the etching gas comprises HF; the reaction temperature is 180-220 ℃.
Optionally, the etching selection ratio of the isolation structure to the fin portion by the etching treatment is greater than 100.
Optionally, the process for forming the isolation structure includes: a fluid chemical vapor deposition process.
Optionally, the isolation structure is made of silicon oxide.
Optionally, the isolation layer is made of silicon oxide or silicon oxynitride.
Optionally, the step of forming the isolation layer includes: forming a sacrificial layer on the isolation structure, wherein the sacrificial layer exposes the isolation structure in the opening; forming an initial isolation layer on the sacrificial layer and on the isolation structure in the opening; removing the initial isolation layer on the sacrificial layer to form an isolation layer; and removing the sacrificial layer after removing the initial isolation layer on the sacrificial layer.
Optionally, the process of forming the initial isolation layer includes an atomic layer deposition process.
Optionally, the sacrificial layer is made of an anti-reflection coating or an organic dielectric layer.
Optionally, the process of removing the initial isolation layer on the sacrificial layer includes a dry etching process or a wet etching process.
Optionally, after forming the isolation layer, the method further includes: forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers partial side wall and the top surface of the fin part; forming a dummy gate structure on the isolation layer; and forming source and drain doped layers in the substrate at two sides of the gate structure by an epitaxial growth process.
Optionally, the surface of the isolation layer is higher than or flush with the top surface of the fin portion; the dummy gate structure is also located on top of the fin portion of the sidewall of the opening.
Accordingly, the present invention also provides a semiconductor structure comprising: the semiconductor device comprises a substrate, wherein the substrate is provided with a fin part, the fin part comprises an isolation region and device regions positioned on two sides of the isolation region, an opening is formed in the fin part isolation region, and the opening penetrates through the fin part in a direction perpendicular to the extending direction of the fin part; an isolation structure located on the substrate and in the opening, a surface of the isolation structure in the opening being flush with a surface of the isolation structure in the device region, the surface of the isolation structure being lower than a top surface of the fin; an isolation layer over the isolation structure in the opening.
Optionally, the material of the isolation layer is silicon oxide.
Optionally, the surface of the isolation layer is higher than or flush with the top surface of the fin portion.
Optionally, the method further includes: the grid electrode structure stretches across the fin part and covers partial side wall and the top surface of the fin part; and the dummy gate structure is positioned on the isolation layer.
Optionally, the surface of the isolation layer is higher than or flush with the top surface of the fin portion; the dummy gate structure is also located on top of the fin portion around the opening.
Optionally, the isolation structure is made of silicon oxide.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, before the isolation layer is formed, the initial isolation structure on the substrate and in the opening is simultaneously etched to form the isolation structure. The process of etching the initial isolation structure is carried out before the isolation layer is formed, the etching process can accurately control the appearance of the formed isolation structure and hardly influences the appearance of the isolation layer, and the selection of the etching process of the etching treatment is flexible, so that the loss of the etching treatment process to the fin part can be reduced by selecting proper etching reactants and etching process parameters, and the performance of the formed semiconductor structure can be improved.
Further, the etching treatment process comprises an isotropic dry etching or wet etching process. The isotropic dry etching or wet etching process has no directionality and small loss on the fin part, so that the loss of the fin part caused by etching treatment can be reduced.
Furthermore, the surface of the isolation layer is higher than or flush with the surface of the top of the fin portion, so that the pseudo gate structure can cover the part of the fin portion around the opening, and in the process of forming the source drain doping layer, the pseudo gate structure can protect the part of the fin portion adjacent to the isolation layer, the fin portion on the side wall of the opening is prevented from being exposed out of the isolation layer, and the source drain doping layer with a complete structure can be formed.
In the semiconductor structure provided by the technical scheme of the invention, the surface of the isolation structure in the opening is flush with the surface of the isolation structure in the device region, so that the process for forming the isolation structure is more flexible, the loss of the fin part in the etching treatment process can be reduced by selecting a proper isolation structure forming process, and the performance of the formed semiconductor structure can be improved.
Further, the surface of the dummy gate structure is higher than or flush with the top of the fin portion, so that electric leakage between the fin portion and the dummy gate structure can be reduced.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The formation method of the semiconductor structure has many problems, such as: the performance of the formed semiconductor structure is poor.
Now, with reference to a method for forming a semiconductor structure, the reason for the poor performance of the semiconductor structure formed by the method is analyzed:
fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes: the substrate 100 and the first fin portion 101 and the second fin portion 102 located on the substrate 100 are adjacent, and the extending directions of the first fin portion 101 and the second fin portion 102 are the same.
With continued reference to fig. 1, an isolation structure 110 is formed on the substrate 100 by a fluid chemical deposition process, where the isolation structure 110 covers sidewalls of the first fin 101 and the second fin 102, and a surface of the isolation structure 110 is flush with top surfaces of the first fin 101 and the second fin 102.
Referring to fig. 2, a protection layer 131 is formed on the isolation structure 110 between the first fin 101 and the second fin 102.
Referring to fig. 3, the isolation structure 110 is etched using the protection layer 131 as a mask, so that the surface of the isolation structure 110 is lower than the top surfaces of the first fin 101 and the second fin 102.
In the method for forming the semiconductor structure, the isolation structure 110 is formed through a fluid chemical vapor deposition process, and the fluid chemical vapor deposition process enables the isolation structure 110 to fully fill a gap between the first fin 101 and the second fin 102. However, the isolation structure 110 formed by the fluid chemical vapor deposition process has poor density and is easily etched.
In the process of etching the isolation structure 110, due to the difference in density of the isolation structure 110, the isolation structure 110 between the first fin 101 and the second fin 102 is also easily etched, so that the isolation performance of the isolation structure 110 is reduced. In order to reduce the loss of the isolation structure 110 between the first fin 101 and the second fin 102 due to the etching process, the process of etching the isolation structure 110 is anisotropic dry etching. However, the etching of the anisotropic dry etching has directionality, and the energy of the etching reactant is large, so that the anisotropic dry etching has large loss on the first fin 101 and the second fin 102, and the performance of the formed semiconductor structure is easily affected.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises an isolation region and device regions positioned on two sides of the isolation region, an opening is formed in the fin part isolation region, and the opening penetrates through the fin part in a direction perpendicular to the extending direction of the fin part; forming an initial isolation structure on the substrate and in the opening, wherein the initial isolation structure covers the side wall of the fin part; etching the initial isolation structure, reducing the thickness of the initial isolation structure, and forming an isolation structure, wherein the surface of the isolation structure is lower than the surface of the top of the fin part; an isolation layer is formed on the isolation structure in the opening.
Wherein, before forming the isolation layer, the initial isolation structure on the substrate and in the opening is simultaneously etched to form an isolation structure. The process of etching the initial isolation structure is carried out before the isolation layer is formed, the etching process can accurately control the appearance of the formed isolation structure and hardly influences the appearance of the isolation layer, and the selection of the etching process of the etching treatment is flexible, so that the loss of the etching treatment process to the fin part can be reduced by selecting proper etching reactants and etching process parameters, and the performance of the formed semiconductor structure can be improved.
The above objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention when taken in conjunction with the accompanying drawings.
Fig. 4 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, the substrate 200 has a fin 203 thereon, the fin 203 includes an isolation region and device regions located at two sides of the isolation region, the isolation region fin 203 has an opening 201 therein, and the opening 201 penetrates through the fin 203 in a direction perpendicular to an extending direction of the fin 203.
In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the fin 203 is made of silicon. In other embodiments, the fin may be made of germanium or silicon germanium.
In this embodiment, the fin 203 further has a groove 202 therein, the groove 202 penetrates through the fin 203 in a direction perpendicular to the extending direction of the fin 203, and the dimension of the groove 202 in the extending direction of the fin 203 is greater than the dimension of the opening 201 in the extending direction of the fin 203. In other embodiments, the fin may not have the groove therein.
In this embodiment, the steps of forming the substrate 200 and the fin portion 203 include: providing an initial substrate; forming a patterned mask layer 204 on the initial substrate; and etching the initial substrate by taking the mask layer 204 as a mask to form the substrate 200 and the fin part 203 positioned on the substrate 200.
In this embodiment, the mask layer 204 is made of silicon nitride or silicon oxynitride.
In this embodiment, the substrate 200 has a plurality of fins 203 arranged in parallel. In other embodiments, the substrate may have only one fin.
After the substrate 200 and the fin 203 are formed, the forming method further includes: a protection layer 205 is formed covering the sidewalls of the fin 203 and the surface of the mask layer 204.
The protection layer 205 is used to protect the sidewalls of the fin 203 during a subsequent etching process.
In this embodiment, the material of the protection layer 205 is silicon oxide.
In this embodiment, the process of forming the protection layer 205 includes a chemical vapor deposition process.
Referring to fig. 5, an initial isolation structure 210 is formed on the substrate 200 and in the opening 201 (as shown in fig. 4), and the initial isolation structure 210 covers the sidewalls of the fin 203.
The initial isolation structure 210 is used to form an isolation structure.
In this embodiment, the initial isolation structure 210 surface is higher than or flush with the fin 203 top surface. In other embodiments, the initial isolation structure surface may also be lower than the fin top surface.
In this embodiment, the initial isolation structure 210 is made of silicon oxide. In other embodiments, the material of the initial isolation structure may also be germanium oxide or silicon oxynitride.
In the present embodiment, the initial isolation structure 210 is formed by a Fluid Chemical Vapor Deposition (FCVD) process. The initial isolation structure 210 formed by the bulk chemical vapor deposition process can substantially fill the opening 201 (shown in fig. 4) and the recess 202 (shown in fig. 4).
In this embodiment, the step of forming the isolation structure 210 by a fluid chemical vapor deposition process includes: forming a precursor in the opening 201 and the groove 202; the precursor is subjected to a water vapor annealing process to activate the precursor, forming an initial isolation structure 210.
The precursor has a certain fluidity and can sufficiently fill the openings 201 and the grooves 202, thereby forming initial isolation structures 210 which sufficiently fill the openings 201 and the grooves 202. The principle of the fluid chemical vapor deposition process is as follows: the precursor is a polymer composed of atoms such as silicon, hydrogen, oxygen, nitrogen and the like, and in the water vapor annealing process, the hydrogen and nitrogen atoms in the polymer are replaced by oxygen atoms to form silicon oxide. However, during the water vapor annealing process, the hydrogen and nitrogen atoms in the polymer are difficult to be sufficiently replaced by oxygen atoms, so that the initial isolation structure 210 is formed with a lower stoichiometric silicon oxide content, and the initial isolation structure 210 is formed with a lower density and is easily etched.
Referring to fig. 6, after the initial isolation structure 210 is formed, the method further includes: the initial isolation structure 210 is planarized.
The planarization process is used to planarize the surface of the initial isolation structure 210, providing a relatively planar etch surface for the subsequent etch process.
It should be noted that, during the planarization process, the protection layer 205 and the mask layer 204 (shown in fig. 5) on the top of the fin 203 are also easily removed, so that the top of the fin 203 is exposed.
In this embodiment, the planarization process is implemented by a chemical mechanical polishing process.
Referring to fig. 7, the initial isolation structure 210 (as shown in fig. 6) is etched to reduce the thickness of the initial isolation structure 210, so as to form an isolation structure 211.
By performing an etching process on the initial isolation structure 210, the isolation structure 211 in the opening 201 (as shown in fig. 4) is flush with the surface of the isolation structure 211 in the device region.
The surface of the isolation structure 211 in the opening 201 is flush with the surface of the device region isolation structure 211, so that the subsequently formed isolation layer 251 can be tightly attached to the isolation structure 211, the insulation properties of the isolation structure 211 and the isolation layer 251 in the opening 201 can be increased, and the performance of the formed semiconductor structure can be improved.
The isolation structure 211 is used to realize insulation between two sidewalls of the opening 201.
It should be noted that, before forming the isolation layer later, the initial isolation structure 210 on the substrate 200 and in the opening 201 are simultaneously etched to form the isolation structure 211. The process of etching the initial isolation structure 210 is performed before the isolation layer is formed, the etching process can accurately control the morphology of the formed isolation structure 211 and hardly influences the morphology of the isolation layer, and the selection of the etching process of the etching treatment is flexible, so that the loss of the etching treatment process to the fin part can be reduced by selecting proper etching reactants and etching process parameters, and the performance of the formed semiconductor structure can be improved.
In this embodiment, the etching process includes isotropic dry etching. In other embodiments, the etching process may further include wet etching.
It should be noted that the etching reactants of the etching process include: HF. The HF can chemically react with the initial isolation structure 210 to etch the initial isolation structure 210. Meanwhile, the reaction rate of HF with the initial isolation structure 210 is much greater than with the fin 203. Therefore, the etching process has a relatively large etching selection for the initial isolation structure 210 and the fin portion 203. Specifically, the etching selection ratio of the initial isolation structure 210 to the fin portion 203 in the etching process is greater than 100: 1.
In this embodiment, the temperature of the etching process is 200 ℃. The significance of the temperature range selection is that: firstly, ensuring higher and stable etching rate; and secondly, ensuring higher silicon oxide to silicon etching selection ratio.
In this embodiment, the material of the isolation structure 211 is the same as the material of the initial isolation structure 210. Specifically, the isolation structure 211 is made of silicon oxide.
An isolation layer is subsequently formed on the isolation structure 211 in the opening 201.
In this embodiment, the step of forming the isolation layer is shown in fig. 8 to 13.
A sacrificial layer is subsequently formed on the isolation structure 211, and the sacrificial layer exposes the isolation structure 211 in the opening 201 (shown in fig. 4). In this embodiment, the steps of forming the sacrificial layer are shown in fig. 8 to 10.
Referring to fig. 8, an initial sacrificial layer 240 is formed in the opening 201 and on top of the fin 203.
The initial sacrificial layer 240 is used for subsequent formation of a sacrificial layer.
In this embodiment, the initial sacrificial layer 240 is made of an organic dielectric layer. In other embodiments, the material of the initial sacrificial layer may also be an anti-reflective coating.
In this embodiment, the process of forming the initial sacrificial layer 240 includes a spin coating process.
With continued reference to fig. 8, a photoresist 230 is formed on the initial sacrificial layer 140, the photoresist 230 exposing the initial sacrificial layer 240 on the isolation structure 211 in the opening 201.
In this embodiment, the process of forming the photoresist 230 includes a spin coating process.
In this embodiment, before forming the photoresist 230, the method further includes: an anti-reflective coating (not shown) is formed on the initial sacrificial layer 140.
In this embodiment, the material of the anti-reflective coating is a silicon-containing organic polymer.
Referring to fig. 9, the initial sacrificial layer 240 (shown in fig. 8) is etched using the photoresist 230 as a mask, and the initial sacrificial layer 240 (shown in fig. 8) on the isolation structure 211 in the opening 201 (shown in fig. 4) is removed to form a sacrificial layer 241.
The sacrificial layer 241 is used for protecting the fin 203 in the subsequent process of removing the initial isolation layer, so that damage to the fin 203 is reduced, and the performance of the formed semiconductor structure is improved.
It should be noted that, in the process of etching the initial sacrificial layer 240, the fin 203 can be protected by the initial sacrificial layer 240 and the photoresist 230 on the top of the fin 203, so that the fin 203 is not easily damaged.
In this embodiment, the step of etching the initial sacrificial layer 240 includes: performing a first etching on the initial sacrificial layer 240 until the surface of the initial sacrificial layer 240 is lower than the top surface of the fin 203; after the first etching, a second etching is performed on the initial sacrificial layer 240 to remove the initial sacrificial layer 240 in the opening 201.
It should be noted that, in the first etching process, the etching rate of the first etching on the fin portion 203 is greater than the etching rate of the second etching on the fin portion 203. The first etching has a high etching rate on the fin portion 203, so that a fillet is formed at the joint of the side wall and the top of the fin portion 203, subsequent source-drain plugs can be prevented from contacting the fin portion 203, and electric leakage is reduced.
In this embodiment, the first etching and the second etching include dry etching. In other embodiments, the process of the first and second etching includes wet etching.
Referring to fig. 10, the photoresist 230 is removed (as shown in fig. 9).
In this embodiment, the process of removing the photoresist 230 includes an ashing process.
Referring to fig. 11, an initial isolation layer 250 is formed on the sacrificial layer 241 and the isolation structure 241 in the opening 201 (shown in fig. 4).
The initial isolation layer 250 is used for subsequent isolation layer formation.
In this embodiment, the material of the initial isolation layer 250 is silicon oxide.
In this embodiment, the process of forming the initial isolation layer 250 includes an atomic layer deposition process. The density of the initial isolation layer 250 formed by the atomic layer deposition process is higher, so that the insulation between two side walls of the opening 201 can be increased; and the temperature of the atomic layer deposition process is low, so that the sacrificial layer 241 is not easily damaged. In other embodiments, the process of forming the initial isolation layer includes a high aspect ratio deposition process or a high density plasma vapor deposition process.
In this embodiment, the process parameters for forming the initial isolation layer 250 include: the reaction temperature is less than 200 ℃.
Referring to fig. 12, the initial isolation layer 250 on the sacrificial layer 241 is removed (as shown in fig. 11), and an isolation layer 251 is formed.
The isolation layer 251 is used to electrically isolate the sidewalls of the opening 201 (shown in fig. 4).
In this embodiment, the process of removing the initial isolation layer 250 on the sacrificial layer 241 includes a chemical mechanical polishing process. In other embodiments, the process of removing the initial isolation layer on the sacrificial layer includes a dry etching process or a wet etching process.
In this embodiment, after removing the initial isolation layer 250 on the sacrificial layer 241, the method further includes: and etching the isolation layer 251, and reducing the thickness of the isolation layer 251 to make the surface of the isolation layer 251 flush with the top surface of the fin portion 203. In other embodiments, the isolation layer surface may also be slightly higher or flush with the fin top surface.
In this embodiment, the surface of the isolation layer 251 is flush with or higher than the top surface of the fin 203.
The surface of the isolation layer 251 is flush with or higher than the surface of the top of the fin portion 203, so that a subsequently formed dummy gate structure covers part of the top of the fin portion 203, the fin portion 203 on the surface of the side wall of the isolation layer 251 can be prevented from being removed in the subsequent process of forming a source drain groove, and the formed source drain doped region can be structurally complete.
In this embodiment, the material of the isolation layer 251 is the same as that of the initial isolation layer 250.
In this embodiment, the process of etching the initial isolation layer 250 includes a dry etching process. In other embodiments, the process of etching the initial isolation layer 250 includes a wet etch.
In the process of etching the initial isolation layer 250, the sacrificial layer 241 can protect the fin portion 203, and reduce loss of the fin portion 203.
Referring to fig. 13, after the initial isolation layer 250 on the sacrificial layer 241 is removed (as shown in fig. 12), the sacrificial layer 241 is removed (as shown in fig. 12).
In this embodiment, the process of removing the sacrificial layer 241 includes a dry etching process or a wet etching process.
Referring to fig. 14, a gate structure 270 is formed to cross the fin 203, wherein the gate structure 270 covers a portion of the sidewalls and the top surface of the fin 203; a dummy gate structure 260 is formed on the isolation layer 251.
In this embodiment, the dummy gate structure 260 also covers a portion of the top and sidewalls of the fin 203.
Specifically, in this embodiment, the dummy gate structure 260 further covers a region of the fin portion 203 adjacent to the isolation layer 251.
The forming method further includes: and forming source and drain doping layers 271 in the fin portions 203 on two sides of the gate structure 270.
In this embodiment, the step of forming the drain doping layer 271 includes: forming source and drain grooves in the fin portions 203 on two sides of the gate structure 270; and forming a source drain doping layer 271 in the source drain groove.
In this embodiment, the process for forming the source and drain grooves includes: the combined action of dry etching and wet etching.
It should be noted that, in the process of forming the source-drain groove, since the dummy gate structure 270 further covers the region of the fin portion 203 adjacent to the isolation layer 251, the dummy gate structure 270 can protect a portion of the fin portion 203 adjacent to the isolation layer 251, so that the fin portion 203 on the sidewall surface of the isolation layer 251 can be prevented from being removed in the process of forming the source-drain groove, the structure of the formed source-drain doped region can be complete, and sufficient stress can be provided for the fin portion 203.
In this embodiment, the forming method further includes: and forming a plug for connecting the source drain doping layer 271.
In summary, in the method for forming a semiconductor structure according to the embodiment of the present invention, before forming the isolation layer, the initial isolation structure on the substrate and in the opening is simultaneously etched to form the isolation structure. The process of etching the initial isolation structure is carried out before the isolation layer is formed, the etching process can accurately control the appearance of the formed isolation structure and hardly influences the appearance of the isolation layer, and the selection of the etching process of the etching treatment is flexible, so that the loss of the etching treatment process to the fin part can be reduced by selecting proper etching reactants and etching process parameters, and the performance of the formed semiconductor structure can be improved.
Further, the etching treatment process comprises an isotropic dry etching or wet etching process. The isotropic dry etching or wet etching process has no directionality and small loss on the fin part, so that the loss of the fin part caused by etching treatment can be reduced.
Furthermore, the surface of the isolation layer is higher than or flush with the surface of the top of the fin portion, so that the pseudo gate structure can cover the part of the fin portion around the opening, and in the process of forming the source drain doping layer, the pseudo gate structure can protect the part of the fin portion adjacent to the isolation layer, the fin portion on the side wall of the opening is prevented from being exposed out of the isolation layer, and the source drain doping layer with a complete structure can be formed.
With continued reference to fig. 13, the present embodiment further provides a semiconductor structure, including: the semiconductor device comprises a substrate 200, wherein a fin 203 is arranged on the substrate 200, the fin 203 comprises an isolation region and device regions positioned at two sides of the isolation region, an opening is arranged in the isolation region of the fin 203, and the opening penetrates through the fin 203 in a direction perpendicular to the extending direction of the fin 203; an isolation structure 211 is arranged on the substrate 200, the surface of the isolation structure 211 in the opening is flush with the surface of the isolation structure 211 in the device region, and the surface of the isolation structure is lower than the top surface of the fin part; an isolation layer 251 located over the isolation structure 211 in the opening.
The surface of the isolation structure 211 in the opening is flush with the surface of the isolation structure 211 in the device region, so that the isolation layer 215 can be tightly attached to the isolation structure 211, the insulativity of the isolation structure 211 and the isolation layer 251 in the opening can be increased, and the performance of the formed semiconductor structure can be improved.
In addition, the surface of the isolation structure 211 in the opening is flush with the surface of the isolation structure 211 in the device region, so that the process for forming the isolation structure 211 is more flexible, the loss of the fin portion 203 in the etching process can be reduced by selecting a proper isolation structure 211 forming process, and the performance of the formed semiconductor structure can be improved.
In this embodiment, the isolation layer 251 and the isolation structure 211 are made of silicon oxide.
In this embodiment, the surface of the isolation layer 211 is higher than or flush with the top surface of the fin 203.
The semiconductor structure further includes: a gate structure 270 spanning the fin 203, the gate structure 270 covering a portion of the sidewalls and a top surface of the fin 203; a dummy gate structure 260 covering the isolation layer 211; and the source and drain doping layers 271 are positioned in the fins 203 on two sides of the gate structure 270.
The surface of the isolation layer 251 is higher than or flush with the top surface of the fin portion 203, so that the dummy gate structure 271 covers part of the top of the fin portion 203, and thus in the process of forming the source/drain doping layer 270, the dummy gate structure 270 can protect part of the fin portion 203 adjacent to the isolation layer 251, the fin portion 203 on the side wall of the opening is prevented from exposing the isolation layer 251, and the source/drain doping layer 271 with a complete structure can be formed.
In this embodiment, the dummy gate structure 260 also covers a portion of the top and sidewalls of the fin 203.
In this embodiment, the dummy gate structure 270 is also located on the fin 203 in a region adjacent to the recess 202.
In this embodiment, the substrate 200, the fin portion 203, the isolation structure 211, and the isolation layer 251 are the same as those in the previous embodiment, and are not described herein again.
In summary, in the semiconductor structure provided by the embodiment of the present invention, the surface of the isolation structure in the opening is flush with the surface of the isolation structure in the device region, so that the process for forming the isolation structure is more flexible, and thus the loss of the fin portion in the etching process can be reduced by selecting a suitable process for forming the isolation structure, and the performance of the formed semiconductor structure can be improved.
Further, the surface of the dummy gate structure is higher than or flush with the top of the fin portion, so that electric leakage between the fin portion and the dummy gate structure can be reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises an isolation region and device regions positioned on two sides of the isolation region, an opening is formed in the fin part isolation region, and the opening penetrates through the fin part in a direction perpendicular to the extending direction of the fin part;
forming an initial isolation structure on the substrate and in the opening, wherein the initial isolation structure covers the side wall of the fin part;
etching the initial isolation structure, reducing the thickness of the initial isolation structure, and forming an isolation structure on the substrate and in the opening, wherein the surface of the isolation structure is lower than the top surface of the fin part, and the isolation structure in the opening is flush with the isolation structure which is positioned on the substrate and positioned on the surface of the side wall of the device region;
forming an isolation layer on the isolation structure in the opening;
and forming a dummy gate structure on the isolation layer.
2. The method of claim 1, wherein the initial isolation structure surface is higher than or flush with the fin top surface.
3. The method of forming a semiconductor structure of claim 1, wherein the etching process comprises an isotropic dry etching process or a wet etching process.
4. The method of forming a semiconductor structure of claim 1, wherein the etching process comprises an isotropic dry etching process; the technological parameters of the etching treatment comprise: the etching gas comprises HF; the reaction temperature is 180-220 ℃.
5. The method of claim 1, wherein an etch selectivity ratio of the etching process to the isolation structure to the fin is greater than 100.
6. The method of claim 1, wherein the process of forming the isolation structure comprises: a fluid chemical vapor deposition process.
7. The method of claim 1, wherein the isolation structure is formed of silicon oxide.
8. The method of claim 1, wherein the isolation layer is made of silicon oxide or silicon oxynitride.
9. The method of forming a semiconductor structure of claim 1, wherein the step of forming the isolation layer comprises: forming a sacrificial layer on the isolation structure, wherein the sacrificial layer exposes the isolation structure in the opening; forming an initial isolation layer on the sacrificial layer and on the isolation structure in the opening; removing the initial isolation layer on the sacrificial layer to form an isolation layer; and removing the sacrificial layer after removing the initial isolation layer on the sacrificial layer.
10. The method of forming a semiconductor structure of claim 9, wherein the process of forming the initial isolation layer comprises an atomic layer deposition process.
11. The method of claim 9, wherein the sacrificial layer is an anti-reflective coating or an organic dielectric layer.
12. The method of forming a semiconductor structure of claim 9, wherein the process of removing the initial isolation layer on the sacrificial layer comprises a dry etching process or a wet etching process.
13. The method of forming a semiconductor structure of claim 1, wherein after forming the isolation layer, further comprising: forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers partial side wall and the top surface of the fin part; and forming source and drain doped layers in the substrate at two sides of the gate structure by an epitaxial growth process.
14. The method of claim 1 or 13, wherein the isolation layer surface is higher than or flush with the fin top surface; the dummy gate structure is also located on top of the fin portion of the sidewall of the opening.
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