CN105990235B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN105990235B CN105990235B CN201510051761.4A CN201510051761A CN105990235B CN 105990235 B CN105990235 B CN 105990235B CN 201510051761 A CN201510051761 A CN 201510051761A CN 105990235 B CN105990235 B CN 105990235B
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Abstract
A kind of forming method of semiconductor devices, comprising: provide semiconductor substrate, substrate includes PMOS transistor region；Grid, hard mask are formed on the PMOS transistor region of substrate；The first spacer material layer is formed on the surface of grid and hard mask, the first spacer material thickness degree of gate surface is greater than the first spacer material layer on hard mask surface；The first spacer material layer of segment thickness on the first spacer material layer and gate lateral wall on hard mask surface is removed, remaining first spacer material layer constitutes the first side wall；Carry out wet chemical cleans；The second side wall is formed around hard mask and the first side wall；The position that source-drain electrode is corresponded in PMOS transistor region forms groove and the germanium silicon layer in groove；At least remove the hard mask of segment thickness.Technical solution of the present invention solves the problems, such as that the result of the electrical property conformity testing of the semiconductor devices formed using existing method is unsatisfactory for requiring.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of semiconductor devices.
Background technique
How to improve the performance of transistor to greatest extent is the target that technical field of semiconductors is persisted in the ambition, since stress can
To change the energy gap and carrier (electronics in NMOS transistor, hole) in PMOS transistor mobility of silicon materials, therefore
More and more common means are become with the performance for improving transistor by the way that stress to be applied to the channel region of transistor.
For PMOS transistor, it can be existed using embedded germanium silicon technology (Embedded SiGe Technology)
The channel region of transistor generates compression, and then improves carrier mobility.So-called embedded SiGe technology refer to close to
Embedding germanium silicon material in the semiconductor substrate of PMOS transistor channel region, not by lattice between silicon and germanium silicon (SiGe)
Together, compression is generated to channel region.
A kind of forming method of existing semiconductor devices comprising the PMOS transistor formed using embedded germanium silicon technology
Include:
As shown in Figure 1, providing semiconductor substrate 1, semiconductor substrate 1 includes NMOS transistor region I, PMOS transistor area
Domain II, NMOS transistor region I, the PMOS transistor region II of semiconductor substrate 1 have been respectively formed on grid 2 and have been located at grid
The first side wall 4 is formed with around hard mask 3 on pole 2, grid 2 and hard mask 3 and on 4 side wall of the first side wall
Second side wall 5.The position that source-drain electrode is corresponded in the PMOS transistor region II of semiconductor substrate 1 is formed with groove 6, in groove 6
Filled with germanium silicon layer 7.
In conjunction with shown in Fig. 1 to Fig. 2, the hard mask 3 of NMOS transistor region I and PMOS transistor region II is removed.
In conjunction with shown in Fig. 2 to Fig. 3, removes and covered in the first side wall 4 of NMOS transistor region I and PMOS transistor region II
The part on 3 side wall of hard mask is covered, then, wet chemical cleans are carried out to semiconductor devices, to remove semiconductor devices table
The particle and organic matter in face.
But electrical testing discovery, electrical property conformity testing are carried out to the semiconductor devices formed using the above method
Result be unsatisfactory for requiring, the electrical property conformity testing includes leakage current, gate turn-on voltage, the electricity between source electrode and drain electrode
Stream, resistance etc..
Summary of the invention
The problem to be solved in the present invention is: utilizing the knot of the electrical property conformity testing of the semiconductor devices of existing method formation
Fruit is unsatisfactory for requiring, the PMOS transistor that the semiconductor devices is formed including the use of embedded germanium silicon technology.
To solve the above problems, the present invention provides a kind of forming methods of semiconductor devices, comprising:
Semiconductor substrate is provided, the semiconductor substrate includes PMOS transistor region；
Grid and covering on the grid firmly are formed on the PMOS transistor region of the semiconductor substrate
Mould；
The first spacer material layer is formed in gate lateral wall and hard mask side wall and upper surface, the of the gate lateral wall
Side walling thickness of feed layer is greater than the first spacer material thickness degree on hard mask surface；
Remove the first side of segment thickness on hard mask side wall and the first spacer material layer and gate lateral wall of upper surface
The walling bed of material, the first spacer material layer remained on the gate lateral wall constitute the first side wall；
It is formed after first side wall, carries out wet chemical cleans；
After the wet chemical cleans, the second side wall is formed around the hard mask and the first side wall；
It is formed after second side wall, the position of source-drain electrode is corresponded in the PMOS transistor region of the semiconductor substrate
It sets to form groove and the germanium silicon layer in the groove；
At least remove the hard mask of segment thickness.
Optionally, cleaning solution used by the wet chemical cleans are as follows: the mixed solution of ammonium hydroxide, hydrogen peroxide and water.
Optionally, ammonium hydroxide in the cleaning solution, hydrogen peroxide, water volume ratio be 1:1:200 to 1:1:5, the volume of ammonium hydroxide
Percent concentration is 27% to 31%, and the concentration of volume percent of hydrogen peroxide is 29% to 33%.
Optionally, the first spacer material layer is formed using thermal oxidation process.
Optionally, the material of the first spacer material layer is silica.
Optionally, segment thickness on hard mask side wall and the first spacer material layer and gate lateral wall of upper surface is removed
The first spacer material layer method be wet etching.
Optionally, etching agent used by the wet etching is hydrofluoric acid solution.
Optionally, the forming method of second side wall includes:
Second side walling is formed in the PMOS transistor region of the semiconductor substrate, the first side wall and hard mask
The bed of material；
Second side walling bed of material carve, until exposing the hard mask, to form second side wall.
Optionally, the groove is sigma shape.
Optionally, the forming method of the groove includes:
Using the hard mask and the second side wall as mask, dry method is carried out to the PMOS transistor region of the semiconductor substrate
Etching, to form groove in the semiconductor substrate；
It is performed etching using side wall of the TMAH aqueous solution to the groove, to form the groove.
Optionally, the forming method of the germanium silicon layer is epitaxial growth technology.
Optionally, the hard mask includes the first hard mask and the second hard mask above the first hard mask.
Optionally, second side wall includes the first sub- side wall and the second son being covered on the first sub- side wall side wall
Side wall.
Optionally, second hard mask, the material of the second sub- side wall are identical.
Optionally, the material of first hard mask is silica, and the material of second hard mask is silicon nitride.
Optionally, the material of the described first sub- side wall is silica, and the material of the second sub- side wall is silicon nitride.
Optionally, the semiconductor substrate further includes NMOS transistor region；
Grid and the hard mask on the grid are formed on the PMOS transistor region of the semiconductor substrate
While, grid and the hard mask on grid are formed on the NMOS transistor region of the semiconductor substrate；
While forming first side wall on the PMOS transistor region of the semiconductor substrate, in the semiconductor
The first side wall is formed on the gate lateral wall of substrate NMOS transistor region；
The forming method further include: formed after the groove and germanium silicon layer, on the NMOS transistor region
Hard mask and the first side wall around form the second side wall.
Compared with prior art, technical solution of the present invention has the advantage that
After gate lateral wall and hard mask side wall and upper surface form the first spacer material layer, hard mask side is removed
The first spacer material layer of segment thickness, remains in grid on wall and the first spacer material layer and gate lateral wall of upper surface
The first spacer material layer on side wall constitutes the first side wall, then, carries out wet chemical cleans.Carry out wet chemical cleans it
Afterwards, the position that source-drain electrode is corresponded in the PMOS transistor region of semiconductor substrate forms groove and the germanium in groove
Silicon layer.During carrying out wet chemical cleans, since germanium silicon layer has not yet been formed, therefore germanium silicon layer will not be corroded, germanium silicon layer table
Face not will form pit, therefore the result of the electrical property conformity testing of semiconductor devices can be made to meet the requirements.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of diagrammatic cross-section of the existing semiconductor devices in the different production phases；
Fig. 4 to Figure 15 be in one embodiment of the present of invention semiconductor devices in the diagrammatic cross-section of different production phases.
Specific embodiment
As previously mentioned, the result of the electrical property conformity testing of the semiconductor devices formed using existing method is unsatisfactory for wanting
It asks, the PMOS transistor that the semiconductor devices is formed including the use of embedded germanium silicon technology.
It has been investigated that the reason of causing the above problem is: as shown in figure 3, when carrying out the wet chemical cleans,
Cleaning solution can corrode germanium silicon layer 7, cause 7 surface of germanium silicon layer to form pit 8, and then the electrical property qualification of semiconductor devices is caused to be surveyed
The result of examination is unsatisfactory for requiring.
To solve the above problems, this method is half the present invention provides a kind of forming method of improved semiconductor devices
Corresponded in the PMOS transistor region of conductor substrate source-drain electrode position formed groove and germanium silicon layer in groove it
Before, execute following steps: after gate lateral wall and hard mask side wall and upper surface form the first spacer material layer, removal
The first spacer material layer of segment thickness, residual on hard mask side wall and the first spacer material layer and gate lateral wall of upper surface
The the first spacer material layer stayed on gate lateral wall constitutes the first side wall, then, carries out wet chemical cleans.Carrying out wet type
During learning cleaning, since germanium silicon layer has not yet been formed, therefore germanium silicon layer will not be corroded, and germanium silicon surface not will form pit,
Therefore the result of the electrical property conformity testing of semiconductor devices can be made to meet the requirements.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
As shown in figure 4, providing semiconductor substrate 10, semiconductor substrate 10 includes NMOS transistor region I, PMOS transistor
Region II.
In the present embodiment, semiconductor substrate 10 is monocrystalline substrate.In other embodiments, semiconductor substrate 10 can also
Think other suitable substrate materials.
Semiconductor substrate 10 includes at least one NMOS transistor region I and at least one PMOS transistor region II,
In order to reduce map sheet, only to include a NMOS transistor region I and a PMOS crystal in the semiconductor substrate 10 of attached drawing
For pipe region II.
It is same on the NMOS transistor region I, PMOS transistor region II of semiconductor substrate 10 with continued reference to shown in Fig. 4
When form grid 11 and the hard mask 14 on grid 11.
In the present embodiment, the forming method of grid 11 and the hard mask 14 on grid 11 includes: in semiconductor
Gate material layers are formed on the NMOS transistor region I and PMOS transistor region II of substrate 10 and are located at the grid material
Layer of hard mask material on the bed of material；Graphical photoresist layer, the graphical photoresist are formed in the layer of hard mask material
Layer has opening, and the position and the position of grid 11 of the opening be not corresponding；It is mask to institute using the graphical photoresist layer
It states layer of hard mask material to perform etching, to form hard mask 14；After removing the graphical photoresist layer, it is with hard mask 14
Mask performs etching the gate material layers, to form grid 11.
In the present embodiment, the material of grid 11 is polysilicon, and hard mask 14 includes the first hard mask 12 and is located at the
The second hard mask 13 in one hard mask 12.Wherein, the material of the first hard mask 12 is silica, the material of the second hard mask 13
For silicon nitride.In other embodiments, hard mask 14 or single layer structure, three layers or more of laminated construction, hard mask
Each layer in 14 also can use the material that other are suitable as hard mask and be made.
As shown in figure 5,11 side wall of grid and hard mask on NMOS transistor region I, PMOS transistor region II
14 side walls and upper surface are respectively formed the first spacer material layer 20, and 20 thickness of the first spacer material layer of 11 side wall of grid is greater than to be covered firmly
First spacer material layer, 20 thickness on 14 surface of mould.
In the present embodiment, the first spacer material layer 20 is formed using thermal oxidation process, the material of the first spacer material layer 20
Material is silica.After thermal oxide, the silicon on 14 surface of semiconductor substrate 10, grid 11 and hard mask is oxidized to aoxidize
Silicon.Since the silicone content in grid 11 is greater than the silicone content in hard mask 14, therefore first of 11 side wall of post tensioned unbonded prestressed concrete through thermal oxide
20 thickness of spacer material layer is greater than 20 thickness of the first spacer material layer on 14 surface of hard mask.
When first spacer material layer 20 is using thermal oxidation process formation, material should not be limited only to silica, can also be with
For other oxygen-containing materials.
In conjunction with shown in Fig. 5 to Fig. 6, in removal 10 upper surface of semiconductor substrate, 14 side wall of hard mask, 14 upper surface of hard mask
The first spacer material layer 20 while, removal 11 side wall upper part of grid divides the first spacer material layer 20 of thickness, remains in grid
The first spacer material layer 20 on 11 side wall of pole constitutes the first side wall 21.
During being performed etching to the first spacer material layer 20, the first spacer material layer on 10 surface of semiconductor substrate
20, the first spacer material layer 20 of 11 side wall of grid, 14 side wall of hard mask and the first spacer material layer 20 of upper surface can be by
Etching, since 20 thickness of the first spacer material layer on 14 upper surface of hard mask and side wall is less than the first side of 11 side wall of grid
20 thickness of the walling bed of material, therefore when the first spacer material layer 20 on 14 upper surface of hard mask and side wall is etched, grid
The first spacer material layer 20 on 11 side walls can remain segment thickness to constitute the first side wall 21.
It should be noted that in the inventive solutions, dividing the first side wall of thickness in removal 11 side wall upper part of grid
In the step of material layer 20 is to form the first side wall 21, simultaneously to the etch thicknesses of the first spacer material layer 20 on 11 side wall of grid
There is no specific requirement.When the first spacer material layer 20 of 14 side wall of hard mask and upper surface is etched, to 11 side wall of grid
On the first spacer material layer 20 etching stopping, enable the first spacer material layer 20 on 11 side wall of grid to have residue with structure
At the first side wall 21.
In the present embodiment, the method for removing the first spacer material of part layer 20 is wet etching, the wet etching institute
The etching agent used is hydrofluoric acid solution.
It with continued reference to shown in Fig. 6, is formed after the first side wall 21, carries out wet chemical cleans.
The effect of the wet chemical cleans is the pollutant for removing semiconductor device surface, avoids semiconductor substrate surface
Pollutant adverse effect is caused to subsequent technique.The pollutant includes particle and organic matter.
In the present embodiment, cleaning solution used by the wet chemical cleans are as follows: the mixing of ammonium hydroxide, hydrogen peroxide and water
Solution, the cleaning solution is in alkalinity.Under the Strong oxdiative of hydrogen peroxide and the dissolution of ammonium hydroxide, the pollutant of semiconductor substrate surface
In organic matter become water soluble compound and fall into cleaning solution.The oxidation film and silicon of semiconductor substrate surface are by ammonium hydroxide corruption
Erosion, therefore, the particle for being attached to silicon chip surface can be fallen into cleaning solution with corrosion layer.
In a particular embodiment, the technological parameter of the wet chemical cleans includes: ammonium hydroxide in cleaning solution, hydrogen peroxide, water
The ratio between volume for 1:1:200 to 1:1:5 (i.e. the volume of ammonium hydroxide: the volume of hydrogen peroxide: volume=1:1:200 to 1:1 of water:
5), wherein the concentration of volume percent of ammonium hydroxide is 27% to 31%, and the concentration of volume percent of hydrogen peroxide is 29% to 33%,
The temperature of cleaning solution is 20 DEG C to 60 DEG C, and scavenging period is 10s to 5min.
As shown in fig. 7, in the NMOS transistor region I of semiconductor substrate 10 and the first side of PMOS transistor region II
Third side wall 22 is formed on wall 21 and the side wall of hard mask 14.
In the present embodiment, the forming method of third side wall 22 include: semiconductor substrate 10, the first side wall 21 and
The surface of hard mask 14 forms third spacer material layer；The third spacer material layer carve, until hard mask 14 is revealed
Out.It returns after carving, the third spacer material layer remained on 14 side wall of the first side wall 21 and hard mask constitutes third side wall 22.
In the present embodiment, the material of third side wall 22 is silicon nitride.In other embodiments, third side wall 22 can also be with
It is made using other materials, such as silicon oxynitride.
After third side wall 22 is formed, can be with grid 11, hard mask 14, the first side wall 21 and third side wall 22
Mask carries out ion implanting to semiconductor substrate 10, to form LDD structure (not shown) in semiconductor substrate 10.
As shown in Fig. 8 to Fig. 9, the second side wall layer 29 and the second side wall 28 are formed, the second side wall layer 29, which is covered on, partly leads
On the NMOS transistor region I of body substrate 10 and the hard mask 14 and third side wall 22 of NMOS transistor region I, second side
Wall 28 is covered on the side wall of third side wall 22 of PMOS transistor region II.
In the present embodiment, the forming method of the second side wall 28 of the second side wall layer 29 and PMOS transistor region II
Include: as shown in figure 8, the NMOS transistor region I of semiconductor substrate 10, PMOS transistor region II, third side wall 22, with
And second side walling bed of material 25 is formed in hard mask 14；The first graphical photoresist layer is formed on second side walling bed of material 25
30, the first graphical photoresist layer 30 has position first opening corresponding with the PMOS transistor region II of semiconductor substrate 10
31, the PMOS transistor region II of semiconductor substrate 10 is exposed in the first opening 31 of the first graphical photoresist layer 30；Knot
It closes shown in Fig. 8 to Fig. 9, carve along first 31 pairs of second side walling bed of materials 25 of opening, until exposing PMOS transistor area
The hard mask 14 in domain II, after etching, the PMOS transistor region II of semiconductor substrate 10 and second side in hard mask 14
The walling bed of material 25 is removed, and remains in 25 structure of second side walling bed of material on 22 side wall of third side wall of PMOS transistor region II
At the second side wall 28.
In the present embodiment, as shown in figure 8, second side walling bed of material 25 includes the first sub- spacer material layer 23, Yi Jiwei
In the second sub- spacer material layer 24 on the first sub- spacer material layer 23.As shown in figure 9, the second side wall 28 includes the first sub- side wall
26 and the second sub- side wall 27 for being covered on the first sub- 26 side wall of side wall.Wherein, the material of the first sub- side wall 26 is oxidation
Silicon, it is silicon nitride that the second sub- side wall 27 is identical as the material of the second hard mask 13 in hard mask 14.
In the alternative of the present embodiment, the second side wall 28 can also be only made of single layer side wall, the second side wall layer 29
It can be single layer structure.
As shown in Figures 9 to 11, the position shape of source-drain electrode is corresponded in the PMOS transistor region II of semiconductor substrate 10
At groove 32 and the germanium silicon layer 33 in groove 32.
In the present embodiment, groove 32 is sigma shape, and forming method includes: in conjunction with shown in Fig. 9 to Figure 10, with first
Graphical photoresist layer 30, the hard mask 14 of PMOS transistor region II and the second side wall 28 are mask, to semiconductor substrate 10
PMOS transistor region II carry out dry etching, to form groove 36 in semiconductor substrate 10, groove 36 substantially in bowl-shape,
During the dry etching, the first graphical photoresist layer 30 can protect the second side wall layer 29 of NMOS transistor region I
The not bombardment of subject plasma, the hard mask 14 of PMOS transistor region II can protect the not subject plasma of grid 11 of lower section
Bombardment；It in conjunction with shown in Figure 10 to Figure 11, is formed after groove 36, removes the first graphical photoresist layer 30, followed by
TMAH (Tetramethyl Ammonium Hydroxied, tetramethyl aqua ammonia) aqueous solution carves the side wall of groove 36
Erosion, to form sigma connected in star 32.
TMAH solution corrosion rate with higher, it is nontoxic and pollution-free, convenient for operation, and the crystal orientation of TMAH is selectively good,
Its corrosion rate in crystal orientation<100>and<110>direction is very fast, and in other crystal orientation directions, such as the corrosion on crystal orientation<111>
Rate is very slow, therefore, using TMAH aqueous solution with the spy of different etching rate on 10 different crystal orientations of semiconductor substrate
Property, continue to etch groove 36 to form sigma connected in star 32.
In the alternative of the present embodiment, groove 32 can also be in other shapes, such as rectangular, U-shaped.When groove 32 is in
When sigma shape, can reduce the distance between PMOS transistor source and drain increases the stress for being applied to transistor channel region effectively
Add, and then improves the performance of PMOS transistor.
As shown in figure 12, in the present embodiment, it is formed after groove 32, is formed in groove 32 using epitaxial growth technology
Germanium silicon layer 33.Since the lattice between germanium silicon layer 33 and the silicon in semiconductor substrate 10 is different, therefore channel region can be generated
Compression, to improve the mobility of carrier.
As shown in Figure 13 to Figure 14, the second side wall layer 29 is carried out back to carve etching, until exposing NMOS transistor region I
Hard mask 14, to form the second side wall 28 on 22 side wall of third side wall of NMOS transistor region I.
In the present embodiment, the forming method of the second side wall 28 of NMOS transistor region I includes: shape as shown in figure 13
At second graphical photoresist layer 34, second graphical photoresist layer 34 has the NMOS transistor of position and semiconductor substrate 10
The opening of region I corresponding second 35；In conjunction with shown in Figure 13 to Figure 14, returned along second 35 pair of second side wall layer 29 of opening
It carves, until expose the hard mask 14 of NMOS transistor region I, after etching, the NMOS transistor region I of semiconductor substrate 10,
And the second side wall layer 29 in hard mask 14 is removed, and is remained on 22 side wall of third side wall of NMOS transistor region I
Second side wall layer 29 constitutes the second side wall 28；After NMOS transistor region I forms the second side wall 28, second graphical is removed
Photoresist layer 34.
In conjunction with shown in Figure 14 to Figure 15, the hard mask 14 of segment thickness is removed.
In the present embodiment, the second hard mask 13 in hard mask 14 is removed, that is, the removal thickness of hard mask 14 is equal to the
The thickness of two hard masks 13.Since the second hard mask 13 is identical as the material of the second sub- side wall 27 in the second side wall 28, it is
Silicon nitride, therefore while removing the second hard mask 13, the second sub- side wall 27 in the second side wall 28 can be also removed, so that the
Two side walls 28 are only left the first sub- side wall 26.During removing the second hard mask 13 and the second sub- side wall 27, hard mask 14
In the first hard mask 12 can protect lower section grid 11 be not etched.
In the present embodiment, the minimizing technology of the second hard mask 13 and the second sub- side wall 27 is wet etching.
After the second sub- side wall 27 in second side wall 28 is removed, in semiconductor substrate 10 adjacent PMOS transistor and
Interval, side wall than second 27 between NMOS transistor are big before being removed.
After second hard mask 13 and the second sub- side wall 27 are removed, inter-level dielectric can be formed over the semiconductor substrate 10
Layer, it is hard that the interlayer dielectric layer is covered on NMOS transistor region I, the first sub- side wall 26 and first of PMOS transistor region II
On mask 12.After being removed due to the second sub- side wall 27 in the second side wall 28, adjacent PMOS is brilliant in semiconductor substrate 10
Interval, side wall than second 27 between body pipe and NMOS transistor are big before being removed, therefore the second sub- side wall 27 is removed it
The depth-to-width ratio that the interval between PMOS transistor and adjacent NMOS transistor can be reduced afterwards, has the interlayer dielectric layer
More preferably filling effect.It is formed after the interlayer dielectric layer, chemical mechanical grinding is carried out to the interlayer dielectric layer, until dew
Grid 11 out.During chemical mechanical grinding, the first hard mask 12 can be removed.
In the alternative of the present embodiment, entire hard mask 14 can also be disposably removed.
As previously mentioned, in the alternative of the present embodiment, hard mask 14 or three layers or more of laminated construction,
In this case, the hard mask 14 for removing segment thickness refers to removal one or more layers mask therein.
It should be noted that in the present embodiment, although going back shape in semiconductor substrate other than being formed with PMOS transistor
At there is NMOS transistor, but this should not become limitation of the present invention.It in other embodiments, can also be with shape in semiconductor substrate
At having PMOS transistor but not formed NMOS transistor.It in this case, need to be to the formation of the semiconductor devices of the present embodiment
Method makes adaptable adjustment.
According to noted earlier it is found that in the prior art, referring to figs. 1 to Fig. 3 shown in, before removing hard mask 3, partly lead
The position that source-drain electrode is corresponded in the PMOS transistor region II of body substrate 1 is already formed with groove 6 and is filled in groove 6
Germanium silicon layer 7.Therefore, the wet chemical cleans step after the part being covered on 3 side wall of hard mask in removing the first side wall 4
In rapid, cleaning solution can corrode germanium silicon layer 7, cause 7 surface of germanium silicon layer to form pit 8, and then lead to the electrical property of semiconductor devices
The result of conformity testing is unsatisfactory for requiring.
And in the inventive solutions, the position of source-drain electrode is corresponded in the PMOS transistor region of semiconductor substrate
It is formed before groove and germanium silicon layer in groove, executes following steps: in semiconductor substrate, grid and hard mask
Surface formed after the first spacer material layer, removal semiconductor substrate upper surface, hard mask side wall, hard mask upper surface the
The first spacer material layer of segment thickness, remains in the first side on gate lateral wall on the side walling bed of material and gate lateral wall
The walling bed of material constitutes the first side wall, then, carries out wet chemical cleans.During carrying out wet chemical cleans, due to germanium
Silicon layer has not yet been formed, therefore germanium silicon layer will not be corroded, and germanium silicon surface not will form pit, therefore can make semiconductor devices
The result of electrical property conformity testing is met the requirements.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes PMOS transistor region；
Grid and the hard mask on the grid are formed on the PMOS transistor region of the semiconductor substrate；
The first spacer material layer, the first side of the gate lateral wall are formed in gate lateral wall and hard mask side wall and upper surface
Walling thickness of feed layer is greater than the first spacer material thickness degree on hard mask surface；
Remove the first side wall material of segment thickness on hard mask side wall and the first spacer material layer and gate lateral wall of upper surface
The bed of material, the first spacer material layer remained on the gate lateral wall constitute the first side wall；
It is formed after first side wall, carries out wet chemical cleans；
After the wet chemical cleans, the second side wall is formed around the hard mask and the first side wall；
It is formed after second side wall, the position shape of source-drain electrode is corresponded in the PMOS transistor region of the semiconductor substrate
At groove and the germanium silicon layer in the groove；
At least remove the hard mask of segment thickness.
2. forming method as described in claim 1, which is characterized in that cleaning solution used by the wet chemical cleans are as follows:
The mixed solution of ammonium hydroxide, hydrogen peroxide and water.
3. forming method as claimed in claim 2, which is characterized in that the volume ratio of ammonium hydroxide, hydrogen peroxide, water in the cleaning solution
Concentration of volume percent for 1:1:200 to 1:1:5, ammonium hydroxide is 27% to 31%, and the concentration of volume percent of hydrogen peroxide is
29% to 33%.
4. forming method as described in claim 1, which is characterized in that the first spacer material layer utilizes thermal oxidation process shape
At.
5. forming method as claimed in claim 4, which is characterized in that the material of the first spacer material layer is silica.
6. forming method as claimed in claim 5, which is characterized in that the first side wall material of removal hard mask side wall and upper surface
The method of the first spacer material layer of segment thickness is wet etching on the bed of material and gate lateral wall.
7. forming method as claimed in claim 6, which is characterized in that etching agent used by the wet etching is hydrofluoric acid
Solution.
8. forming method as described in claim 1, which is characterized in that the forming method of second side wall includes:
Second side walling bed of material is formed in the PMOS transistor region of the semiconductor substrate, the first side wall and hard mask；
Second side walling bed of material carve, until exposing the hard mask, to form second side wall.
9. forming method as described in claim 1, which is characterized in that the groove is sigma shape.
10. forming method as claimed in claim 9, which is characterized in that the forming method of the groove includes:
Using the hard mask and the second side wall as mask, is carried out to the PMOS transistor region of the semiconductor substrate dry method quarter
Erosion, to form groove in the semiconductor substrate；
It is performed etching using side wall of the TMAH aqueous solution to the groove, to form the groove.
11. forming method as described in claim 1, which is characterized in that the forming method of the germanium silicon layer is epitaxial growth work
Skill.
12. forming method as described in claim 1, which is characterized in that the hard mask includes the first hard mask and is located at
The second hard mask above first hard mask.
13. forming method as claimed in claim 12, which is characterized in that second side wall include the first sub- side wall and
The second sub- side wall being covered on the first sub- side wall side wall.
14. forming method as claimed in claim 13, which is characterized in that the material of second hard mask, the second sub- side wall
It is identical.
15. forming method as claimed in claim 12, which is characterized in that the material of first hard mask is silica, institute
The material for stating the second hard mask is silicon nitride.
16. forming method as claimed in claim 13, which is characterized in that the material of the first sub- side wall is silica, institute
The material for stating the second sub- side wall is silicon nitride.
17. such as the described in any item forming methods of claim 1 to 16, which is characterized in that the semiconductor substrate further includes
NMOS transistor region；
The same of grid and the hard mask on the grid is formed on the PMOS transistor region of the semiconductor substrate
When, grid and the hard mask on grid are formed on the NMOS transistor region of the semiconductor substrate；
While forming first side wall on the PMOS transistor region of the semiconductor substrate, in the semiconductor substrate
The first side wall is formed on the gate lateral wall of NMOS transistor region；
The forming method further include: it is formed after the groove and germanium silicon layer, it is hard on the NMOS transistor region
The second side wall is formed around mask and the first side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510051761.4A CN105990235B (en) | 2015-01-30 | 2015-01-30 | The forming method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510051761.4A CN105990235B (en) | 2015-01-30 | 2015-01-30 | The forming method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990235A CN105990235A (en) | 2016-10-05 |
| CN105990235B true CN105990235B (en) | 2019-05-28 |
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| CN101711427A (en) * | 2007-04-12 | 2010-05-19 | 先进微装置公司 | Strain hardening N-type semiconductor N device and be used for the method that this semiconductor device is made |
| CN101777516A (en) * | 2005-01-11 | 2010-07-14 | 富士通微电子株式会社 | Fabrication process for semiconductor integrated circuit |
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| CN101711427A (en) * | 2007-04-12 | 2010-05-19 | 先进微装置公司 | Strain hardening N-type semiconductor N device and be used for the method that this semiconductor device is made |
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