CN104716029B - The preparation method of semiconductor devices - Google Patents
The preparation method of semiconductor devices Download PDFInfo
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- CN104716029B CN104716029B CN201310681725.7A CN201310681725A CN104716029B CN 104716029 B CN104716029 B CN 104716029B CN 201310681725 A CN201310681725 A CN 201310681725A CN 104716029 B CN104716029 B CN 104716029B
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Abstract
The invention discloses a kind of preparation method of semiconductor devices, methods described includes：a）Semiconductor substrate is provided, surrounded in the Semiconductor substrate formed with tungsten grid structure, the tungsten grid structure by interlayer dielectric layer；b）A part for the tungsten grid structure is etched back to, to form groove in the top of the tungsten grid structure；c）On the interlayer dielectric layer and cap layers are formed in the groove, the cap layers fill up the groove；d）Protective layer is formed in the cap layers；And e）Cap layers beyond the protective layer and the groove are removed using chemically mechanical polishing.Method provided by the invention can avoid the cap layers in CMP process from being layered with tungsten grid structure by forming protective layer with protective cap layers.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular it relates to a kind of preparation method of semiconductor devices.
Background technology
As dimensions of semiconductor devices becomes less and less, the size of grid structure also correspondingly reduces.Work as semiconductor device
When part size is less than 0.1 μm, it usually needs using metal gate（Such as aluminium gate）Instead of polysilicon gate.Work as dimensions of semiconductor devices
It is, for example, less than 20nm technology nodes when further reducing, due to the clearance filling capability of tungsten and the needs of semiconductor devices, leads to
Aluminium gate is replaced frequently with tungsten grid.
It is the contact using autoregistration pattern making that the further reduction of dimensions of semiconductor devices, which brings another problem,
Hole also is difficult to be aligned.If such case occurs, contact hole is likely to bridge with tungsten grid.In order to solve the problem, in tungsten grid
The chemically mechanical polishing of pole（CMP）Tungsten grid will be etched back after technique, and the surface cvd nitride after being etched back to
Silicon finally carries out CMP to fill the groove for being etched back to be formed to silicon nitride.But the bonding force of silicon nitride layer and tungsten compared with
Difference, during the CMP of silicon nitride layer, silicon nitride layer is easy to be layered with tungsten and out of groove depart from.So, subsequent shape
If into contact hole misalignment, may be bridged with tungsten grid, cause semiconductor device failure.
It is, therefore, desirable to provide a kind of preparation method of semiconductor devices, to solve problems of the prior art.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to solve problems of the prior art, the present invention proposes a kind of preparation method of semiconductor devices, institute
The method of stating includes：a）Semiconductor substrate is provided, formed with tungsten grid structure in the Semiconductor substrate, the tungsten grid structure by
Interlayer dielectric layer surrounds；b）A part for the tungsten grid structure is etched back to, it is recessed to be formed in the top of the tungsten grid structure
Groove；c）On the interlayer dielectric layer and cap layers are formed in the groove, the cap layers fill up the groove；d）In the cap layers
Upper formation protective layer；And e）Cap layers beyond the protective layer and the groove are removed using chemically mechanical polishing.
Preferably, the thickness for being etched back to part of the tungsten grid structure is 200-400 angstroms.
Preferably, the cap layers are nitride.
Preferably, the protective layer is oxide.
Preferably, the polishing speed of the protective layer is more than the polishing speed of the cap layers.
Preferably, the thickness of the protective layer is less than the thickness of the cap layers.
Preferably, the thickness of the cap layers is 500-1500 angstroms.
Preferably, the thickness of the protective layer is 200-1000 angstroms.
Preferably, the tungsten grid structure includes gate dielectric in the Semiconductor substrate, positioned at the grid
The work-function layer of tungsten gate material layers and the encirclement tungsten gate material layers on the dielectric layer of pole.
Preferably, the adhesion of the protective layer is more than the adhesion of the cap layers.
Method provided by the invention can be avoided in CMP process by forming protective layer with protective cap layers
Cap layers are layered with tungsten grid structure.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the flow chart of the preparation method of semiconductor devices according to an embodiment of the invention；And
Fig. 2A -2E are to make the device that each step obtains during semiconductor devices using the method shown in Fig. 1
Sectional view.
Embodiment
Next, the present invention will be more fully described by with reference to accompanying drawing, shown in the drawings of embodiments of the invention.But
It is that the present invention can be implemented in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, provide
These embodiments will make disclosure thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.
In accompanying drawing, for clarity, the size and relative size in Ceng He areas may be exaggerated.Same reference numerals represent phase from beginning to end
Same element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.
According to an aspect of the present invention, there is provided a kind of preparation method of semiconductor devices.Specifically, there is provided one kind has
The preparation method of the semiconductor devices of tungsten grid.It is worth noting that, can before making tungsten grid, among or provide afterwards
Extra technique makes the other elements in semiconductor devices.After herein exemplified by grid technology, the flow chart with reference to shown in Fig. 1
And the method for making semiconductor devices of the semiconductor device structure schematic diagram shown in Fig. 2A -2E to the present invention is carried out specifically
It is bright.
Perform step S110：Semiconductor substrate is provided, formed with tungsten grid structure, the tungsten grid knot in the Semiconductor substrate
Structure is surrounded by interlayer dielectric layer.
As shown in Figure 2 A, there is provided Semiconductor substrate 210.The Semiconductor substrate 210 can be silicon, silicon-on-insulator（SOI）、
Silicon is laminated on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And
Germanium on insulator（GeOI）At least one of.The shallow trench for isolating active area is could be formed with Semiconductor substrate 210
Isolation（STI）Can be by silica, silicon nitride, silicon oxynitride, Fluorin doped glass and/or other existing Deng the isolation of, shallow trench
Dielectric materials are formed.Certainly, can also be formed with dopant well in Semiconductor substrate 210（It is not shown）Etc..In order to illustrate letter
It is clean, square frame is only used for herein to represent.
Formed with tungsten grid structure 220 in Semiconductor substrate 210.As an example, tungsten grid structure 220 can include grid
Dielectric layer 221, tungsten gate material layers 222 and work-function layer 223.Gate dielectric 221 is located in Semiconductor substrate 210.Grid
Dielectric layer 221 can be formed by atomic layer deposition method or other suitable modes.Gate dielectric 221 can be high k dielectric
Material, such as hafnium oxide（HfO2）.Tungsten gate material layers 222 are located on gate dielectric 221.Tungsten gate material layers 222 can be with
Formed by tungsten or tungsten alloy.Work-function layer 223 surrounds tungsten gate material layers 222, to provide high effective work function（EWF）Value.Should
Work-function layer 223 can include the one or more in Ti, TaN, TiN, AlCO, TiAlN.Work-function layer 223 can pass through original
Sublayer sedimentation or other suitable modes are formed.
Formed with the interlayer dielectric layer 230 for surrounding tungsten grid structure 220 in Semiconductor substrate 210.Interlayer dielectric layer 230 can
For silicon oxide layer, made using thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP)
Make the material layer for having doped or undoped silica of technique formation, such as undoped silica glass (USG), phosphorosilicate glass
Or boron-phosphorosilicate glass (BPSG) (PSG).In addition, interlayer dielectric layer 230 can also be the spin cloth of coating-type for adulterating boron or adulterating phosphorus
Glass (spin-on-glass, SOG), the tetraethoxysilane (PTEOS) for adulterating phosphorus or the tetraethoxysilane for adulterating boron
(BTEOS)。
In addition, the material of interlayer dielectric layer 230 can also include such as fluorocarbon (CF), carbon doped silicon oxide
Or carbonitride of silicium (SiCN) etc. (SiOC).Or the film that SiCN films are formd on fluorocarbon (CF) can also be used
Deng.Fluorocarbon is with fluorine (F) and carbon (C) for main component.Fluorocarbon can also be used with noncrystal (noncrystalline
Property) construction material.Interlayer dielectric layer can also use the Porous such as carbon doped silicon oxide (SiOC) to construct.
Tungsten grid structure 220 is, for example, to make what is formed using following technique.Specifically, can be first in Semiconductor substrate
Dummy grid is formed on 210, the dummy grid can include such as polysilicon；Then regions and source/drain is formed in substrate 210,
Regions and source/drain can be formed in any manner known in the art；Afterwards, interlayer is formed on Semiconductor substrate 210
Dielectric layer 230, and interlayer dielectric layer 230 is planarized, to expose dummy grid；Then, dummy grid is removed, the dummy grid can be with
Removed for example, by the mode of etching, so as to form recess among interlayer dielectric layer 230；Finally, tungsten grid are formed in recess
Pole structure.
Perform step S120：A part for tungsten grid structure is etched back to, to form groove in the top of tungsten grid structure.
As shown in Figure 2 B, for example reactive plasma etching industrial of use is by the top etch of tungsten grid structure, so as to
The top of tungsten grid structure forms groove 240.Etching gas selected by the step can be mainly for tungsten, due to work content
Several layers 223 relatively thin, can be consumed substantially during being etched back to.As an example, being etched back to the etching gas of technique can include
NF3、F2And SF6At least one of.In a preferred embodiment, etching gas include about 500sccm Ar and about 50sccm
NF3.Furthermore it is also possible to add a small amount of O2And CH2F2Or CH3F.For example, about 10sccm O2About 50sccm's
CH2F2Or CH3F.Additive below can help to maintain to abut the selectivity of size or increase to oxide hardmask.
In preferred embodiment, pressure is about 100-200mTorr, and power is about 500W.
In one embodiment, the thickness for being etched back to part of tungsten grid structure can be 200-400 angstroms.This is etched back to portion
Divide the part for referring to be removed in technique is etched back to.So, can form depth in the top of remaining tungsten grid structure is
200-400 angstroms of groove 240.
Perform step S130：On interlayer dielectric layer and cap layers are formed in groove, the cap layers fill up groove.
As shown in Figure 2 C, depositing cap layers 250, cap layers 250 fill up groove on interlayer dielectric layer 230 and in groove 240
240.In one embodiment, cap layers 250 are nitride layer.The cap layers 250 can be using chemical vapor deposition, physical vapor
What the methods of deposition, was formed.The opening higher than groove 240 is preferably able to after cap layers 250 fill up groove 240, so as to be follow-up
CMP provide surplus.But the thickness of the cap layers 250 blocked up cycle that may extend whole process, therefore, at one preferably
In embodiment, the thickness of cap layers is 500-1500 angstroms.
Perform step S140：Protective layer is formed in cap layers.
As shown in Figure 2 D, protective layer 260 is formed in cap layers 250.Protective layer 260 covers cap layers 250, to fill up cap layers
The microrelief on 250 surfaces.Signified microrelief does not include the surface of protective layer 260 caused by groove 240 herein
Larger depression.In subsequent CMP process, protective layer 260 can avoid cap layers 250 and tungsten grid in groove
Pole structure 220 is layered.
Due to the generally use nitride of cap layers 250, nitride generally has relatively low polishing speed.Therefore, the present invention carries
The method of confession, which is particularly applicable to protect layer 260, has a case that the polishing speed for being higher than cap layers 250.In the case, in this hair
In the preferred embodiment of bright offer, the thickness of protective layer 260 is less than the thickness of cap layers 250.At the initial stage of chemically mechanical polishing, by
It is higher in the polishing speed of protective layer 260, therefore, it is very easy to make the surface of protective layer 260 flat.Therefore, the thickness of protective layer 260
Degree can be with relatively thin relative to the thickness of cap layers 250.It is micro- due to the surface of cap layers 250 when being polished to the surface of cap layers 250
Small fluctuating is already filled up and surface is flat, therefore continues to keep away to a certain extent during polishing cap layers 250
Exempt from cap layers 250 to be layered with tungsten grid structure 220.As an example, the thickness of protective layer 260 can be 200-1000 angstroms.Protective layer
260 thickness can play a good protection within the range, and and can enough avoids extending the process time.
Moreover it is preferred that the adhesion of protective layer 260 is preferably more than the adhesion of cap layers 250.The adhesion refers to crystalline substance
Existing interaction force between particle in body.During below face A-A and not up to face B-B is polished to, the surface of cap layers 250
Depression in protective layer 260 crystal grain in cap layers 250 can be played constraint effect.Also, due to what is now polished
Surface relatively flat, therefore the risk that cap layers 250 are layered with tungsten grid structure 220 can be reduced.As an example, protective layer
260 can be oxide skin(coating).
Perform step S150：Cap layers beyond protective layer and groove are removed using chemically mechanical polishing.
As shown in Figure 2 E, protective layer 260 and the unexpected cap layers 250 of groove are removed using chemically mechanical polishing.So exist
The cap layers 250 that the top of tungsten grid structure 220 is formed can play a protective role during contact hole is formed, and avoid occurring
The phenomenon that tungsten grid structure 220 bridges with contact hole.
Method provided by the invention can be avoided in CMP process by forming protective layer with protective cap layers
Cap layers are layered with tungsten grid structure.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that methods described includes：
A) Semiconductor substrate is provided, be situated between in the Semiconductor substrate formed with tungsten grid structure, the tungsten grid structure by interlayer
Electric layer is surrounded；
B) part for the tungsten grid structure is etched back to, to form groove in the top of the tungsten grid structure；
C) on the interlayer dielectric layer and cap layers are formed in the groove, the cap layers fill up the groove；
D) protective layer is formed in the cap layers；And
E) cap layers beyond the protective layer and the groove are removed using chemically mechanical polishing.
2. the method as described in claim 1, it is characterised in that the thickness for being etched back to part of the tungsten grid structure is 200-
400 angstroms.
3. the method as described in claim 1, it is characterised in that the cap layers are nitride.
4. the method as described in claim 1, it is characterised in that the protective layer is oxide.
5. the method as described in claim 1, it is characterised in that the polishing speed of the protective layer is more than the polishing of the cap layers
Speed.
6. method as claimed in claim 5, it is characterised in that the thickness of the protective layer is less than the thickness of the cap layers.
7. method as claimed in claim 6, it is characterised in that the thickness of the cap layers is 500-1500 angstroms.
8. method as claimed in claim 6, it is characterised in that the thickness of the protective layer is 200-1000 angstroms.
9. the method as described in claim 1, it is characterised in that the tungsten grid structure is included in the Semiconductor substrate
Gate dielectric, the tungsten gate material layers on the gate dielectric and the work content for surrounding the tungsten gate material layers
Several layers.
10. the method as described in claim 1, it is characterised in that the adhesion of the protective layer is more than the combination of the cap layers
Power.
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| CN107968092B (en) * | 2017-11-16 | 2018-12-14 | 长江存储科技有限责任公司 | Intermetallic compound protective layer in 3D NAND and forming method thereof |
| CN110149765B (en) * | 2019-04-26 | 2020-06-05 | 信利光电股份有限公司 | Method for manufacturing protective film on circuit substrate |
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| US5444026A (en) * | 1992-06-10 | 1995-08-22 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor device by forming insulator-layer to suppress bubble formation |
| CN102569383A (en) * | 2010-12-14 | 2012-07-11 | 中国科学院微电子研究所 | MOS (Metal oxide semiconductor) tube and manufacturing method thereof |
| CN102810561A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103378136A (en) * | 2012-04-17 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Structure and method for NFET with high k metal gate |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444026A (en) * | 1992-06-10 | 1995-08-22 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor device by forming insulator-layer to suppress bubble formation |
| CN102569383A (en) * | 2010-12-14 | 2012-07-11 | 中国科学院微电子研究所 | MOS (Metal oxide semiconductor) tube and manufacturing method thereof |
| CN102810561A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103378136A (en) * | 2012-04-17 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Structure and method for NFET with high k metal gate |
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