CN107968092B - Intermetallic compound protective layer in 3D NAND and forming method thereof - Google Patents
Intermetallic compound protective layer in 3D NAND and forming method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
Provide intermetallic compound (IMC) protective layer and forming method thereof in a kind of 3D NAND.The IMC object protective layer is formed in drain selection unit groove, between TiN adhesion layer and tungsten (W) grid, for by HfF4、WF6The IMC HfW that metal layer is formed via 1000 DEG C or more high-temperature heat treatments is co-deposited with the hafnium Hf and tungsten W of other auxiliary gas preparations2Layer.The IMC HfW2Layer can prevent the tungsten of tungsten grid from diffusing into silicon substrate, so as to avoid breakdown voltage Problem of Failure, improve the electrical property of 3D NAND.
Description
Technical field
This application involves three-dimensional (3D) memory technology fields, more specifically, the metal being related in a kind of 3D NAND
Between compound protective layer and forming method thereof.
Background technique
With the fast development of flash memory, 3D flash memory structure is rapidly developed, and NAND-type flash memory is a kind of to compare hard disk
Driver preferably stores equipment, as people pursue the non-volatile memory product of low in energy consumption, light weight and excellent performance, 3D
Nand flash memory is even more to be widely used in electronic product.
In existing 3D NAND preparation process, the preparation for being related to bottom selection gate (BTM) generallys use following technique:
As shown in Fig. 1 (a), the bottom gate oxide layers of steam in situ growth (ISSG) technique preparation bottom selection gate (BSG) are utilized；
After forming storage unit, source electrode groove is formed via etching, and the side gate oxide of BSG is formed as shown in Fig. 1 (b)
Layer；The last depositing tungsten metal that formed in the trench after barrier layer as shown in Fig. 1 (c) is using as tungsten grid 103.And ISSG technique
The major defect of the BSG oxide skin(coating) of formation is that the BSG oxide skin(coating) in the drain selection area after the gate oxidation of the side BSG is blocked up.
In order to solve the defect, NH is generallyd use3Processing+high temperature oxidation process processing mode is to improve the BSG oxygen in drain selection area
Compound layer thickness, but this will lead to BSG oxide quality it is bad and have an adverse effect to chip Acceptance Test performance, simultaneously
It is found by the applicant that NH3Although BSG oxide skin(coating) that processing+high temperature oxidation process processing mode overcomes drain selection area is blocked up
The problem of, but will lead to BSG and generate connecting lead wire (CW) breakdown voltage Problem of Failure, this diffusion for being likely due to tungsten causes
's.
Summary of the invention
To solve the above-mentioned problems, the present invention provides the intermetallic compound protective layers and its shape in a kind of 3D NAND
At method, spread and forming a kind of intermetallic compound protective layer to prevent tungsten from passing through the BSG oxide in drain selection area
Into silicon substrate.
The purpose of the present invention is what is be achieved through the following technical solutions:
Intermetallic compound (IMC) protective layer forming method in a kind of 3D NAND is provided, following step is specifically included
It is rapid:
S1: the oxide structure of the bottom selection gate of drain selection unit is prepared on a semiconductor substrate, is then made
Standby Al2O3The laminated construction of gate blocks layer and TiN adhesion layer；
S2: IMC protective layer is formed on above-mentioned laminated construction；
S3: the deposits tungsten grid on the IMC protective layer；
Wherein the IMC layers is IMC HfW2Layer.
Further, above-mentioned IMC protective layer forming method forms above-mentioned IMC protective layer in step S2 and specifically includes: first
The co-deposited layer of hafnium Hf and tungsten W are formed, is then heated at high temperature above-mentioned co-deposited layer to form IMC layers.
Further, in above-mentioned IMC protective layer forming method, formed above-mentioned co-deposited layer chemical formula such as following formula (1) and
(2):
HfF4→Hf+F2 (1)
WF6→W+F2 (2)。
Further, in above-mentioned IMC protective layer forming method, the implementation temperature of above-mentioned high-temperature heating is greater than 1000 DEG C.
Further, in above-mentioned IMC protective layer forming method, the oxide of the bottom selection gate is prepared in step S1
Structure specifically includes: the bottom gate oxide of above-mentioned bottom selection gate is prepared using steam growth (ISSG) technique in situ；
The side gate oxide of above-mentioned bottom selection gate is prepared in the source electrode groove etched.
Further, in above-mentioned IMC protective layer forming method, above-mentioned Al is prepared using atomic layer deposition (ALD) technique2O3
Gate blocks layer.
Further, in above-mentioned IMC protective layer forming method, step S1 further comprises: selecting forming above-mentioned bottom
After the oxide structure of grid, using NH3Processing is handled with high temperature oxidation process.
Also provided is intermetallic compound (IMC) protective layer in a kind of 3D NAND, which includes being formed
Storage unit and drain selection unit on a semiconductor substrate, the IMC protective layer are formed in above-mentioned drain selection unit, should
Drain selection unit further comprises the bottom selection grid being made of bottom gate oxide and side gate oxide, in above-mentioned source electrode
It also successively include Al in the groove of selecting unit2O3Gate blocks layer, TiN adhesion layer and tungsten grid, in which: above-mentioned IMC layers of setting
Between above-mentioned TiN layer and tungsten grid, and this IMC layers is IMC HfW2Layer.
Further, in above-mentioned IMC protective layer, the IMC layers by including HfF4And WF6Gas preparation.
Further, in above-mentioned IMC protective layer, above-mentioned bottom gate oxide is that steam in situ grows (ISSG) oxidation
Object.
Further, in above-mentioned IMC protective layer, the oxide structure of bottom selection gate is via NH3Processing and high temperature
Oxidation technology processing.
The present invention has the advantages that by providing a kind of intermetallic compound in the bottom gate configuration in 3D NAND
Protective layer can prevent tungsten from passing through the BSG oxide in drain selection area and diffuse into silicon substrate, so that drain selection area
BSG oxide will not be blocked up, and can prevent tungsten spread and cause BSG structure generate connecting lead wire breakdown voltage failure ask
Topic.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 (a)~1 (c) shows the preparation work of bottom selection gate involved in 3D NAND technique in the prior art
Skill；
Fig. 2 (a)~2 (c) is the shape of the intermetallic compound protective layer in a kind of 3D NAND provided by present embodiment
At method；
Fig. 3 is HfW2Lattice structure；
Fig. 4 is IMC HfW2Layer diffuses to the barrier effect schematic diagram of silicon substrate to the tungsten in tungsten metal layer；
Fig. 5 is hafnium tungsten binary phase diagraml.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
Fig. 2 (a) -2 (c) shows the intermetallic compound in a kind of 3D NAND provided by the application embodiment and protects
The forming method of sheath, wherein the forming method includes:
S1: preparing the storage unit and BSG gate oxidation structure of 3D NAND on a semiconductor substrate, wherein utilizing original
The bottom gate oxide layers of position steam growth (ISSG) technique preparation bottom selection gate (BSG), and the source electrode formed in etching
The side gate oxide layers of BSG are prepared in groove；Then as shown in Fig. 2 (a), atomic layer deposition is utilized in source electrode groove
(ALD) technique forms high dielectric oxidation aluminium Al2O3Layer and be subsequently formed TiN sedimentary, so as to form Al2O3Gate blocks
The laminated construction 101 of layer and TiN adhesion layer.
Wherein due to there is a problem of that the BSG oxide skin(coating) in drain selection area is blocked up, in order to improve the thickness of BSG oxide skin(coating)
Degree, needs to implement NH after forming side gate oxide layers3Processing+high temperature oxidation process processing.
S2: in Al as shown in Fig. 2 (b)2O3With formation IMC layer 102 on TiN laminated construction 101.The IMC layer 102 utilizes two
Step process preparation, is initially formed metal co-deposition layer, then forms IMC structure through Overheating Treatment.
The lattice structure of IMC structure is tightly packed and has specific chemical bond, and the chemical bond is between metallic bond and covalently
Between key.Exactly because its specific lattice structure, therefore this compact continuous IMC layers can be effectively prevented metal diffusion,
Such as the diffusion of tungsten.It is not that any metal mixture can form IMC structure, the preparation of IMC structure must be according to heating power
Theory is realized.And in the 3D NAND structure, IMC layers of preparation are between TiN layer and tungsten layer, therefore IMC layers of the characteristic must
It must match with above-mentioned adjacent TiN layer, tungsten layer.By selection, since metal hafnium Hf and tungsten W has close atomicity,
The two has similar characteristic.In addition, being capable of forming HfW via processing between hafnium Hf and tungsten W2Intermetallic compound, HfW2Metal
Between compound lattice structure as shown in figure 3, its with compound cubic lattice structure so that the HfW2Intermetallic compound
It is capable of the diffusion of effectively barrier metal tungsten, it is shown in Figure 4.Therefore before tungsten gate deposition, hafnium Hf and tungsten W is selected to prepare
Form HfW2Intermetallic compounds layer.
S3: finally, the shown deposits tungsten grid 103 on the IMC layer of such as Fig. 2 (c).
In above-mentioned steps S2, in order to form IMC HfW2It may first have to form the co-deposited layer of hafnium Hf Yu tungsten W.Tool
For body, before forming tungsten sedimentary, HfF is utilized4、WF6The metal of hafnium Hf Yu tungsten W are formd with other auxiliary gas preparations
Co-deposited layer.Shown in the chemical formula wherein reacted such as following formula (1) and (2):
HfF4→Hf+F2 (1)
WF6→W+F2 (2)。
Then it needing to carry out high-temperature heat treatment to above-mentioned metal co-deposition layer, Fig. 5 shows the binary phase diagraml of Hf and W,
Abscissa is the component of Hf and W, and ordinate is the temperature value as unit of Kelvin.According to diagram, the Hf and W of different component
Metal is capable of forming body-centered cubic lattic (bcc) and close-packed hexagonal structure (hcp) under high-temperature process, and in specific components and
At a temperature of, it will be able to IMC HfW needed for forming the application2Structure.And as shown in the figure in order to form compact continuous IMC HfW2
Structure, the heat treatment must be implemented at 1000 DEG C or more.Shown in such as following formula of chemical formula at this time (3):
Hf+W→HfW2(3)。
3D NAND structure shown in Fig. 2 (c) is obtained using above-mentioned preparation method comprising: storage unit and source electrode select
Unit is selected, further includes side including the bottom gate oxide that ISSG technique is formed in the bottom selection grid of drain selection unit
Gate oxide also successively includes Al in the groove of drain selection unit2O3Gate blocks layer, TiN adhesion layer and tungsten grid, and
An IMC layers is provided between the TiN layer and tungsten grid, the IMC layers is HfW2Layer utilizes HfF4、WF6Gas is assisted with other
Body is formed.Due to being prepared for the IMC HfW in the 3D NAND structure2Layer, therefore in order to improve the thickness of BSG oxide skin(coating)
And implement NH3After processing+high temperature oxidation process processing, it still is able to utilize the IMC HfW2Layer effectively stops tungsten grid
In tungsten diffuse into silicon substrate so that the 3D NAND structure avoid generate connecting line Problem of Failure.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (10)
1. intermetallic compound (IMC) protective layer forming method in a kind of 3D NAND, which comprises the steps of:
S1: the oxide structure of the bottom selection gate of drain selection unit is prepared on a semiconductor substrate, is then prepared
Al2O3The laminated construction (101) of gate blocks layer and TiN adhesion layer；
S2: intermetallic compound protective layer (102) are formed on above-mentioned laminated construction (101)；
S3: the deposits tungsten grid (103) on the intermetallic compound protective layer (102)；
Wherein the intermetallic compound protective layer (102) is intermetallic compound HfW2Layer.
2. IMC protective layer forming method according to claim 1, which is characterized in that form above-mentioned IMC protection in step S2
Layer (102) specifically include: be initially formed the co-deposited layer of hafnium (Hf) Yu tungsten (W), then by above-mentioned co-deposited layer high-temperature heating from
And form IMC layers.
3. IMC protective layer forming method according to claim 2, which is characterized in that form the chemistry of above-mentioned co-deposited layer
Formula such as following formula (1) and (2):
HfF4→Hf+F2 (1)
WF6→W+F2 (2)。
4. IMC protective layer forming method according to claim 2, which is characterized in that the implementation temperature of above-mentioned high-temperature heating
For greater than 1000 DEG C.
5. IMC protective layer forming method according to any one of claims 1 to 3, which is characterized in that in step S1 described in preparation
The oxide structure of bottom selection gate specifically includes: preparing above-mentioned bottom using steam growth (ISSG) technique in situ and selects
The bottom gate oxide of grid；The side gate oxide of above-mentioned bottom selection gate is prepared in the source electrode groove etched.
6. IMC protective layer forming method according to any one of claims 1 to 3, which is characterized in that utilize atomic layer deposition
(ALD) technique prepares above-mentioned Al2O3Gate blocks layer.
7. IMC protective layer forming method according to any one of claims 1 to 3, which is characterized in that step S1 is further wrapped
It includes: after the oxide structure for forming above-mentioned bottom selection gate, using NH3Processing is handled with high temperature oxidation process.
8. intermetallic compound (IMC) protective layer in a kind of 3D NAND, which includes being formed on a semiconductor substrate
Storage unit and drain selection unit, the intermetallic compound protective layer be formed in above-mentioned drain selection unit, the source electrode
Selecting unit further comprises the bottom selection grid being made of bottom gate oxide and side gate oxide, in above-mentioned drain selection
It also successively include Al in the groove of unit2O3Gate blocks layer, TiN adhesion layer and tungsten grid, it is characterised in that: between above-mentioned metal
Compound protective layer is arranged between above-mentioned TiN layer and tungsten grid, and the intermetallic compound protective layer is intermetallic
Object HfW2Layer.
9. IMC protective layer according to claim 8, which is characterized in that the IMC layers by including HfF4And WF6Gas system
It is standby.
10. IMC protective layer according to claim 8 or claim 9, which is characterized in that above-mentioned bottom gate oxide is steam in situ
Grow (ISSG) oxide.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274042A (en) * | 1986-05-22 | 1987-11-28 | Mitsubishi Heavy Ind Ltd | Sliding member |
| CN103094246A (en) * | 2011-11-08 | 2013-05-08 | 台湾积体电路制造股份有限公司 | Post-passivation interconnect structure and method of forming the same |
| CN104716029A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN106716624A (en) * | 2014-09-24 | 2017-05-24 | 高通股份有限公司 | Metal-gate with an amorphous metal layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8318596B2 (en) * | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274042A (en) * | 1986-05-22 | 1987-11-28 | Mitsubishi Heavy Ind Ltd | Sliding member |
| CN103094246A (en) * | 2011-11-08 | 2013-05-08 | 台湾积体电路制造股份有限公司 | Post-passivation interconnect structure and method of forming the same |
| CN104716029A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN106716624A (en) * | 2014-09-24 | 2017-05-24 | 高通股份有限公司 | Metal-gate with an amorphous metal layer |
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