JPS618942A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS618942A
JPS618942A JP12976584A JP12976584A JPS618942A JP S618942 A JPS618942 A JP S618942A JP 12976584 A JP12976584 A JP 12976584A JP 12976584 A JP12976584 A JP 12976584A JP S618942 A JPS618942 A JP S618942A
Authority
JP
Japan
Prior art keywords
recess
thin film
substances
film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12976584A
Other languages
Japanese (ja)
Inventor
Hideaki Itakura
秀明 板倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12976584A priority Critical patent/JPS618942A/en
Publication of JPS618942A publication Critical patent/JPS618942A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To contrive the improvement in productivity by ensuring a burying sufficiently by a method wherein a thin film is formed on a semiconductor substrate and an aperture is opened on said thin film after which a recess communicating with said aperture is formed on the semiconductor substrate and particulate insulating substances are stuck to the overall surface under that condition and then the particulate insulating substances on a surface of the thin film are removed and are filled in the recess and said substances are heated to fill the recess. CONSTITUTION:As shown in FIG. (a), a thin film 9 (e.g. a thermal oxidation Si film and a polysilicon film on that) is formed on a surface of a semiconductor substrate 1 and a photoresist film 2 is formed over the overall surface. Then an aperture 2a is formed in the necessary position. Etching of the substrate 1 is done to the necessary depth and the photoresist film 2a is removed. Then a recess 3 is formed under the condition as shown in FIG. (c) and particulate insulating substances 10 (e.g. SiO2 powder) are stuck to the overall surface. Subsequently, the particulate insulating substances are contained only in the recess 3 and the semiconductor substrate 1 is put in the atmosphere which is so heated that the substances 10 can be fused. The processes of the second overall adhesion of particulate insulating substances 10, removal of the substances 10 on the surface, containing those in the recess 3 as shown in FIG. (g), and fusing the substances are repeated. Then the thin film 9 is subjected to the overall etching to be removed and the burying process is finished.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明け、半導体装置の製造工程において、半導体基
板に形成された凹Sを絶縁物質で埋める、半導体装置の
製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, in which a recess S formed in a semiconductor substrate is filled with an insulating material in a manufacturing process of the semiconductor device.

〔従来技術〕[Prior art]

半導体基板の表面に、例えば左右の素子間又は領M、間
を分離するため、凹部を形成する。この凹部を絶縁物で
埋め、空所部をなくする処理をし、素子特性が低下しな
いようにしている。
A recess is formed on the surface of the semiconductor substrate, for example, in order to separate left and right elements or regions M. These recesses are filled with an insulator to eliminate voids and prevent device characteristics from deteriorating.

この種の従来の半導体装置の製造方法は、第1図(a)
〜(f)に工程順に示す基板の要部断面図のようにして
いた。まず、第1図(a)に示すように、半導体基板(
11表面にホトレジスト膜(2)を形成し、通常のマス
クパターン転写工程を経て、ホトレジスト膜(2)のう
ち、所要の位置の部分を除去し開口部(2a)を形成す
る。このホトレジスト膜(2)ヲマスクとして半導体基
板filのエツチングを所要の深さまで行い、この後5
.ホトレジスト膜(2)を除去すると、第1図(b)の
ように凹5(3)が形成される。つづいて、この凹部を
絶縁材料で埋めるため、化学的気相成長法により、第1
図(C)に示すように、全面に絶縁膜(4)(例えば酸
化シリコン膜)を形成する。ついで、例えば、反応性イ
オンの直進性を利用したドライエツチング法、いわゆる
反応性イオンエツチング法により全面をエツチングし、
第1図釦のように、凹部(3)の外の絶縁膜(4)を除
去すると、凹部(3)の側面に残留絶縁膜(5)が残る
。このような残留絶縁膜(5)によって凹部(3)が埋
まらない場合には、第1図(e)に示すように、さちに
、第2回目の絶縁膜(6)を形成しt後、再び全面をエ
ツチングする。
The conventional manufacturing method of this type of semiconductor device is shown in FIG. 1(a).
-(f) are cross-sectional views of the main parts of the substrate shown in the order of steps. First, as shown in FIG. 1(a), a semiconductor substrate (
A photoresist film (2) is formed on the surface of the photoresist film (2), and through a normal mask pattern transfer process, a portion of the photoresist film (2) at a desired position is removed to form an opening (2a). Using this photoresist film (2) as a mask, the semiconductor substrate fil is etched to the required depth, and then
.. When the photoresist film (2) is removed, a recess 5 (3) is formed as shown in FIG. 1(b). Next, in order to fill this recess with an insulating material, a first
As shown in Figure (C), an insulating film (4) (for example, a silicon oxide film) is formed over the entire surface. Then, the entire surface is etched by, for example, a dry etching method that utilizes the linearity of reactive ions, so-called reactive ion etching method.
As shown by the button in FIG. 1, when the insulating film (4) outside the recess (3) is removed, a residual insulating film (5) remains on the side surfaces of the recess (3). If the recess (3) is not filled with such a residual insulating film (5), as shown in FIG. 1(e), immediately form a second insulating film (6) and then Etch the entire surface again.

この絶縁膜形成とエツチングを繰返すことにより、第1
図(f)に示すように、埋込み絶縁層(7)で凹部(3
)を埋めることができる。
By repeating this insulating film formation and etching, the first
As shown in Figure (f), the buried insulating layer (7) has a recess (3).
) can be filled in.

しかしながら、上記従来の方法では、工程′が複雑で生
産性が低く、また、第1図(f)に示すようへ4   
 埋込み絶縁層(″)内に空洞(8)を生じ・素子特性
を悪化させるおそれがあった。さらに、同一基板面内に
幅が種々の大きさの凹部が混在する場合、埋込み完了ま
での時間に差がでる。このため、幅の大きい凹部は幅の
小さい凹部より埋込みにくくなる。
However, in the above conventional method, the process ' is complicated and the productivity is low.
There was a risk of creating a cavity (8) in the buried insulating layer ('') and deteriorating the device characteristics.Furthermore, if there are concave portions of various widths on the same substrate surface, the time required to complete the filling may be reduced. Therefore, a recess with a large width is more difficult to fill than a recess with a small width.

そのうえ、凹部の幅が極めて狭く、かつ、深さが幅に比
べてかなり大きい場合は、凹部内に膜形成を行うことが
困難となり、埋込みができないことがあった〇 〔発明の概要〕 この発明け、半導体基板とに薄膜を形成し、写真製版と
エツチング処理により薄膜を開口し連通ずる凹部を半導
体基板に形成し、この状態の全表面に粒状絶縁物質を付
着させ、表面の粒状絶縁物質を除去して凹部内に充てん
し、粒状絶縁物質を加熱溶融し凹部を埋めるようにして
いる。こhにより、薄膜の厚さ分だけ凹部に粒状絶縁物
質の量が多く収容でき、粒状絶縁物質の充てんと溶融の
繰返し回数が少なくて早く埋めることができ、埋込みが
確実に施され、生産性が向上され、まt、同一平面にあ
る各凹部の大きさや形状が異なって   酬も一様に確
実に埋込むことができる、半導体装置の製造方法を提供
することを目的としている。
Furthermore, if the width of the recess is extremely narrow and the depth is considerably larger than the width, it becomes difficult to form a film in the recess, and embedding may not be possible. Next, a thin film is formed on the semiconductor substrate, a recess is formed in the semiconductor substrate through which the thin film is opened and communicated by photolithography and etching, and a granular insulating material is attached to the entire surface of this state, and the granular insulating material on the surface is removed. The granular insulating material is removed and filled into the recess, and the granular insulating material is heated and melted to fill the recess. As a result, a large amount of granular insulating material can be accommodated in the recess corresponding to the thickness of the thin film, and the number of repetitions of filling and melting the granular insulating material can be reduced, allowing for faster filling, ensuring reliable embedding, and increasing productivity. It is an object of the present invention to provide a method for manufacturing a semiconductor device, in which recesses of different sizes and shapes on the same plane can be filled uniformly and reliably.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例による半導体装置の製造方法
を、第2図(a)〜(1)に工程順に示す基板の要部断
面図により説明する。まず、第2図(a)に示すように
、半導体基板fll 表面に薄膜(9)(例えば熱酸化
シリコン膜及びその上に多結晶シリコン膜)を形成する
。この薄膜(9)ハ後で形成される凹部(3)の基板(
11表面よりある高さを保つためのもので、用済後のエ
ツチング除去の容易である材料を用いる。つづいて、第
2図(b)のように、全面にホトレジスト膜(2)膜形
成し、通常のマスクパターン転写工程を経て、ホトレジ
スト膜(2)の所要の位置に開口部(2&)を形成する
Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to sectional views of main parts of a substrate shown in the order of steps in FIGS. 2(a) to 2(1). First, as shown in FIG. 2(a), a thin film (9) (for example, a thermally oxidized silicon film and a polycrystalline silicon film thereon) is formed on the surface of the semiconductor substrate fl1. This thin film (9) is then formed on the substrate (3) of the recess (3).
11 to maintain a certain height above the surface, and is made of a material that can be easily removed by etching after use. Next, as shown in FIG. 2(b), a photoresist film (2) is formed on the entire surface, and openings (2&) are formed at desired positions in the photoresist film (2) through a normal mask pattern transfer process. do.

このホトレジスト膜(2)ヲマスクとして、薄膜(9)
を例えばフレオン系ガスを用いたドライエツチング法に
よりエツチングし関口部(9a) (鎖線で示す)を形
成する。これらホトレジスト膜(2)と薄膜(9)とを
マスクとして半導体基板fl+のエツチングを所要の深
さまで行い、後、ホトレジスト膜(2)を除去すると、
第2図(Q)に示す状態で凹部(3)が形成される。
A thin film (9) is used as a mask for this photoresist film (2).
is etched by, for example, a dry etching method using a Freon gas to form a Sekiguchi portion (9a) (indicated by a chain line). Using these photoresist film (2) and thin film (9) as masks, the semiconductor substrate fl+ is etched to the required depth, and then the photoresist film (2) is removed.
A recess (3) is formed in the state shown in FIG. 2(Q).

この後、第2図(+1) K示すように、粒状絶縁物質
(10) (例えは二酸化シリコン粉末)を全面に付着
させる。ついで、遠心分離法あるいけ空気吹付は法など
の方法により、薄膜(9)面の粒状絶縁物質(10)を
除去して第2図(e)のように、粒状絶縁物質を凹部(
3)のみに収まるようにする。つぎに900℃以上で粒
状絶縁物質(lO)が溶融する程度に加熱さねた雰囲気
中に、半導体基板(11を置くと、粒状絶縁物It f
101場合、1回の付着及び溶融のみでは凹部(3)を
十分に埋込めないため、粒状絶縁物質(lO)の2回目
の全面付着及び表面の粒状絶縁物質(10)を除去して
第2図(−のように凹部(31VC収容し、溶融する工
程を繰返すことにより、第2図(h)に示すように、凹
部(3)内金部を埋込み絶縁層(121で埋められる。
Thereafter, as shown in FIG. 2(+1)K, a granular insulating material (10) (for example, silicon dioxide powder) is deposited on the entire surface. Next, the granular insulating material (10) on the surface of the thin film (9) is removed by a method such as centrifugation or air blowing, and the granular insulating material is placed in the recesses (as shown in FIG. 2(e)).
3). Next, when the semiconductor substrate (11) is placed in an atmosphere heated to a temperature of 900° C. or higher to the extent that the granular insulating material (lO) melts, the granular insulating material It f
In the case of No. 101, the recess (3) cannot be filled sufficiently with one deposition and melting, so a second deposition is performed on the entire surface of the granular insulating material (10) and the granular insulating material (10) on the surface is removed. By repeating the step of accommodating VC in the recess (31) and melting it as shown in the figure (-), the metal part inside the recess (3) is filled with a buried insulating layer (121) as shown in FIG. 2(h).

第2図(g)のように、薄膜(9)の開口部(9a)に
より、凹部(3)の基板(1)表面より高い位置まで、
粒状絶縁物質を満たすことができ、第2図(h)のよう
に、加i@により溶融しt後の埋込み絶縁層口21の上
面を基板(,11の表面にそろえることができる。こう
してから、第2図(1)のように、薄膜(9)を全面エ
ツチング除去して埋込み工程が完了する口 上記薄膜(9)の膜厚け、粒状絶縁物質(10)の加熱
溶融による占有容積の減少割合によって決まるものであ
る。この割合をもとにし、凹部(3)内で溶融により形
成された埋込み絶縁層(121の上面が基板(11表面
と同一高さになるための、粒状絶縁物質(10)の所要
量が収容されるように、薄膜(9)の膜厚を設定してお
く。
As shown in FIG. 2(g), the opening (9a) of the thin film (9) allows the recess (3) to reach a position higher than the surface of the substrate (1).
The upper surface of the buried insulating layer opening 21 can be aligned with the surface of the substrate (11) after being melted by adding t, as shown in FIG. 2(h). As shown in FIG. 2 (1), the embedding process is completed by etching away the entire surface of the thin film (9). It is determined by the rate of decrease. Based on this rate, the granular insulating material is The thickness of the thin film (9) is set so that the required amount of (10) is accommodated.

なお、上記実施例では、粒状絶縁物質(lO)の付着は
、1回目と2回目以降との付着工程では同一の粒径のも
のを用いたが、2回目以降でけ粒径を順次小さくしても
よい。
In the above example, the particle size of the insulating material (lO) was the same in the first and second and subsequent adhesion processes, but the particle size was gradually decreased from the second time onwards. It's okay.

また、上記実施例では粒状絶縁物質+101が球状のも
のを示したが、これに限らず、立方体、八面体I   
 など多面体であってもよい・なぶまた、薄膜(9ンの
材料きしては、二酸化シリコンを用いてもよい。
Further, in the above embodiment, the granular insulating material +101 is spherical;
It may also be a polyhedron such as a polyhedron.Also, silicon dioxide may be used as a thin film material.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明の方法によれば、半導体基板上
に薄膜を形成し、写真製版とエツチングにより薄膜を開
口しこれと連通ずる凹部を半導体基板に形成し、この状
態の全表「に粒状絶縁物質を付着し、薄膜表面の粒状絶
縁物質を除去して凹部内に充てんし、粒状絶縁物質を加
熱により溶融し凹部を埋めるようにしたので、薄膜の開
口部により凹部に充てんする粒状絶縁物質の量が多く収
容でき、粒状絶縁物質の充てんと溶融の繰返し回数が少
なくてよく、埋込みが十分で確実にできる。
As described above, according to the method of the present invention, a thin film is formed on a semiconductor substrate, a recess is formed in the semiconductor substrate by opening the thin film by photolithography and etching, and communicating with the recess, and the entire table in this state is The granular insulating material is attached, the granular insulating material on the surface of the thin film is removed to fill the recess, and the granular insulating material is melted by heating to fill the recess, so the granular insulation fills the recess through the opening of the thin film. A large amount of material can be accommodated, the number of repetitions of filling and melting the granular insulating material can be reduced, and embedding can be performed sufficiently and reliably.

また、工程が簡単になり生産性が向上され、同一平面に
ある凹部の大きさや形状が異なっても、一様に確実に埋
めることができる。
Furthermore, the process is simplified and productivity is improved, and even if the recesses on the same plane have different sizes and shapes, they can be filled uniformly and reliably.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の製造方法を工程順に示す基
板要部の断面図、第2図はこの発明の一実施例による半
導体装置の製造方法を、工程順に示   、貫す基板要
部の断固図である。 1・・・半導体基板、2・・・ホトレジスト膜、3・・
・凹部、9・・・薄膜、9a・・・開口部、10・・・
粒状絶縁物質、11・・・充てん絶縁膜、12・・・埋
込み絶縁層なお、図中同一符号は同−又は相当部分を示
す。
FIG. 1 is a sectional view of a main part of a substrate showing a conventional method for manufacturing a semiconductor device in the order of steps, and FIG. 2 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. This is a decisive picture. 1... Semiconductor substrate, 2... Photoresist film, 3...
・Concave portion, 9... thin film, 9a... opening, 10...
Particulate insulating material, 11... Filled insulating film, 12... Buried insulating layer Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板の表面に薄膜を形成し、写真製版とエ
ッチング処理により、上記薄膜に開口部を形成しこれに
連通し上記半導体基板に凹部を形成し、上記薄膜の全表
面及び凹部に粒状絶縁物質を付着させ、薄膜面の粒状絶
縁物質を除去して上記凹部に充てんし、この充てんされ
た粒状絶縁物質を加熱溶融し凹部を埋めることを特徴と
する半導体装置の製造方法。
(1) Form a thin film on the surface of the semiconductor substrate, form an opening in the thin film by photolithography and etching, and form a recess in the semiconductor substrate communicating with the opening, and form grains on the entire surface of the thin film and in the recess. 1. A method for manufacturing a semiconductor device, comprising: depositing an insulating material, removing particulate insulating material on the thin film surface to fill the recess, and heating and melting the filled insulating material to fill the recess.
(2)粒状絶縁物質は二酸化シリコン粉末からなる特許
請求の範囲第1項記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the granular insulating material is made of silicon dioxide powder.
(3)薄膜は熱酸化シリコン膜とこの上面の多結晶シリ
コン膜とからなる特許請求の範囲第1項又は第2項記載
の半導体装置の製造方法。
(3) A method of manufacturing a semiconductor device according to claim 1 or 2, wherein the thin film is composed of a thermally oxidized silicon film and a polycrystalline silicon film on the upper surface thereof.
(4)薄膜は二酸化シリコンからなる特許請求の範囲第
1項又は第2項記載の半導体装置の製造方法。
(4) A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the thin film is made of silicon dioxide.
JP12976584A 1984-06-23 1984-06-23 Manufacture of semiconductor device Pending JPS618942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12976584A JPS618942A (en) 1984-06-23 1984-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12976584A JPS618942A (en) 1984-06-23 1984-06-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS618942A true JPS618942A (en) 1986-01-16

Family

ID=15017648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12976584A Pending JPS618942A (en) 1984-06-23 1984-06-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS618942A (en)

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