JP2002368220A - Semiconductor device and power system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the ON-resistance and capacity of a longitudinal power MOSFET and to improve the efficiency of a DC-DC power circuit. SOLUTION: A longitudinal power MOSFET has gate electrodes 6 and 7, a gate oxide film 5, a source region 4, and a channel diffusion region 3 on a silicon groove formed in a 1st surface of a semiconductor chip. In this MOSFET, a low capacity and low on-voltage trench power MOSFET is actualized, by making minimum width (L3) of a gate electrode layer region surrounded by the channel diffusion region 20% larger than maximum width (L2) of the gate electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency power semiconductor device, and more particularly to a high-frequency power MOSFE.
The present invention relates to reducing the on-resistance of T and increasing the efficiency of a system using the same.

[0002]

2. Description of the Related Art Conventionally, DC / DC of personal computers, VRMs, etc.
Vertical power MO with excellent low on-resistance for power circuit
Although SFETs were mainly used, as the frequency of power supply circuits has increased, not only low on-resistance of power MOSFETs, which has been required to improve power supply efficiency, but also reduction of feedback capacitance has been required. It has become. For example, Buck
In the case of a type power supply circuit, it is necessary to reduce the feedback capacitance in order to increase the efficiency in order to reduce the switching loss of the upper power MOSFET.

A vertical power MOS having a trench gate
Although there is a problem that the FET is suitable for reducing the on-resistance, it is difficult to reduce the feedback capacitance because fine processing is required to reduce the capacitance immediately below the gate.

On the other hand, a trench power MOSFET using a metal for the gate is also disclosed since the gate resistance must be reduced by increasing the driving frequency of the power MOSFET in order to improve the efficiency of the DC / DC power supply circuit.

[0005]

The use of metal or silicide as the gate electrode to reduce the gate resistance has been studied, but in order to improve the efficiency of the DC / DC power supply, in particular, the feedback capacitance must be reduced at the same time. There was not enough consideration on the structure to be achieved.

[0006] In the prior art power transistor having a drain withstand voltage of about 30 V or less, a method and a mounting method for reducing the resistance of the low-resistance substrate have not been sufficiently studied. Further, studies for preventing the operation of the parasitic diode of the power MOSFET to improve the efficiency of the power supply circuit and the like have not been sufficient.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and relates to a feedback capacitance and an on-resistance of a power semiconductor device, and improves the efficiency of a circuit in which the semiconductor device is used. It is to provide a method.

[0008]

The outline of the semiconductor device of the present invention is as follows. (1) A trench gate structure in which the minimum width of the gate electrode layer region sandwiched between the channel diffusion layers is smaller than the maximum width of the gate electrode by 20% or more. (2) At least a part of the gate electrode portion is made of a metal layer (or a metal compound layer), and the gate electrode portion region sandwiched by the channel diffusion layers is larger than the maximum width of the gate electrode portion made of the metal or the metal compound layer. A trench gate structure having a minimum width narrower by 20% or more is used. (3) At least 80% of the gate electrode side of the gate oxide film portion in contact with the channel region has a trench gate structure in which a polycrystalline silicon layer is a boundary. (4) A structure in which at least a part of the gate electrode portion protrudes above the upper surface of the source region on the semiconductor main surface. (5) The thickness of a semiconductor chip having a built-in vertical power MOSFET with a withstand voltage between drain and source of 30 V or less is set to 60 μm.
Do the following. (6) In a vertical power MOSFET having a drain-source withstand voltage of 30 V or less, at least a part of a semiconductor chip of a low-resistance drain substrate is etched from a back surface, and a metal or a metal compound is put in a groove. The effective thickness of the substrate is set to 20 μm or less. (7) A power MOS in which the ratio of the width of the gate electrode layer region sandwiched by the channel diffusion layers to the interval between the trench grooves is small.
The FET is used as an element for the lower arm (for synchronous rectification) of the DC / DC power supply circuit, and the power MOSFET having a larger ratio of the width of the gate electrode layer region is used as an element for the upper arm (for switch) of the power supply circuit. .

The features of the DC / DC converter of the present invention are as follows. (8) The power MOSFET with the smaller cell pitch is used as a lower arm (for synchronous rectification) element of the power supply circuit,
The power MOSFET with the larger cell pitch is DC / D
Used as an element for the upper arm (for switch) of the C power supply circuit. (9) An n-channel MOSFET for driving the vertical power MOSFET to be cut off is formed on the same chip as the vertical power MOSFET, and is formed in the semiconductor chip to turn on the vertical power MOSFET. This is realized by applying a voltage to a certain external gate terminal. To turn off the vertical power MOSFET, an n-channel MOSF
The semiconductor device realized by turning on ET is DC
/ DC power supply circuit.

As described above, according to the present invention, a power semiconductor device such as a power transistor can be reduced in loss and capacity.
Further, since the adverse effect due to the parasitic impedance can be reduced, the efficiency of the power supply circuit using the present power transistor can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power supply according to the present invention will be described in detail with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a sectional view of this embodiment. A silicon groove is formed on the n-type epitaxial region 2 formed above the low-resistance n-type semiconductor substrate 1;
Gate electrodes 6 and 7 are provided on the silicon groove, and a gate oxide film 5 is provided along the silicon groove. here,
The gate electrode 6 is made of a polycrystalline silicon layer, and the gate electrode 7 is a metal or a metal compound. As a specific example, tungsten or tungsten silicide is used.

An n-type source region 4, a p-type channel diffusion region 3, and an n-type epitaxial region 2 serving as a drain are provided outside the silicon groove and adjacent to the gate oxide film 5.

Reference numeral 12 denotes a metal electrode, and a region 13 is a drain pad (external drain terminal). Also, 14
Is a back electrode used as an external source terminal. 8,9
Is an insulating film, and the insulating film 9 is a sidewall insulating layer used to dig silicon in the source contact region deeper than the source region 4. Reference numerals 11 and 10 denote low-resistance p-type regions in which boron is implanted with different ion energies in order to lower the resistance of the channel diffusion region 3. The ohmic connection between the source electrode and the channel diffusion layer is ensured by the low resistance diffusion region, and the operation of a parasitic npn transistor constituted by the source region 4, the channel diffusion region 3 and the n-type epitaxial region 2 as the drain region is performed. Can be prevented and the breakdown strength can be improved.

In this embodiment, the silicon etching conditions are selected so that the shape of the silicon groove becomes narrower as going downward. In the example of this embodiment, L1 is 1 μm, L2 is 0.5 μm, and L3 and L4 are 0.1 μm. Therefore,
The minimum width (L3) of the gate electrode layer region sandwiched by the channel diffusion regions 3 is smaller than the maximum width (L2) of the gate electrodes 6 and 7 by 20% or more (80% narrower in the present embodiment). For this reason, the capacitance between the drain and the gate, which strongly affects the efficiency of the DC / DC power supply, can be reduced.

In the semiconductor device of this embodiment, the dimension L3 which affects the capacity between the drain and the gate is shortened without reducing the mask dimension of the trench gate. Further, a metal or a metal compound is provided on a part of the gate electrode, and the gate electrode is formed as wide as 0.5 μm. Therefore, the gate resistance can be reduced without using fine processing, and the capacitance between the drain and the gate can be reduced.

Further, in order to avoid an electric field strength increase at the bottom of the gate electrode and a decrease in breakdown voltage and a decrease in reliability of the gate oxide film, the thickness of the gate oxide film at the bottom is partially increased by 20% or more. Further, the low-resistance p-type region 10 is formed deeper than the channel diffusion region 3 so as to be diffused to near the bottom of the trench.

Further, as means for further reducing the resistance, n
By reducing the thickness Z of the mold substrate 1 to reduce the thickness of the semiconductor chip to 60
μm or less. This means that the power MOSFET has a withstand voltage specification between drain and source of 30 V or less and an on-resistance specification of 3 m.
It is effective when aiming at Ω or less. The reason for this is that the low-resistance substrate 1 is currently limited to silicon with a thickness of about 2 to 3 mΩcm, and this resistance is reduced from the thick silicon of about 200 μm used in the conventional power device to about 60 μm.
If not less than m, the balance of the on-resistance component is poor. Furthermore, when a substrate such as SiC, whose substrate resistance is unlikely to decrease, is used, the resistivity of the substrate 1 is 3 times higher than that of silicon.
Since the SiC substrate is about 60 μm or less, an effective specification is an on-resistance specification of 10 mΩ or less.

Embodiment 2 FIG. 2 is a sectional view of a semiconductor device according to the present embodiment. In the case of FIG. 1, the gate electrode layer 6 is formed thicker instead of the width of the groove, but in the present embodiment shown in FIG. A region 7 of the compound layer partially enters the silicon groove. Therefore, in the present embodiment, the gate resistance is lower than that in FIG. Others are the same as the first embodiment.

<Embodiment 3> FIG. 3 is a sectional view of a semiconductor device according to this embodiment. In the case of FIG. 3, the shape of the silicon groove is approximately the same from the surface to the bottom, but the region of the metal or metal compound layer 7 is formed outside the silicon etching groove and wider than the silicon etching groove. L3 is 0.3 μm, whereas L2 is 0.5 μm.
That is, the width of the gate electrode layer region sandwiched by the channel diffusion layers can be reduced by 40% as compared with the width of the metal or metal compound layer of the gate electrode portion.

Therefore, in this embodiment, although the capacitance between the drain and the gate is not reduced as much as in the first embodiment, it is possible to reduce the gate resistance and the capacitance between the drain and the gate. It is to be noted that increasing the thickness of the bottom gate oxide film also improves the withstand voltage because the curvature of the bottom is improved, so that the drain-source withstand voltage does not easily deteriorate without increasing the thickness of the gate oxide film at the bottom of the gate. is there. When only the bottom gate oxide film is thickened in this structure, the drain-gate capacitance can be further reduced. Also, it is possible to prevent breakdown voltage and characteristic deterioration between the drain and the source and between the drain and the gate. Others are the same as the first embodiment.

<Embodiment 4> FIG. 4 is a sectional view of a semiconductor device according to this embodiment. In FIG. 4, the gate electrode layer 6 made of polycrystalline silicon is formed only in the groove by extending the etch back time, and the gate electrode layer 7 which is a metal or metal compound layer is not buried deeper than the vicinity of the source region 4. It is like that. For this reason, although the reduction of the gate resistance is slightly sacrificed, the dimension L2 can be shortened, so that the on-resistance can be reduced. Others are the same as the first embodiment.

<Embodiment 5> FIG. 5 is a sectional view of a semiconductor device according to the present embodiment. In the case of FIG. 5, the entire gate electrode layer is a metal or metal compound layer 7. This embodiment is characterized in that the gate resistance is sufficiently reduced. In this embodiment, as a method of lowering the resistance of the low-resistance n-type semiconductor substrate 1, a silicon groove is formed and a metal such as copper or aluminum or a metal compound 20 is buried therein. In this embodiment, the resistance is reduced by using the metal or the metal compound 20 for the portion where the silicon thickness is not sufficiently reduced.
In the present embodiment, the effective thickness U of the semiconductor substrate 1 (the portion of the semiconductor substrate 1 where the metal or metal compound 20 does not enter) is used.
Can be set to 20 μm or less.
This is effective in reducing the substrate resistance component of a power transistor, such as C, whose substrate resistance is unlikely to decrease.

In this embodiment, the metal or metal compound 20 is buried in the fine etching groove. However, only a part of the silicon chip (immediately below the active area) is etched so that the silicon chip is not easily broken, and the soldering is performed at the time of mounting. The same effect can be obtained by filling with a conductive adhesive or a metal or a metal compound. Others are the same as the first embodiment.

Embodiment 6 FIG. 6 is a circuit diagram of a power semiconductor device according to this embodiment. The power semiconductor device of the first embodiment can be used for the upper arm power MOSFET 401 chip, the lower arm power MOSFET 402 chip, or both. The circuit of this embodiment is a Buck type power supply circuit which is a non-insulated DC / DC power supply circuit. The input voltage Vin of about 48V to 5V is lowered to output voltage V of 5V to 0.5V.
This is a circuit for obtaining out. In FIG. 6, reference numeral 311 denotes a load such as a microprocessor, 309 denotes an inductance,
10 is a capacitor. Reference numerals 401 and 402 denote semiconductor chips with built-in power MOSFETs 100 and 200. In this embodiment, n-channel MOSFETs 103 and 2 are used.
03 and polycrystalline silicon diode 10 for gate protection
7 and 209 are also shown. The external drain terminals are 501 and 505, and the external source terminals are 502 and 50.
6. External gate terminals are 509 and 510, power MOSF
External input terminal 5 to shut off ET100, 200
03,507 is provided.

In this embodiment, the n-channel MOSFET 20
3, a polycrystalline silicon diode 107 for gate protection,
209 is also shown. Reference numeral 403 is a control IC, 303 and 314 are switches for turning on the power MOSFET 100, and 313 is a power MOSFET.
This is a switch for turning off 100. Reference numerals 315 and 317 are switches for turning on the power MOSFET 200, and 316 is a switch for turning on the power MOSFET 200.
307 is a switch for turning off the power MOSF
Step-up circuits for controlling the gate voltage of the ET to be higher than Vin, 302 and 301 are diodes and capacitors for a bootstrap circuit. Here, the upper arm power M
If a power supply higher than Vin can be used to turn on the OSFET 100, 302, 301, and 307 can be omitted. Reference numerals 509, 518, 511, 512, 51
0 is an external terminal of the control IC.

When the vertical power MOSFET of the present invention is used as the power MOSFET 401 chip for the upper arm, the power supply efficiency can be improved because the feedback capacitance is small and the on-resistance is low. When the vertical power MOSFET of the present invention is used as the lower arm power MOSFET 401 chip, the feedback capacitance is small, so that when the drain voltage increases sharply (when 200 turns off and 100 turns on) The self-turn-on malfunction in which the voltage of the internal gate terminal coupled due to the capacitance between the gates increases and the power MOSFET is turned on even when the power MOSFET is cut off by an external circuit can be prevented, and the loss can be reduced.

Further, n-channel MOSFETs 103 and 2
In the case where 03 is incorporated on the same chip as the power MOSFETs 100 and 200, the parasitic gate impedance can be reduced, so that the power MOSFETs 100 and 200 can be accurately turned off even if the gate drive frequency increases. Therefore, the output voltage Vout can be stabilized and the output current flowing to the load can be stabilized, and the efficiency of the power supply can be improved.

Although not shown in FIG. 6, the power M
The gates of the OSFETs 100 and 200 and the n-channel MO
Between the drains of the SFETs 103 and 203 or between the sources of the n-channel MOSFETs 103 and 203 and the power M
When a polycrystalline silicon diode is connected between the source of the OSFET 100 and the source of the OSFET 200, even if the drain-body of the power MOSFET is forward-biased, the power MOSF
ET100, 200 and n-channel MOSFET 103,
The operation of the parasitic npn transistor during the period 203 can be prevented.

In the DC / DC power supply circuit of this embodiment, the width of the gate electrode layer region sandwiched by the channel diffusion layers (L3 in FIG. 1) is larger than the interval between the trenches of the power MOSFET (L1 in FIG. 1). ) Power MOSF with small ratio
ET for lower arm of power supply circuit (for synchronous rectification) 200
By using a power MOSFET having a larger ratio of the width of the gate electrode layer region (L3 in FIG. 1) as the upper arm (switch) element 100 of the power supply circuit, the power supply efficiency is improved. This is because it is necessary to use an element having a low product of the feedback capacitance and the on-resistance in addition to the on-resistance for the element for the upper arm in order to improve the efficiency, and in the case of the element for the lower arm, the feedback capacitance is large. Therefore, it is not necessary to cause self-turn-on, but it is necessary that the on-resistance is lower than the capacitance in order to increase the efficiency of the power supply.

For the same reason, the cell pitch (L in FIG. 1)
1) Use the smaller power MOSFET as the lower arm (synchronous rectification) element 200 of the power supply circuit and use the larger power MOSFET as the upper arm (switch) element 100 of the power supply circuit. This improves power supply efficiency.

The lower arm (for synchronous rectification) element 20
It is desirable to reduce the loss of the parasitic diode by diffusion of heavy metal such as gold or platinum, or lifetime control by irradiation of electron beam, proton or helium.

As described above, the present invention has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. .

For example, the transistor is a power MOSFET.
It is not limited to T, but may be a junction field effect transistor, SIT or MESFET. Further, the above description has mainly been given of the case where the present invention is applied to a DC / DC power supply. However, the present invention is not limited to this and can be applied to a power supply circuit of another circuit.

[0035]

As described above, according to the present invention,
A power MOSFET with low capacitance and low on-resistance can be realized.
This is effective for improving the efficiency of the DC / DC power supply device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view of the power semiconductor device according to the first embodiment.

FIG. 4 is a sectional view of a power semiconductor device according to a second embodiment.

FIG. 5 is a sectional view of a power semiconductor device according to an embodiment of Example 3;

FIG. 6 is a circuit diagram of a power semiconductor device according to a fourth embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 low-resistance n-type semiconductor substrate 2 n-type epitaxial region 3 channel diffusion region 4 source region 5 gate oxide film 6 gate electrode layer (polycrystalline silicon layer) 7
... Gate electrode layer (metal or metal compound), 10, 11
... low resistance p-type region, 13 ... drain pad, 14 ... back electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822 H02M 3/155 T 27/04 H01L 27/04 B H02M 3/155 H (72) Inventor Takayuki Iwasaki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference)

Claims (16)

[Claims] 1. A gate electrode is provided on a silicon groove formed on a first surface of a semiconductor chip, a gate oxide film is provided along the silicon groove, and is adjacent to the gate oxide film outside the silicon groove. A source region of the first conductivity type, a channel diffusion region of the second conductivity type, and a drain region of the first conductivity type, and a gate electrode layer sandwiched between the channel diffusion layers as compared with a maximum width of the gate electrode. A semiconductor device, wherein the minimum width of the region is at least 20% narrower. 2. A gate electrode is provided on a silicon groove formed on a first surface of a semiconductor chip, a gate oxide film is provided along the silicon groove, and is adjacent to the gate oxide film outside the silicon groove. A source region of the first conductivity type, a channel diffusion region of the second conductivity type, and a drain region of the first conductivity type; at least a part of the gate electrode portion is made of a metal layer or a metal compound layer; A semiconductor device, wherein a minimum width of a gate electrode layer region sandwiched between channel diffusion layers is at least 20% narrower than a maximum width of a gate electrode portion formed of a metal or metal compound layer. 3. The semiconductor device according to claim 1, wherein 80% or more of the gate oxide film portion in contact with the channel region is bounded by a polycrystalline silicon layer. Semiconductor device. 4. The semiconductor device according to claim 1, wherein at least a part of said gate electrode portion protrudes above an upper surface of a source region of said semiconductor main surface. 5. The method of claim 1, wherein the source contact portion is silicon-etched deeper than the source diffusion layer to form an ohmic contact between the channel diffusion layer and the source electrode. 5. The semiconductor device according to claim 1, wherein a low resistance channel diffusion layer region having a high concentration is formed. 6. The semiconductor device according to claim 1, wherein the low-resistance channel diffusion layer region is formed deeper than the channel diffusion layer. 7. The semiconductor device according to claim 1, wherein said trench groove is filled with said gate electrode layer. 8. The thickness of the gate oxide film under the trench is 20% of the thickness of the gate oxide film in contact with the channel diffusion layer.
The semiconductor device according to claim 1, wherein the semiconductor device is thicker. 9. A semiconductor chip having a source diffusion layer, a gate electrode, and a channel diffusion layer formed on a first surface, a low resistance drain substrate and a back electrode provided on a second surface opposite to the first surface,
Vertical power MO with drain-source breakdown voltage of 30V or less
A semiconductor device, wherein a thickness of a semiconductor chip having a built-in SFET is 60 μm or less. 10. A semiconductor chip having a source diffusion layer, a gate electrode, and a channel diffusion layer formed on a first surface, a low-resistance drain substrate and a back electrode provided on a second surface opposite to the first surface, In a vertical power MOSFET having a source-to-source withstand voltage of 30 V or less, at least a part of the semiconductor chip of the low-resistance drain substrate is etched from the back surface, and a metal or a metal compound is put in the groove to make the low-resistance drain substrate effective. Target thickness 2
A semiconductor device having a thickness of 0 μm or less. 11. A DC / DC power supply circuit using the semiconductor device according to claim 1. 12. A power MOSFET in which the ratio of the width of the gate electrode layer region sandwiched by the channel diffusion layers to the interval of the trench groove is small, is used as the lower arm element of the power supply circuit, and the ratio of the width of the gate electrode layer region is Power MOS with large
A DC / DC power supply circuit using an FET as an upper arm element of a power supply circuit. 13. A power MOSFET having a small cell pitch.
And a power MOSFET having a large cell pitch as an upper arm element of the power supply circuit. 14. A semiconductor chip having a source diffusion layer, a gate electrode, and a channel diffusion layer formed on a first surface, and a low-resistance drain substrate 1 and a back surface electrode formed on a second surface opposite to the first surface.
A vertical power MOSFET provided with: and n driving the vertical power MOSFET to shut off
Forming a channel MOSFET on the same chip as the vertical power MOSFET; applying a voltage to an external gate terminal formed in the semiconductor chip to turn on the vertical power MOSFET; DC using a semiconductor device that turns on an n-channel MOSFET to turn off the
/ DC power supply circuit. 15. The DC / DC power supply circuit according to claim 14, further comprising a semiconductor chip connected to a polysilicon diode between a gate electrode of said vertical power MOSFET and a drain of said n-channel MOSFET. 16. The semiconductor device according to claim 1, wherein said semiconductor device is used.
The DC / DC power supply circuit according to any one of the above.