JP2636753B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for flattening wiring.

[0002]

2. Description of the Related Art When a wiring is multi-layered, a step becomes large between a portion having a wiring and a portion having no wiring, and it becomes difficult to focus on photolithography. There is a problem that the film thickness is reduced at the step.

Conventionally, as a method of reducing this step, FIG.
There is a first prior art shown in FIG. This is because wirings 02A-
F with a large interval (02C, 02D, 0 in FIG. 5)
2E and 02F), dummy wirings 09A to 09D made of the same material as the wirings 02A to 02F are arranged.
K was filled, and an insulating film 08 was formed thereon. The insulators 07A to K used silica or the like by a coating method. When silica is used, it is necessary to insert the insulating film 11 so that the moisture of the silica does not cause adverse effects such as corrosion on the wirings 02A to F and the dummy wirings 09A to 09D. Further, the dummy wiring 09 was formed simultaneously with the wiring 02 by performing etching using the same photolithography mask as that of the wiring 02.

As another method, there is a second prior art shown in FIG. This is described in Japanese Patent Office Publication No. 276345/1986. The second conventional technique uses dummy insulating films 10A to 10D instead of the dummy wirings 09A to 09D of the first conventional technique. That is, the portions of the insulating film 01 where the wirings 02A to 02F are widely spaced (02C and 02D, 02E and 02 in FIG. 6).
F), dummy insulating films 10A to 10D having substantially the same thickness as the wirings 02A to 02F are formed, and a reflowable insulator 0 such as silica is formed between the wirings 02A to F and the dummy insulating films 10A to 10D.
7A to 7K, and an insulating film 08 was formed thereon. The dummy insulating films 10A to 10D are provided with wirings 02A to 02F.
Before or after the formation of an insulating film, an insulating film is deposited on the entire surface of the wafer, and then patterned using a photolithographic mask different from the wirings 02A to 02F.

[0005]

In the first prior art, the dummy wirings 09A to 09D, which are conductors, are connected to the wiring 02A.
To F, the dummy wirings 09A to 09D serve as electrodes of the inter-wiring parasitic capacitance, increasing the inter-wiring parasitic capacitance and deteriorating the high-speed characteristics.

[0006] The second prior art includes wirings 02A to 02F.
And separate photolithography masks are required for patterning the dummy insulating films 10A to 10D.
Separate steps are required for forming the wirings 02A to 02F and the dummy insulating films 10A to 10D, which has the disadvantage of increasing the amount of work.

Accordingly, the present invention is intended to improve the disadvantages of the above two prior arts and to flatten a multilayer wiring of a semiconductor device having a small parasitic capacitance without increasing the number of photolithography masks.

[0008]

The present invention employs the following means to solve the above-mentioned problems.

(1) A step of forming a first conductive layer on a first insulating film, a step of forming a first film on the first conductive layer, and patterning the first film The process of
Filling the space between the first films with a second film, removing the second film other than the narrow portion of the first film to expose the first conductive layer, Converting the exposed first conductive layer into a second insulating film, etching and removing the second film, and patterning the first conductive layer using the first film as a mask A method for manufacturing a semiconductor device, comprising: a step of removing the first film.

(2) The method of manufacturing a semiconductor device according to (1), further comprising using aluminum for the first conductive layer and converting the first conductive layer into an insulating film by an anodic oxidation method.

(3) The method of manufacturing a semiconductor device according to (1), wherein the step of exposing the first conductive layer leaves the second film on a side wall of the patterned first film.

(4) Between the step of exposing the first conductive layer and the step of converting it to the second insulating film, the exposed first conductive layer is partially etched to reduce the film thickness. The method for manufacturing a semiconductor device according to (1), further comprising a step of thinning the semiconductor device.

[0013]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) and FIGS. 3 (a) and 3 (b)
The cross-sectional view in the order of the manufacturing process is shown.

As shown in FIG. 1, the first semiconductor device of the present invention has wirings 02A to 02F on an insulating film 01 provided on a silicon semiconductor substrate 14, and has wirings 0A to 0F on the insulating film 01.
2A to F with a wide interval (0 in FIG. 1)
Alumina film 06 on 2C and 02D, between 02E and 02F)
A to C. Further, the insulating film 01 and the wirings 02A to
An insulating film 11 such as a silicon nitride film or a silicon oxide film on the F and alumina films 06A to 06C;
1 and wirings 02A-F and alumina film 06A
C have a reflowable insulator 07A-I such as a silica film. Further, an insulating film 08 such as a silicon nitride film or a silicon oxide film is provided thereon.

Next, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 2 (a) and 2 (b) and FIGS.
This will be described with reference to FIG. First, the insulating film 01 is formed on the silicon semiconductor substrate 14. Next, using a photolithography mask for the insulating film 01,
A contact hole 15 is formed. Power is supplied to this contact hole 15 through this portion at the time of anodic oxidation in a later step. Also, this contact hole 15
Is used to connect to elements (not shown) such as transistors, diodes, resistors, and capacitors formed on or on the surface of the silicon semiconductor substrate 14. Next, an aluminum film 16 is deposited by sputtering or chemical vapor deposition (hereinafter referred to as CVD). Next, a silicon nitride film 03 having a thickness of, for example, 0.1 to 0.3 μm is formed by, for example, a plasma CVD method. Next, a silicon oxide film 12 is deposited. It is desirable that the thickness of the silicon oxide film 12 be larger than the minimum distance between the wirings 02A to 02F. Next, a photoresist 04A is formed on a portion where a wiring is to be formed.
To F are formed. The cross section at this time is shown in FIG.
(A).

Next, the silicon oxide film 12 and the silicon nitride film 03 are patterned by anisotropic etching using the photoresists 04A to 04F as masks.
F and 03A-F. Next, the photoresists 04A to 04F are removed. Next, for example, ozone TEOS
Silicon oxide films 05A to 05I having reflow properties are deposited by a CVD method or the like. The thickness of the silicon oxide film 05 is at least の of the minimum distance between the silicon oxide films 12A to 12F, preferably about 0.6 to 1 times. Next, the silicon oxide film 05 is anisotropically etched so that the upper portions of the silicon oxide films 12A to 12F are exposed. At this time, as shown in FIG. 2B, the silicon oxide film 05 remains on the side wall portions of the wide portions (between 12C and 12D and between 12E and 12F) of the silicon oxide films 12A to 12F (FIG. 2B). 05A, D,
E, G, H, I) and the aluminum film 16 is exposed except for the side wall. Further, the narrow portions of the silicon oxide films 12A to 12F are buried with the silicon oxide film 05 (FIG. 2B).
05B, C, F). As the silicon oxide film 05, a silica film formed by a coating method or another CVD film having good coverage may be used.

Next, in the oxalic acid solution, the aluminum film 16 is oxidized from the exposed portion using an anodic oxidation method,
It is converted to alumina films 06A to 06C. At this time, aluminum film 1
6A to 6C need to be electrically connected to the outside through the contact hole 15 and the silicon semiconductor substrate 14 or the like. The cross section at this time is shown in FIG.

Next, the silicon oxide films 05A to I and the silicon oxide films 12A to 12F are removed by etching with a diluted hydrofluoric acid solution or the like, and then anisotropic dry etching is performed using the silicon nitride films 03A to 03F as masks. The aluminum film 16 is patterned to form wirings 02A to 02F. A cross-sectional view at this time is shown in FIG.

Next, after depositing the insulating film 11 on the entire surface, an insulator 07 is formed by a coating method, anisotropic etching is performed, and portions other than the portion between the wiring 02 and the alumina film 06 are removed by etching. When the insulator 07 is silica, the insulating film 11 is formed of a wiring 02 formed by contact with the wirings 02A to 02F.
It has a function of preventing corrosion and the like of AF. At this time, there is no large portion of the space between the wiring 02 and the alumina film 06, and all the spaces are buried by the insulators 07A to 07I. Next, an insulating film 08 is formed on the entire surface to complete the semiconductor device of the first embodiment of the present invention shown in FIG. Note that the insulator 07
Instead of organic coating film such as polyimide, ozone TE
An insulating film with good coverage such as a silicon oxide film formed by an OS method may be used.

As described above, in the semiconductor device according to the first embodiment of the present invention, the wirings 02A to 02F which require fineness are patterned by anisotropic dry etching capable of forming a fine pattern. Alumina films 06A to 06C are formed in portions where wirings 02A to 02F are widely spaced. These wirings 02A to 02F and the alumina film 06A
To C can be formed in a self-aligned manner by using one photolithography mask. Thereby, a fine wiring pattern and flatness can be obtained at the same time. In addition, since the thermal conductivity of the alumina film 06 is 21 W / K · m, which is higher than the 1.4 W / K · m of the silicon oxide film, high discharge performance can be obtained.

Next, a second embodiment of the present invention will be described. In the step of the semiconductor device of the second embodiment, after forming the silicon oxide film 05 in the step of the semiconductor device of the first embodiment (a cross section is shown in FIG. 2B), the aluminum film 16 is formed by anisotropic dry etching. Etching is performed for about 1/4 to 1/3 of the film thickness (FIG.
(Shown in (a)), and then an alumina film 0
6A to 6C (shown in FIG. 4B). Except for this, the process is the same as the process of the first embodiment. Aluminum film 16
Increases in volume when converted to alumina film 06. Therefore, the flatness can be further improved by reducing the thickness of the aluminum film 16 in advance before performing the anodic oxidation.

Further, by forming a through hole on the wiring 02F and connecting with the silicon semiconductor substrate 14, the wiring of the second and subsequent layers can be formed with good flatness as well.

[0023]

As described above, the present invention has an alumina film formed in a self-aligned manner with a wiring pattern in a portion where wiring intervals are wide. The aluminum film is patterned by anisotropic dry etching, and the alumina film is formed by anodic oxidation of the aluminum film. This gives 1
With a single photolithographic mask, a fine pattern and excellent flatness can be obtained without causing an increase in parasitic capacitance and a decrease in heat dissipation.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of one of the manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view of Step 2 of the process for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a first conventional semiconductor device.

FIG. 6 is a cross-sectional view of a second conventional semiconductor device.

[Explanation of symbols]

 01 insulating film 02A-F wiring 03A-F silicon nitride film 04A-F photoresist 05A-I silicon oxide film 06A-C alumina film 07A-I insulator 08 insulating film 09A-D dummy wiring 10A-D dummy insulating film 11 insulating film 12 silicon oxide film 14 silicon semiconductor substrate 15 contact hole 16 aluminum film

Claims (4)

(57) [Claims] A step of forming a first conductive layer on a first insulating film; a step of forming a first film on the first conductive layer; and patterning the first film. A step of filling the space between the first films with a second film, and removing the second film other than a narrow portion of the first film to expose the first conductive layer. Process and the first exposed
Converting the conductive layer into a second insulating film, etching away the second film, patterning the first conductive layer using the first film as a mask, Removing the film of the semiconductor device. 2. The method according to claim 1, further comprising the step of using aluminum for the first conductive layer and converting the first conductive layer to an insulating film by anodization. Method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of exposing the first conductive layer leaves the second film on a side wall of the patterned first film. Method. 4. A step of partially etching the exposed first conductive layer to reduce the thickness between the step of exposing the first conductive layer and the step of converting the first conductive layer into a second insulating film. 2. The method according to claim 1, further comprising the step of: