KR20040031955A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
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- KR20040031955A KR20040031955A KR1020020061250A KR20020061250A KR20040031955A KR 20040031955 A KR20040031955 A KR 20040031955A KR 1020020061250 A KR1020020061250 A KR 1020020061250A KR 20020061250 A KR20020061250 A KR 20020061250A KR 20040031955 A KR20040031955 A KR 20040031955A
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- snc
- insulating film
- spacer
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- hard mask
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 55
- 125000006850 spacer group Chemical group 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000004544 sputter deposition Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 오버행(Over-hang) 프로파일(Profile)이 발생되지 않은 라인 타입(Line type)의 SNC(Storage node contact) 스페이서(Spacer)를 형성하여 소자의 수율 및 신뢰성을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to form a storage node contact (SNC) spacer of a line type in which no over-hang profile is generated, thereby yielding a yield of the device. And a method for manufacturing a semiconductor device for improving reliability.
반도체 소자의 집적화에 따라 비트라인 미스얼라인 마진(Bit line misalign margin) 한계로 홀(Hole) 타입 SNC를 형성할 수 없어 라인 타입 SNC를 형성하는 추세이다.Due to the integration of semiconductor devices, a hole type SNC cannot be formed due to a bit line misalign margin, and thus a line type SNC is being formed.
상기 라인 타입 SNC 형성 공정 시, SNC 패턴을 형성한 후, 비트라인간의 플러그(Plug)를 격리시키기 위해 CMP(Chemical Mechanical Polishing) 공정 또는 에치백(Etch-back) 공정을 진행하여 SNC 스페이서를 형성하기 때문에 상기 비트라인 하드 마스크(Hard mask)의 손실이 발생되는 문제점이 있었다.In the process of forming the line type SNC, after forming the SNC pattern, the SNC spacer is formed by performing a chemical mechanical polishing (CMP) process or an etch-back process to isolate the plug between the bit lines. Therefore, there is a problem in that the loss of the bit line hard mask occurs.
상기 라인 타입 SNC 스페이서의 형성 물질로 스텝 커버리지(Step coverage)가 불량한 PE-Nitride층을 사용하여 상기 비트라인 하드 마스크의 손실을 최소화하고 있었다.The loss of the bit line hard mask was minimized by using a PE-Nitride layer having poor step coverage as a material for forming the line type SNC spacer.
도 1a 내지 도 1e는 종래 반도체 소자의 제조 방법을 도시한 레이아웃도이고, 도 2a 내지 도 2e는 도 1a 내지 도 1e 각각의 Ⅰ-Ⅰ선상의 단면도이다.1A to 1E are layout views illustrating a conventional method for manufacturing a semiconductor device, and FIGS. 2A to 2E are cross-sectional views taken along the line I-I of FIGS. 1A to 1E, respectively.
그리고, 도 3은 도 1c를 나타낸 사진도이고, 도 4는 도 2c를 나타낸 사진도이며, 도 5는 도 2d를 나타낸 사진도이다.3 is a photographic view of FIG. 1C, FIG. 4 is a photographic view of FIG. 2C, and FIG. 5 is a photographic view of FIG. 2D.
도 1a 및 도 2a를 참조하면, 반도체 기판(11) 상에 형성된 제 1 층간절연막(13)과 상기 제 1 층간절연막(13) 상에 형성되며 하드 마스크층(17)이 구비된 비트라인(15)을 포함한 하부 구조물 상에 질화막을 형성하고, 에치백하여 상기 비트라인(15) 측벽에 질화막 스페이서(19)를 형성한다.1A and 2A, a bit line 15 formed on a first interlayer insulating layer 13 and a first interlayer insulating layer 13 formed on a semiconductor substrate 11 and provided with a hard mask layer 17 is provided. The nitride film is formed on the lower structure including the (), and etched back to form the nitride film spacer 19 on the sidewall of the bit line 15.
도 1b 및 도 2b를 참조하면, 상기 질화막 스페이서(19)를 포함한 전면에 제 2 층간절연막(21)을 형성하고, 평탄화 시킨다.1B and 2B, a second interlayer insulating film 21 is formed and planarized on the entire surface including the nitride film spacer 19.
도 1c, 도 2c, 도 3 및 도 4를 참조하면, 라인 타입의 SNC용 마스크(도시하지 않음)를 사용한 사진식각 공정으로 상기 제 1, 제 2 층간절연막(13,21)을 식각하여 SNC(23)를 형성한다.Referring to FIGS. 1C, 2C, 3, and 4, the first and second interlayer insulating layers 13 and 21 may be etched by a photolithography process using a line-type SNC mask (not shown). 23).
도 1d, 도 2d 및 도 5를 참조하면, 상기 제 2 층간절연막(21)을 포함한 전면에 2000 ∼ 3000Å 두께의 PE-Nitride층을 형성한다. 이때, 상기 PE-Nitride층이 스텝 커버리지가 불량하기 때문에 상기 PE-Nitride층의 증착 두께는 상기 비트라인(15) 측벽에는 150 ∼ 250Å(6 ∼ 7의 스텝 커버리지)이고, 상기 SNC(23) 바닥부위에는 200 ∼ 300Å(약 5의 스텝 커버리지)이며, 상기 하드 마스크층(17) 상에는 1000 ∼ 1500Å이다.1D, 2D, and 5, a PE-Nitride layer having a thickness of 2000 to 3000 에 is formed on the entire surface including the second interlayer insulating film 21. At this time, since the PE-Nitride layer has poor step coverage, the deposition thickness of the PE-Nitride layer is 150 to 250 mW (6 to 7 step coverage) on the sidewall of the bit line 15, and the bottom of the SNC 23 is reduced. It is 200-300 Pa (about 5 step coverage) in a site | part, and is 1000-1500 Pa on the said hard mask layer 17.
그리고, 상기 PE-Nitride층을 에치백하여 SNC 스페이서(25)를 형성한다.The PE-Nitride layer is etched back to form an SNC spacer 25.
여기서, 상기 PE-Nitride층이 상기 하드 마스크층(17) 상에 1000 ∼ 1500Å으로 다른 부위보다 두껍게 증착되어, 상기 SNC 스페이서(25) 형성 공정 시 상기 에치백 공정에 사용되는 식각 용액의 투입량이 작아 도 5의 “A”와 같이, 상기 SNC(23) 바닥부위의 CD(Critical Dimension)가 작아진다. 또한 상기 하드마스크층(17) 부위에 오버행 프로파일(B)이 발생된다.Here, the PE-Nitride layer is deposited on the hard mask layer 17 to be thicker than other portions of 1000 to 1500Å, so that the amount of the etching solution used in the etch back process during the SNC spacer 25 formation process is small. As shown by “A” in FIG. 5, the CD (Critical Dimension) at the bottom of the SNC 23 is reduced. In addition, an overhang profile B is generated in the hard mask layer 17.
도 1e 및 도 2e를 참조하면, 상기 SNC 스페이서(25)를 포함한 전면에 다결정 실리콘층을 형성한다. 이때, 상기 다결정 실리콘층의 형성 공정 시, 상기 오버행 프로파일(B)의 발생으로 종횡비가 증가하여 보이드(Void)(27)가 발생된다.1E and 2E, a polycrystalline silicon layer is formed on the entire surface including the SNC spacer 25. At this time, in the process of forming the polycrystalline silicon layer, the aspect ratio increases due to the generation of the overhang profile B, thereby generating voids 27.
그리고, 상기 하드 마스크층(17)을 식각 방지막으로 하는 CMP 방법으로 상기 다결정 실리콘층을 식각하여 플러그(29)를 형성한다.The polycrystalline silicon layer is etched by the CMP method using the hard mask layer 17 as an etch stop layer to form a plug 29.
종래 반도체 소자의 제조 방법은 라인 타입의 SNC 스페이서 형성 물질로 PE-Nitride층을 사용하여 비트라인의 하드 마스크층 손실을 저하시키는 경우, 상기 PE-Nitride층의 스텝커버리지가 불량하기 때문에 상기 SNC 스페이서 형성 공정 시 상기 하드 마스크층 부위에 오버행 프로파일이 발생되고, SNC 바닥부위의 CD가 작아지고, 상기 SNC 스페이서를 형성한 후 후속 공정인 플러그 형성 공정 시 보이드가 발생되는 문제점이 있었다.In the conventional method of manufacturing a semiconductor device, when the hard mask layer loss of the bit line is reduced by using a PE-Nitride layer as a line type SNC spacer forming material, the step coverage of the PE-Nitride layer is poor, thus forming the SNC spacer. During the process, an overhang profile is generated in the hard mask layer, the CD at the bottom of the SNC is reduced, and voids are generated in the plug forming process, which is a subsequent process after forming the SNC spacer.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 PE-Nitride층을 사용한 라인 타입의 SNC 스페이서 형성 공정 시, 비트라인의 하드 마스크층 부위에 형성된 상기 PE-Nitride층을 식각한 후, 상기 SNC 스페이서 형성 공정을 진행함으로써, SNC 바닥부위의 CD가 작아지는 것을 방지하고, 후속 공정인 플러그 형성 공정 시 보이드의 발생을 방지하는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, in the process of forming a line-type SNC spacer using a PE-Nitride layer, after etching the PE-Nitride layer formed on the hard mask layer of the bit line, the SNC spacer It is an object of the present invention to provide a method for manufacturing a semiconductor device which prevents the CD on the bottom of the SNC from becoming smaller and prevents the generation of voids in the subsequent plug formation step.
도 1a 내지 도 1e는 종래 반도체 소자의 제조 방법을 도시한 레이아웃도.1A to 1E are layout views showing a conventional method for manufacturing a semiconductor device.
도 2a 내지 도 2e는 도 1a 내지 도 1e 각각의 Ⅰ-Ⅰ선상의 단면도.2A to 2E are cross-sectional views taken along line II of each of FIGS. 1A to 1E.
도 3은 도 1c를 나타낸 사진도.3 is a photographic view of FIG. 1C.
도 4는 도 2c를 나타낸 사진도.4 is a photographic view of FIG. 2C.
도 5는 도 2d를 나타낸 사진도.5 is a photographic view of FIG. 2D.
도 6a 내지 도 6f는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 도시한 단면도.6A through 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11,31 : 반도체 기판13,33 : 제 1 층간절연막11,31 semiconductor substrate 13,33 first interlayer insulating film
15,35 : 비트라인17,37 : 하드 마스크층15,35 bit line 17,37 hard mask layer
19,39 : 질화막 스페이서21,41 : 제 2 층간절연막19,39: nitride film spacer 21,41: second interlayer insulating film
23,43 : SNC25,47 : SNC 스페이서23,43: SNC25,47: SNC spacer
27 : 보이드29,49 : 플러그27: void 29,49: plug
45 : PE-Nitride층45 PE-Nitride layer
이상의 목적을 달성하기 위한 본 발명은,The present invention for achieving the above object,
하드 마스크층과 절연막 스페이서가 구비된 비트라인과 그 하부에 형성된 제 1 층간 절연막을 포함한 하부 구조물 상에 제 2 층간 절연막을 형성하는 단계와,Forming a second interlayer insulating film on a lower structure including a bit line having a hard mask layer and an insulating film spacer and a first interlayer insulating film formed thereunder;
라인 타입의 SNC용 마스크를 사용한 사진식각 공정으로 상기 제 2 층간 절연막과 제 1 층간 절연막을 식각하여 SNC를 형성하는 단계와,Forming an SNC by etching the second interlayer insulating film and the first interlayer insulating film by a photolithography process using a line type SNC mask;
상기 SNC를 포함한 전면에 스텝 커버리지가 불량한 절연막을 형성하되, 상기 하드 마스크층의 상부 부위에 오버행 프로파일이 발생되는 단계와,Forming an insulating film having poor step coverage on the entire surface including the SNC, wherein an overhang profile is generated in an upper portion of the hard mask layer;
상기 오버행 프로파일을 식각하고, 상기 절연막의 스페이서 형성 공정을 진행하여 상기 SNC 내측에 절연막 스페이서를 형성하는 단계와,Etching the overhang profile and performing a spacer forming process of the insulating film to form an insulating film spacer inside the SNC;
상기 SNC의 매립층인 플러그를 형성하는 단계를 포함하는 반도체 소자의 제조 방법을 제공하는 것과,Providing a method of manufacturing a semiconductor device comprising forming a plug that is a buried layer of the SNC;
상기 절연막을 2000 ∼ 3000Å 두께의 PE-Nitride층으로 형성하는 것을 특징으로 하는 것과,Forming the insulating film with a PE-Nitride layer having a thickness of 2000 to 3000 Å;
상기 오버행 프로파일의 식각 공정은 챔버 바텀 파워가 300 ∼ 600W이고 챔버 압력이 10 ∼ 30mT인 조건하에 아르곤(Ar)을 사용한 스퍼터링 공정으로 실시하는 것을 특징으로 한다.The etching process of the overhang profile is characterized in that the sputtering process using argon (Ar) under a condition that the chamber bottom power is 300 ~ 600W and the chamber pressure is 10 ~ 30mT.
본 발명의 원리는 라인 타입의 SNC 스페이서 형성 공정 시, 아르곤(Ar)을 사용한 스퍼터링(Sputtering) 공정으로 비트라인 하드 마스크층의 상부부위에 형성된 상기 SNC 스페이서 형성 물질인 PE-Nitride층을 식각한 후, 상기 SNC 스페이서 형성 공정을 진행함으로써, 상기 SNC 스페이서 형성 공정 시 SNC 바닥부위의 CD가 작아지는 것을 방지하고, 상기 SNC 스페이서를 형성한 후, 후속 공정인 플러그 형성 공정 시 보이드의 발생을 방지하기 위한 것이다.Principle of the present invention is to etch the PE-Nitride layer, which is the SNC spacer forming material formed on the upper part of the bit line hard mask layer by a sputtering process using argon (Ar) during the line type SNC spacer forming process The process of forming the SNC spacer prevents the CD on the bottom of the SNC from decreasing during the SNC spacer formation process, and prevents the generation of voids during the plug formation process, which is a subsequent process, after forming the SNC spacer. will be.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 6a 내지 도 6f는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 도시한 단면도이다.6A through 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 6a를 참조하면, 반도체 기판(31) 상에 형성된 제 1 층간절연막(33)과 상기 제 1 층간절연막(33) 상에 형성되며 하드 마스크층(37)이 구비된 비트라인(35)을 포함한 하부 구조물 상에 질화막을 형성하고, 에치백하여 상기 비트라인(35) 측벽에 질화막 스페이서(39)를 형성한다.Referring to FIG. 6A, a first interlayer insulating layer 33 formed on a semiconductor substrate 31 and a bit line 35 formed on the first interlayer insulating layer 33 and provided with a hard mask layer 37 are provided. A nitride film is formed on the lower structure and etched back to form a nitride film spacer 39 on the sidewalls of the bit line 35.
도 6b를 참조하면, 상기 질화막 스페이서(39)를 포함한 전면에 제 2 층간절연막(41)을 형성하고, 평탄화 시킨다.Referring to FIG. 6B, a second interlayer insulating film 41 is formed on the entire surface including the nitride film spacer 39 and is planarized.
도 6c를 참조하면, 라인 타입의 SNC용 마스크를 사용한 사진식각 공정으로 상기 제 1, 제 2 층간절연막(33,41)을 식각하여 SNC(43)를 형성한다.Referring to FIG. 6C, the first and second interlayer insulating layers 33 and 41 are etched to form the SNC 43 by a photolithography process using a line type SNC mask.
도 6d를 참조하면, 상기 SNC(43)를 포함한 전면에 2000 ∼ 3000Å 두께의 PE-Nitride층(45)을 형성한다. 이때, 상기 PE-Nitride층(45)이 스텝 커버리지가 불량하기 때문에 상기 PE-Nitride층(45)의 증착 두께는 상기 비트라인(35) 측벽에는 150 ∼ 250Å(6 ∼ 7의 스텝 커버리지)이고, 상기 SNC(43) 바닥부위에는 200 ∼ 300Å(약 5의 스텝 커버리지)이며, 상기 하드 마스크층(37) 상에는 1000 ∼ 1500Å이다.Referring to FIG. 6D, a PE-Nitride layer 45 having a thickness of 2000 to 3000 에 is formed on the entire surface including the SNC 43. At this time, since the PE-Nitride layer 45 has poor step coverage, the deposition thickness of the PE-Nitride layer 45 is 150 to 250 GPa (6 to 7 step coverage) on the sidewall of the bit line 35. The bottom portion of the SNC 43 is 200 to 300 mW (about 5 step coverages), and the hard mask layer 37 is 1000 to 1500 mW.
그리고, 챔버 바텀 파워(Chamber bottom power)가 300 ∼ 600W이고 챔버 압력이 10 ∼ 30mT인 조건하에 Ar을 사용한 스퍼터링 공정을 진행하여, 플라즈마(Plasma)에 의해 형성된 시스(Sheath) 전압의 토폴로지(Topology) 효과에 의해 상기 하드 마스크층(37)의 상부부위에 형성된 PE-Nitride층(45)을 식각한다. 이때, 상기 Ar을 사용한 스퍼터링 공정은 폴리머(Polymer) 발생 및 폴리머 재증착에 의한 공정과 장비 문제를 억제하여 진행한다. 그리고, 상술한 스퍼터링 공정은 RIE(Reactive Ion Etching) 타입(Type)의 장비와 듀얼 파워 소스(Dual power source) 장비까지 플라즈마를 사용한 드라이(D교) 장비에서 진행한다.Then, a sputtering process using Ar is performed under the condition that the chamber bottom power is 300 to 600 W and the chamber pressure is 10 to 30 mT, and the topology of the sheath voltage formed by plasma is shown. By effect, the PE-Nitride layer 45 formed on the upper portion of the hard mask layer 37 is etched. At this time, the sputtering process using Ar proceeds by suppressing the process and equipment problems caused by polymer generation and polymer redeposition. In addition, the above sputtering process is performed in a dry (D bridge) equipment using plasma to the equipment of the RIE (Reactive Ion Etching) type (DIE) type and dual power source (Dual power source) equipment.
도 6e를 참조하면, 상기 PE-Nitride층(45)을 에치백하여 SNC 스페이서(47)를 형성한다.Referring to FIG. 6E, the PE-Nitride layer 45 is etched back to form an SNC spacer 47.
여기서, 상술한 Ar을 사용한 스퍼터링 공정과 스페이서 형성 공정을 조합하여 진행할 수도 있다.Here, the sputtering process using Ar described above and the spacer forming step may be performed in combination.
도 6f를 참조하면, 상기 SNC 스페이서(47)를 포함한 전면에 다결정 실리콘층을 형성한다.Referring to FIG. 6F, a polycrystalline silicon layer is formed on the entire surface including the SNC spacer 47.
그리고, 상기 하드 마스크층(37)을 식각 방지막으로 하는 CMP 방법으로 상기 다결정 실리콘층을 식각하여 플러그(49)를 형성한다.The polycrystalline silicon layer is etched by a CMP method using the hard mask layer 37 as an etch stop layer to form a plug 49.
본 발명의 반도체 소자의 제조 방법은 라인 타입의 SNC 스페이서 형성 공정 시, 비트라인 하드 마스크층의 상부부위에 형성된 상기 SNC 스페이서 형성 물질인 PE-Nitride층을 식각한 후, 상기 SNC 스페이서 형성 공정을 진행함으로써, 상기 SNC 스페이서 형성 공정 시 SNC 바닥부위의 CD가 작아지는 것을 방지하고, 상기SNC 스페이서를 형성한 후, 후속 공정인 플러그 형성 공정 시 보이드의 발생을 방지하여 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, during the process of forming a line type SNC spacer, the PE-Nitride layer, which is the SNC spacer forming material formed on the upper portion of the bit line hard mask layer, is etched and then the SNC spacer forming process is performed. Thus, the CD at the bottom of the SNC spacer is prevented from becoming smaller during the SNC spacer forming process, and after forming the SNC spacer, the voids are prevented during the plug forming process, which is a subsequent process, to improve the yield and reliability of the device. There is.
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| US10748908B2 (en) | 2015-07-01 | 2020-08-18 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor device |
| US11393827B2 (en) | 2015-07-01 | 2022-07-19 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor device |
| US11882691B2 (en) | 2015-07-01 | 2024-01-23 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor device |
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