KR20030059445A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20030059445A
KR20030059445A KR1020010088306A KR20010088306A KR20030059445A KR 20030059445 A KR20030059445 A KR 20030059445A KR 1020010088306 A KR1020010088306 A KR 1020010088306A KR 20010088306 A KR20010088306 A KR 20010088306A KR 20030059445 A KR20030059445 A KR 20030059445A
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KR
South Korea
Prior art keywords
wiring
semiconductor device
manufacturing
contact hole
substrate
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KR1020010088306A
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Korean (ko)
Inventor
윤국한
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주식회사 하이닉스반도체
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Priority to KR1020010088306A priority Critical patent/KR20030059445A/en
Publication of KR20030059445A publication Critical patent/KR20030059445A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of reducing parasitic capacitance between an interconnection and a contact plug. CONSTITUTION: Interconnections(20A) and a hard mask(30) are sequentially stacked on a semiconductor substrate(10). The width of the interconnection(20A) is reduced by under-cutting of the interconnection. An interlayer dielectric(40) is formed to fill the under-cut portion. A contact hole is formed by etching the interlayer dielectric(40) by using SAC(Self Aligned Contact) processing. A contact plug(80) is formed by filling a conductive layer into the contact hole. At this time, the interlayer dielectric(40) remains at both sidewalls of the interconnection.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 배선과 콘택 플러그 사이의 기생 캐패시턴스(parastic capacitance)를 감소시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of reducing parasitic capacitance between a wiring and a contact plug.

반도체 소자의 고집적화에 따른 디자인 룰(design rule)의 감소에 의해 리소그라피(lithography) 장비의 해상도(Resolution) 한계와 오정렬(misalignment) 등의 문제로 인하여 각 층간의 공정 마진을 확보하는 것이 매우 어렵게 되었다. 이에 따라, 콘택형성시 산화막과 질화막 등의 절연막 간의 식각선택비 차이를 이용하는 자기정렬콘택(self-aligned contact; SAC) 공정을 적용하고 있다.Due to the reduction of design rules due to the high integration of semiconductor devices, it is very difficult to secure process margins between layers due to problems such as resolution limitations and misalignment of lithography equipment. Accordingly, a self-aligned contact (SAC) process using a difference in etching selectivity between an oxide film and an insulating film such as a nitride film is applied.

그러나, SAC 공정을 적용하는 경우에는 식각정지층으로서 작용하는 질화막이 7.0 의 높은 절연상수(k) 값을 갖기 때문에, 이미 형성된 배선, 예컨대 워드라인이나 비트라인 같은 배선과, 플러그와 같은 콘택물질 사이의 기생 캐패시턴스가 증가되는 문제가 있었다.However, in the case of applying the SAC process, since the nitride film acting as an etch stop layer has a high dielectric constant (k) of 7.0, the wiring between already formed wires, such as word lines or bit lines, and contact materials such as plugs. There was a problem of increased parasitic capacitance.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 워드라인이나 비트라인 같은 배선과 콘택 플러그 사이의 기생 캐패시턴스를 감소시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing parasitic capacitance between a wiring such as a word line or a bit line and a contact plug.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

10 : 반도체 기판 20, 20A : 배선10: semiconductor substrate 20, 20A: wiring

30 : 하드 마스크 40 : 층간절연막30: hard mask 40: interlayer insulating film

50 : 포토레지스트 패턴 60 : 콘택홀50: photoresist pattern 60: contact hole

70 : 질화막 80 : 콘택 플러그70 nitride film 80 contact plug

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 배선 및 하드 마스크가 적층된 반도체 기판을 준비하는 단계; 배선을 언더컷시켜 배선의 폭을 감소시키는 단계; 언더컷된 배선 사이의 공간이 매립되도록 기판 전면 상에 층간절연막을 형성하는 단계; 층간절연막을 SAC 공정으로 식각하여 하드 마스크 사이의 기판을 노출시키는 콘택홀을 형성하는 단계; 및 콘택홀에 매립되도록 도전막을 증착하고 패터닝하여, 기판과 콘택하는 콘택 플러그를 형성하는 단계를 포함하며, 콘택홀 형성시 콘택홀 측부의 배선 측벽에 층간절연막이 잔류되는 것을 특징으로 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of preparing a semiconductor substrate having a wiring and a hard mask laminated; Reducing the width of the wiring by undercutting the wiring; Forming an interlayer insulating film on the entire surface of the substrate so as to fill the space between the undercut wirings; Etching the interlayer insulating film by a SAC process to form a contact hole exposing the substrate between the hard masks; And depositing and patterning a conductive film so as to be buried in the contact hole, thereby forming a contact plug in contact with the substrate, wherein the interlayer insulating film remains on the wiring sidewall of the contact hole side when forming the contact hole. It can be achieved by the method.

바람직하게, 층간절연막은 갭필 특성이 우수하고 비교적 낮은 절연상수를 갖는 산화막으로서 폴리머 계열의 SOG 산화막으로 형성한다. 또한, 배선의 언더컷은 플라즈마를 이용한 등방성 식각으로 수행하고, 언더컷의 정도는 50 내지 500Å 정도의 범위로 조절한다. 또한, SAC 공정은 고밀도 또는 중밀도 플라즈마 방식으로 O2/N2/CH4, O2/N2, O2/SO2, 및 O2/CO와 같은 산소기재의 조합개스를 이용하여 수행한다.Preferably, the interlayer insulating film is formed of a polymer-based SOG oxide film as an oxide film having excellent gap fill characteristics and having a relatively low insulating constant. In addition, the undercut of the wiring is performed by isotropic etching using plasma, and the degree of the undercut is adjusted in the range of about 50 to 500 kV. In addition, the SAC process is performed using a combination gas of oxygen substrates such as O 2 / N 2 / CH 4, O 2 / N 2, O 2 / SO 2, and O 2 / CO in a high density or medium density plasma method.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(10) 상에 폴리실리콘막, 금속막 또는 금속실리사이드막과 같은 배선용 도전막 및 하드 마스크용 절연막으로서 질화막을 순차적으로 적층하고, 건식식각으로 질화막을 식각하여 하드 마스크(30)를 형성한다. 그 다음, 하드 마스크(30)를 식각 마스크로하여 상기 도전막을 건식식각으로 식각하여 워드라인 또는 비트라인과 같은 배선(20)을 형성한다.Referring to FIG. 1A, a nitride conductive film is sequentially stacked on the semiconductor substrate 10 as a conductive film for wiring, such as a polysilicon film, a metal film, or a metal silicide film, and an insulating film for a hard mask, and the nitride film is etched by dry etching to hard mask. 30 is formed. Next, the conductive layer is etched by dry etching using the hard mask 30 as an etching mask to form a wiring 20 such as a word line or a bit line.

그 후, 배선(20)에 대한 플라즈마를 이용한 등방성 식각조건을 적용하여 하드 마스크(30) 하부의 배선(20)을 언더컷(undercut)시켜, 도 1b에 도시된 바와 같이, 배선(20) 보다 폭이 감소된 배선(20A)을 형성한다. 이때, 언더컷의 정도는 배선의 선폭을 고려하여 50 내지 500Å 정도의 범위로 조절한다. 즉, 언더컷의 조절에 의해 배선(20A)의 폭을 조절할 수 있고, 또한 이후 배선(20A) 측벽에 잔류하는 층간절연막의 양도 조절할 수 있다.Thereafter, an isotropic etching condition using plasma is applied to the wiring 20 to undercut the wiring 20 under the hard mask 30, and as shown in FIG. 1B, the width of the wiring 20 is wider than that of the wiring 20. This reduced wiring 20A is formed. At this time, the degree of undercut is adjusted in the range of about 50 to 500 mV in consideration of the line width of the wiring. That is, the width of the wiring 20A can be adjusted by adjusting the undercut, and the amount of the interlayer insulating film remaining on the side wall of the wiring 20A can be adjusted later.

도 1c를 참조하면, 기판 전면 상에 층간절연막(40)을 형성한다. 바람직하게, 층간절연막(40)은 배선(20A) 사이의 공간을 완전히 매립시킬 수 있도록 갭필(gap-fill) 특성이 우수하면서 비교적 절연상수 값이 낮은 산화막, 더욱 바람직하게는 플로우 특성이 우수한 폴리머 계열의 SOG(Spin On Glass) 산화막으로 형성한다. 예컨대, 이러한 폴리머 계열의 제품으로는 실크(silk), BCB (Benzocyclobutene), 또는 플레어(flare) 등이 있다. 즉, SOG 계열의 산화막은 화학기상증착(Chemical Vapor Deposition; CVD)-산화막에 비해 절연상수값이 낮으므로, 이후 배선(20A)과 콘택 플러그 사이의 기생 캐패시턴스를 감소시키는데 효과적이다. 그 후, 층간절연막(40) 상부에 공지된 포토리소그라피를 이용하여, 배선(20A) 사이에 매립된 층간절연막(40)을 노출시키는 포토레지스트 패턴(50)을 형성한다.Referring to FIG. 1C, an interlayer insulating film 40 is formed on the entire substrate. Preferably, the interlayer insulating film 40 is an oxide film having excellent gap-fill characteristics and a relatively low insulating constant value so as to completely fill a space between the wirings 20A, and more preferably a polymer series having excellent flow characteristics. A spin on glass (SOG) oxide film. For example, such polymer-based products include silk, Benzocyclobutene (BCB), or flare. That is, since the SOG-based oxide film has a lower dielectric constant than the chemical vapor deposition (CVD) -oxide film, it is effective to reduce the parasitic capacitance between the wiring 20A and the contact plug. Thereafter, the photoresist pattern 50 exposing the interlayer insulating film 40 embedded between the wirings 20A is formed by using known photolithography on the interlayer insulating film 40.

도 1d를 참조하면, 포토레지스트 패턴(50)을 식각 마스크로 하여 질화막인 하드 마스크(30)와 산화막인 층간절연막(40)과의 식각 선택비 차이를 이용한 SAC 식각공정을 수행하여, 하드 마스크(30) 사이의 기판(10)을 노출시키는 콘택홀(60)을 형성한다. 여기서, SAC 공정은 O2/N2/CH4, O2/N2, O2/SO2, 및 O2/CO와 같은 산소기재(oxygen-based)의 조합개스를 이용한 고밀도(high density) 또는 중밀도(middle density) 플라즈마 방식으로 수행한다. 이때, 언더컷에 의해 감소된 배선폭에 의해, 도시된 바와 같이, 콘택홀(60) 측부의 배선(20A) 측벽에 층간절연막(40)이 잔류하게 된다. 그 후, 공지된 방법으로 포토레지스트 패턴(50)을 제거한다.Referring to FIG. 1D, using the photoresist pattern 50 as an etching mask, a SAC etching process using an etching selectivity difference between the hard mask 30, which is a nitride film, and the interlayer insulating layer 40, which is an oxide film, is performed. A contact hole 60 exposing the substrate 10 between the 30 is formed. Here, the SAC process is a high density or medium density plasma using an oxygen-based combination gas such as O 2 / N 2 / CH 4, O 2 / N 2, O 2 / SO 2, and O 2 / CO. Do it in a way. At this time, due to the wiring width reduced by the undercut, as shown in the figure, the interlayer insulating film 40 remains on the side wall of the wiring 20A on the side of the contact hole 60. Thereafter, the photoresist pattern 50 is removed by a known method.

도 1e를 참조하면, 후속 세정 공정 등에 의한 산화막 손실을 방지하기 위하여, 필요에 따라 선택적으로 콘택홀(60) 표면 및 층간절연막(40) 상부에 얇은 라이너(liner) 질화막(70)을 형성한 후, 기판(60)이 노출되도록 콘택홀(60) 저부의 질화막(70)을 제거한다.Referring to FIG. 1E, after forming a thin liner nitride layer 70 on the surface of the contact hole 60 and the interlayer insulating layer 40 selectively, as necessary, in order to prevent oxide loss due to a subsequent cleaning process. The nitride layer 70 at the bottom of the contact hole 60 is removed to expose the substrate 60.

도 1f를 참조하면, 콘택홀(60)에 매립되도록 기판 전면 상에 플러그용 도전막을 증착하고, 도전막 및 질화막(70)을 층간절연막(40)이 노출되도록 전면 식각하여, 기판(10)과 콘택하면서 서로 절연된 콘택 플러그(80)를 형성한다.Referring to FIG. 1F, a plug conductive film is deposited on the entire surface of the substrate to be filled in the contact hole 60, and the entire surface is etched so that the interlayer insulating film 40 is exposed to expose the conductive film and the nitride film 70. The contact plugs 80 which are contacted and insulated from each other are formed.

상기 실시예에 의하면, 층간절연막으로서 절연상수가 SOG 계열의 산화막을 적용하고, 디자인룰에 따른 배선의 해당 선폭을 유지하면서 배선의 폭을 언더컷으로 소정 폭만을 감소시켜 SAC 공정 이후에도 층간절연막이 배선의 측벽에 잔류하도록 함으로써, 배선과 콘택 플러그 사이의 기생 캐패시턴스를 감소시킬 수 있다.According to the above embodiment, the insulating constant is applied to the SOG series oxide film as the interlayer insulating film, and the width of the wiring is reduced only by a predetermined width by undercut while maintaining the corresponding line width of the wiring according to the design rule. By remaining on the sidewall, parasitic capacitance between the wiring and the contact plug can be reduced.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

전술한 본 발명은 워드라인이나 비트라인 같은 배선과 콘택 플러그 사이의 기생 캐패시턴스를 감소시킴으로써, 소자의 동작속도를 향상시킬 수 있다.According to the present invention, the parasitic capacitance between the contact line and the wiring such as the word line or the bit line can be reduced, thereby improving the operation speed of the device.

Claims (7)

배선 및 하드 마스크가 적층된 반도체 기판을 준비하는 단계;Preparing a semiconductor substrate on which wiring and hard masks are stacked; 상기 배선을 언더컷시켜 배선의 폭을 감소시키는 단계;Undercutting the wiring to reduce the width of the wiring; 상기 언더컷된 배선 사이의 공간이 매립되도록 상기 기판 전면 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface of the substrate so that the space between the undercut wires is filled; 상기 층간절연막을 SAC 공정으로 식각하여 상기 하드 마스크 사이의 기판을 노출시키는 콘택홀을 형성하는 단계; 및Etching the interlayer dielectric layer by a SAC process to form a contact hole exposing a substrate between the hard masks; And 상기 콘택홀에 매립되도록 도전막을 증착하고 패터닝하여, 상기 기판과 콘택하는 콘택 플러그를 형성하는 단계를 포함하며,Depositing and patterning a conductive film to be filled in the contact hole, thereby forming a contact plug in contact with the substrate, 상기 콘택홀 형성시 상기 콘택홀 측부의 상기 배선 측벽에 상기 층간절연막이 잔류되는 것을 특징으로 반도체 소자의 제조방법.And wherein the interlayer insulating film remains on the wiring sidewall of the contact hole side at the time of forming the contact hole. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은 갭필 특성이 우수하고 비교적 낮은 절연상수를 갖는 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the interlayer insulating film is formed of an oxide film having excellent gap fill characteristics and having a relatively low insulating constant. 제 2 항에 있어서,The method of claim 2, 상기 산화막은 폴리머 계열의 SOG 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The oxide film is a method of manufacturing a semiconductor device, characterized in that formed of a polymer-based SOG oxide film. 제 1 항에 있어서,The method of claim 1, 상기 배선의 언더컷은 플라즈마를 이용한 등방성 식각으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The undercut of the wiring is a method of manufacturing a semiconductor device, characterized in that performed by isotropic etching using plasma. 제 1 항 또는 제 4 항에 있어서,The method according to claim 1 or 4, 상기 언더컷의 정도는 50 내지 500Å 정도의 범위로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.The degree of the undercut is a semiconductor device manufacturing method characterized in that it is adjusted to the range of about 50 ~ 500Å. 제 1 항에 있어서,The method of claim 1, 상기 SAC 공정은 고밀도 또는 중밀도 플라즈마 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The SAC process is a method of manufacturing a semiconductor device, characterized in that performed in a high density or medium density plasma method. 제 6 항에 있어서,The method of claim 6, 상기 SAC 공정은 O2/N2/CH4, O2/N2, O2/SO2, 및 O2/CO와 같은 산소기재의 조합개스를 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The SAC process is a method of manufacturing a semiconductor device, characterized in that performed using a combination gas of oxygen substrates such as O2 / N2 / CH4, O2 / N2, O2 / SO2, and O2 / CO.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026256B2 (en) 2003-07-24 2006-04-11 Hynix Semiconductor Inc. Method for forming flowable dielectric layer in semiconductor device
US7087515B2 (en) 2003-07-24 2006-08-08 Hynix Semiconductor Inc. Method for forming flowable dielectric layer in semiconductor device
US10068799B2 (en) 2016-06-27 2018-09-04 International Business Machines Corporation Self-aligned contact

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026256B2 (en) 2003-07-24 2006-04-11 Hynix Semiconductor Inc. Method for forming flowable dielectric layer in semiconductor device
US7087515B2 (en) 2003-07-24 2006-08-08 Hynix Semiconductor Inc. Method for forming flowable dielectric layer in semiconductor device
US10068799B2 (en) 2016-06-27 2018-09-04 International Business Machines Corporation Self-aligned contact
US10304736B2 (en) 2016-06-27 2019-05-28 International Business Machines Corporation Self-aligned contact

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