KR20040003960A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device is provided to be capable of preventing deformation of a contact hole caused by the difference of doping concentration between stacked interlayer dielectrics. CONSTITUTION: A doped first interlayer dielectric(22) is formed on a semiconductor substrate(20) having an active region(21). The second interlayer dielectric(23) with a relatively low doping concentration compared to the first interlayer dielectric is formed on the resultant structure. A contact hole is formed to expose the active region by two-step etching processes, wherein O2 plasma treatment is used as the second etching in order to improve processing margins. The contact hole is then wet-cleaned.

Description

Method for fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly to a contact plug of a semiconductor device.

As semiconductor devices, especially DRAMs, have become highly integrated, conductive patterns such as word lines, bit lines, and the like are becoming smaller, and contact areas are also decreasing in size. When the contact region had sufficient margin, a contact hole was formed by a general etching process using a photoresist pattern as a mask, and a conductive material was buried in the contact hole and the wiring region to be electrically connected to the lower conductive layer.

However, as devices are becoming more and more integrated, a method of forming contact holes through self-aligned contact processes has been introduced due to a lack of margin of contact regions. In addition, as the size of the contact hole decreases, it is difficult to bury the contact hole with a conductive material satisfactorily, and a contact plug method for filling only the contact hole using a conductive material having excellent embedding characteristics has been widely adopted.

Although contact plugs are formed using doped polysilicon or tungsten (W) for forming contact plugs, tungsten plugs having a relatively lower resistance than doped polysilicon are mainly used.

On the other hand, as the manufacturing technology of semiconductor devices is miniaturized, gap fill capability and planarization technology of interlayer insulating films are increasingly required, and accordingly, doping levels of silicon oxide films used as interlayer insulating films are increasing.

1A to 1B are cross-sectional views illustrating a method of manufacturing a contact plug of a semiconductor device according to the prior art.

As shown in FIG. 1A, first and second interlayer insulating films 12 and 13 are formed on a substrate 10 on which an active region 11 is formed, and then a photoresist pattern 14 for forming a contact hole is formed. do. Here, the first interlayer insulating film 12 is a doped insulating film, and the second interlayer insulating film 13 is an undoped interlayer insulating film.

Subsequently, as illustrated in FIG. 1B, the contact holes 15 are formed by selectively etching the first and second interlayer insulating films 12 and 13 to expose the active region 11 using the photoresist pattern 13. .

Subsequently, as shown in FIG. 1C, the wet cleaning operation is performed after the contact hole is formed.

Next, as shown in FIG. 1D, a barrier metal 15 is formed in the contact hole to protect the substructure in a subsequent process.

At this time, the doped interlayer insulating film 12 and the undoped interlayer insulating film 13 generate a difference in the wet etching rate, which causes a step ('A' in FIG. 1C) during the cleaning operation. This step causes a problem when forming the above-mentioned barrier metal and the like in a subsequent step (Fig. 1D B).

As described above, in the manufacture of a semiconductor device, an interlayer dielectric layer is formed by stacking a doped silicon oxide layer and an undoped silicon oxide layer. Due to the difference in wet etching rate between the interlayer insulating films, a step is generated.

In this case, the step may prevent the film formed in the subsequent process from being formed properly, increase contact resistance, or cause contact fail. In recent years, the higher the integration of semiconductor devices, the higher the doping level of the interlayer insulating film, and thus the larger the step due to this wet cleaning operation.

An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device by preventing the deformation of the contact hole due to the difference in the doping concentration of the interlayer insulating film laminated in the wet cleaning operation.

1A to 1D are cross-sectional views showing a method for manufacturing a contact plug of a semiconductor device according to the prior art;

2A through 2D are cross-sectional views illustrating a method of manufacturing a contact plug in a semiconductor device according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

20: substrate

21: active area

22: first interlayer insulating film

23: second interlayer insulating film

24: photosensitive film pattern

The present invention for achieving the above object comprises the steps of forming a doped first interlayer insulating film on the substrate; Forming a second interlayer dielectric layer having a lower doping concentration than the first interlayer dielectric layer; performing a first etching process of selectively removing the first and second interlayer dielectric layers to form a contact hole; Performing a second etching process of removing a second interlayer dielectric layer in the area around the contact hole with a process margin greater than that of the first etching process; And wet cleaning the contact hole.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A through 2D are cross-sectional views illustrating a method of manufacturing a contact plug in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, first and second interlayer insulating films 22 and 23 are formed on a substrate 20 on which an active region 21 is formed, and then a photoresist pattern 24 for forming a contact hole is formed thereon. ). Here, the first interlayer insulating film 22 is a doped insulating film using a film made of PSG (Phospho-Silicate Glass), BPSG (Boro-Phospho-Silicate Glass), BSG (Boro-Silicate Glass), or SOG (Spin on Glass). The second interlayer insulating film 23 is an undoped interlayer insulating film, and is formed using MTO (Medium Temperature Deposition of Oxide), HTO (High Temperature Oxide), TEOS (Tetraethylorthosilicate), or the like. In this case, the second interlayer insulating film 23 may be used as a nitride film, and a nitride film may be formed on the second interlayer insulating film 23.

Subsequently, as illustrated in FIG. 2B, the first and second interlayer insulating layers 22 and 23 are selectively etched to expose the active regions 21 using the photoresist pattern 13 to form the contact holes 25. . The contact hole 25 may be formed of a hole type, a T type, a bar type, a line type, or the like.

Then as shown in FIG. 2C. After using the O ₂ plasma, the mask CD (critical dimension) is slightly expanded and then etched again. In this case, the first interlayer insulating film 22 is etched so that the etching target is about 80% to 120% of the thickness of the first interlayer insulating film 22.

In addition, in the plasma treatment, argon gas is added for the stability of the plasma, and the process of widening the CD may be performed in-situ or moving the chamber in the same chamber after the first contact hole etching.

Subsequently, as shown in FIG. 2D, the photoresist pattern 13 is removed and a wet cleaning process is performed. In this way, if the contact hole etching process is divided into two and each has a different CD, the vertical step C of the contact hole does not occur even if the wet cleaning process is performed in a subsequent process.

Therefore, since the contact hole does not occur due to the doping concentration of the interlayer insulating film, the resistance of the contact hole may be increased or the contact hole may be prevented, thereby increasing the yield and reliability of manufacturing a semiconductor device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, stable contact holes can be formed, and process reliability of semiconductor devices is expected to be improved.

Claims (5)

Forming a doped first interlayer dielectric film on the substrate; Forming a second interlayer insulating film having a lower doping concentration than the first interlayer insulating film: Performing a first etching process of selectively removing the first and second interlayer dielectric layers to form contact holes; Performing a second etching process of removing a second interlayer dielectric layer in the area around the contact hole with a process margin greater than that of the first etching process; And Wet cleaning the contact hole Method for manufacturing a semiconductor device comprising a. The method of claim 1, And the first interlayer insulating film is one selected from a BPSG film, a BSG film, a PSG film, and an SOG film. The method of claim 1, And the second interlayer dielectric film is one selected from a nitride film, an MTO film, an HTO film, or a TEOS film. The method of claim 1, A method of manufacturing a semiconductor device, characterized by using an O ₂ plasma treatment to have a larger process margin than the first etching process. The method of claim 4, wherein The manufacturing method of the semiconductor device, characterized in that for proceeding the process by adding Ar gas for the stability of the plasma treatment.