KR100329754B1 - A method for fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a process of forming a bit line during a manufacturing process of a semiconductor device. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing residual residue of a bit line conductive material. The present invention does not use a conventional PE-TEOS (plasma enhanced tetraethylotho silicate) film as an interlayer insulating film for the insulation between the landing plug contact and the bit line, and replaces it with a high density plasma oxide (HDP oxide), thereby causing bit line conduction. Prevent residue of material.

Description

A method for fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a bit line forming process of a semiconductor device manufacturing process.

Patterns and pattern gaps are miniaturized with high integration of semiconductor devices, thereby reducing process margins. In particular, the process margin is greatly reduced when forming bit line contacts or charge storage electrode contacts, which is a major factor in yield reduction.

In order to increase the process margin when forming the bit line contact or the charge storage electrode contact, a self-aligned contact (SAC) process is introduced and used. Recently, a landing pad polysilicon, which is a kind of contact pad, is used as a bit line contact and The process margin of the contact process is further increased by simultaneously forming the charge storage electrode contact region.

1A to 1C illustrate a conventional bit line (cell area) forming process using a landing plug polysilicon, which will be described below with reference to the drawing.

In the conventional process, first, as shown in FIG. 1A, the gate oxide film 12, the polysilicon film 13, the tungsten silicide film 14, and the capping insulating film are formed on the silicon substrate 10 on which the field oxide film 11 is formed. 15) forming a word line (gate electrode) composed of sidewall spacer insulating film 16 and a source / drain junction (not shown), and forming a planarized interlayer insulating film 17 over the entire structure, and then forming a landing plug. The interlayer insulating layer 17 of the landing plug forming region is selectively etched by performing a mask process and an etching process for the same. Next, the landing plug polysilicon 18 is formed by depositing a polysilicon film for landing plug contact on the entire structure and performing a chemical and mechanical planarization (CMP) process. At this time, the loss of the interlayer insulating film 17 in the region A in which the landing plug contact is not formed by the CMP process causes a step.

Next, washing is performed using a buffered oxide etchant (BOE) solution as shown in FIG. 1B. At this time, a loss of the interlayer insulating film 17 in the region A in which the landing plug contact is not formed occurs, which causes a larger step (500 to 1000 kV). 2 is a scanning electron microscope (SEM) photograph showing the wafer cross-section after the deposition of the interlayer insulating film, and it can be seen that a step B of about 760 GHz occurs.

Subsequently, as shown in FIG. 1C, a plasma enhanced tetraethylotho silicate (PE-TEOS) film 19 is formed on the entire structure, and a mask process for forming bit lines and selective etching of the PE-TEOS film 19 are performed. After the process, a polysilicon film 20 / tungsten silicide film 21, which is a conductive film for bit lines, is deposited.

Thereafter, the polysilicon layer 20 / tungsten silicide layer 21 is selectively etched to form a bit line. At this time, the polysilicon residue remains due to the step in the region A in which the landing plug contact is not formed. Such residue causes a micro bridge, which reduces the reliability and yield of the semiconductor device. It is becoming. 3 is a planar scanning electron micrograph of a wafer on which a bit line is formed, and shows a state in which a micro bridge C is induced.

In order to reduce the topology of the entire wafer to suppress the occurrence of such polysilicon residues, a method of increasing the thickness of the PE-TEOS film, or increasing the thickness of the PE-TEOS film, and performing etch back after deposition is considered. It is becoming. Increasing the thickness of the PE-TEOS film is concerned with the decrease in productivity due to the increase of the deposition process, particle problems, and the reduction of the process margin due to the increase of the etching depth in the subsequent charge storage electrode contact etching process. In addition, when the etchback is applied to the PE-TEOS film, there is a disadvantage that the process step is increased along with the above-mentioned problems, and thus it is difficult to apply to mass production.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing residual residue of a bit line conductive material due to a step difference caused by oxide loss in a region where a landing plug contact is not formed when the landing plug contact is applied. .

1A to 1C are diagrams illustrating a conventional bit line (cell region) forming process using landing plug polysilicon.

Figure 2 is a scanning electron microscope (SEM) photograph showing the cross-section of the wafer after the deposition of the interlayer dielectric film according to the prior art.

3 is a planar scanning electron micrograph of a wafer on which bit lines are formed.

4A and 4B illustrate a process of forming a bit line (cell area) according to an exemplary embodiment of the present invention.

Figure 5 is a comparison of the profile of the HDP oxide film and the conventional PE-TEOS film.

FIG. 6 is a scanning electron microscope (SEM) photograph showing a cross section of a wafer after deposition of an interlayer dielectric film in accordance with an embodiment of the present invention. FIG.

* Explanation of symbols for the main parts of the drawings

40: silicon substrate 41: field oxide film

42: gate oxide film 43: polysilicon film

44 tungsten silicide film 45 capping insulating film

46 sidewall spacer insulating film 47 interlayer insulating film

48: landing plug polysilicon 49: high density plasma oxide film

In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: a first step of forming a gate electrode having a capping insulating layer and sidewall spacers on a semiconductor substrate; A second step of forming an interlayer insulating film on the entire structure after the first step; Selectively removing the interlayer insulating film in the landing plug contact forming region; A fourth step of forming a conductive film for forming the landing plug contact on the entire structure after the third step; A fifth step of forming the landing plug contact by polishing the conductive film and the interlayer insulating film to the extent that the capping insulating film is exposed through a chemical and mechanical planarization process; A sixth step of forming a high density plasma oxide film on the entire structure of the fifth step; Selectively etching the high density plasma oxide layer to expose the landing plug contacts; And an eighth step of forming a bit line electrically connected to the landing plug contact.

That is, the present invention does not use a conventional PE-TEOS (plasma enhanced tetraethylotho silicate) film as an interlayer insulating film for the insulation between the landing plug contact and the bit line. Prevent residual residue in line conductors.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

4A and 4B illustrate a process of forming a bit line (cell area) according to an embodiment of the present invention, which will be described below with reference to the drawing.

In the process according to the present embodiment, first, as shown in FIG. 4A, a gate oxide film 42, a polysilicon film 43, a tungsten silicide film 44, and a silicon oxide film 40 are formed on the silicon substrate 40 on which the field oxide film 41 is formed. After forming a word line (gate electrode) and a source / drain junction (not shown) composed of the capping insulating film 45 and the sidewall spacer insulating film 46, and forming the planarized interlayer insulating film 47 on the entire structure, The interlayer insulating layer 47 of the landing plug formation region is selectively etched by performing a mask process and an etching process for forming the landing plug. Subsequently, a polysilicon film for landing plug contact is deposited on the entire structure, and a chemical and mechanical planarization (CMP) process is performed to form a landing plug polysilicon 48, followed by cleaning using a buffered oxide etchant (BOE) solution. Conduct. At this time, a loss of the interlayer insulating film 47 in the region D in which the landing plug contact is not formed by the CMP process and the cleaning process causes a step.

Next, as shown in FIG. 4B, a high density plasma oxide film 49 is deposited on the entire structure.

Subsequently, a mask process for forming a bit line contact and a selective etching process of the high density plasma oxide layer 49 are performed. Then, a conductive film for the bit line is deposited and patterned to form a bit line.

5 is a view illustrating a comparison between a profile of an HDP oxide film and a conventional PE-TEOS film. As illustrated in FIG. 5, the HDP oxide film X is different from the conventional PE-TEOS film Y because deposition and etching occur simultaneously. It has excellent gap-filling characteristics and has a characteristic topography in the shape of a mountain in the form opposite to the topology below. This mountain-shaped topology is generated by sputtering, and is formed at an angle of about 45 ° although there is a difference by a deposition recipe.

According to the deposition principle of the HDP oxide film X, it is possible to prevent the residue of the bit line material from occurring in the region D (see FIG. 4A) where the landing plug is not formed during the bit line patterning process.

That is, when the HDP oxide film X is used as an interlayer insulating film, as shown in FIG. 6, the acid-shaped protrusions protrude in the opposite direction to the shape of the valleys generated in the existing oxide film while having almost the same level as in the prior art (see FIG. 2). The topology allows for effective residue removal in the bitline etching process.

In addition, when the HDP oxide film is applied, the gap-filling property is excellent, so that the thickness of the interlayer insulating film can be lowered from 1000 kW or more to 1000 kW or less, thereby ensuring the stability of the subsequent charge storage electrode contact process. have.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

For example, in the above-described embodiment, the case where the polysilicon film is used as the conductive film for the landing plug contact has been described as an example. However, the present invention is almost always used when the conductive film other than the polysilicon film is used as the conductive film for the landing plug contact. Can be applied.

The present invention described above can prevent the micro bridge between the bit lines without increasing the thickness of the interlayer insulating film or the subsequent etch back process by applying the HDP oxide film, it is possible to reduce the manufacturing cost and process steps. In addition, the present invention can take the thickness of the interlayer insulating film to a thickness of 1000Å or less to minimize the generation of particles due to the increase in the thickness of the interlayer insulating film, and for the same reason it is possible to ensure the stability of the subsequent charge storage electrode contact process.

Claims (3)

Forming a gate electrode having a capping insulating film and sidewall spacers on the semiconductor substrate; A second step of forming an interlayer insulating film on the entire structure after the first step; Selectively removing the interlayer insulating film in the landing plug contact forming region; A fourth step of forming a conductive film for forming the landing plug contact on the entire structure after the third step; A fifth step of forming the landing plug contact by polishing the conductive film and the interlayer insulating film to the extent that the capping insulating film is exposed through a chemical and mechanical planarization process; A sixth step of forming a high-density plasma oxide film as an interlayer insulating film on the entire structure after the fifth step; Selectively etching the high density plasma oxide layer to expose the landing plug contacts; And An eighth step of forming a bit line electrically connected to the landing plug contact Semiconductor device manufacturing method comprising a. The method of claim 1, The conductive film for forming the landing plug contact, A semiconductor device manufacturing method, characterized in that the polysilicon film. The method according to claim 1 or 2, The high density plasma oxide film, The semiconductor device manufacturing method characterized by the above-mentioned.