KR100342820B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR100342820B1 KR100342820B1 KR1019990065171A KR19990065171A KR100342820B1 KR 100342820 B1 KR100342820 B1 KR 100342820B1 KR 1019990065171 A KR1019990065171 A KR 1019990065171A KR 19990065171 A KR19990065171 A KR 19990065171A KR 100342820 B1 KR100342820 B1 KR 100342820B1
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- hard mask
- film
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- 239000003990 capacitor Substances 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 38
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000011259 mixed solution Substances 0.000 claims abstract description 18
- 238000001039 wet etching Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 38
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 229910008484 TiSi Inorganic materials 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000243 solution Substances 0.000 abstract description 2
- 239000003989 dielectric material Substances 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000000126 substance Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 제조방법에 관한것으로 고유전체를 이용한 캐패시터 제조공정에서 하드마스크를 이용한 식각공정으로 하부 전극을 형성한후, 하드마스크인 TiN막을 H2SO4/H2O2혼합용액 또는 HN4OH/H2O2/H2O 혼합용액 중 어느 하나의 용액을 이용한 습식식각방법으로 제거하므로 종래 하드마스크를 제거하기 위한 공정에서 원하지 않는 식각이 발생되어 상부 전극 노드의 단선 및 하부 비트라인이 노출되는 등의 문제를 방지할 수 있어, 캐패시터의 전기적 특성 및 소자의 신뢰성을 향상 시킬수 있는 반도체 소자의 캐패시터 제조방법이 제시된다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device. After forming a lower electrode by an etching process using a hard mask in a capacitor manufacturing process using a high dielectric material, a TiN film, which is a hard mask, is mixed with a H 2 SO 4 / H 2 O 2 solution. Alternatively, the wet etching method may be performed by using a wet etching method using any one of HN 4 OH / H 2 O 2 / H 2 O mixed solution. Thus, unwanted etching occurs in a process for removing a hard mask, thereby disconnecting and lowering the upper electrode node. A method of manufacturing a capacitor of a semiconductor device capable of preventing a problem such as exposing a bit line and improving the electrical characteristics of the capacitor and the reliability of the device is provided.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 귀금속을 하부전극으로 이용하는 고유전체 캐패시터에서 하드마스크로 하부전극을 패터닝한 후에 하드마스크 제조공정시 하지층의 식각 손상을 방지하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, after patterning a lower electrode with a hard mask in a high-k dielectric capacitor using a precious metal as a lower electrode, the reliability of the device is prevented by preventing etching of the underlying layer during the hard mask manufacturing process. A method for manufacturing a capacitor of a semiconductor device that can be improved.
종래 반도체 소자의 캐패시터 제조방법을 도 1a 내지 도 1e를 참조하여 설명하면 다음과 같다.A method of manufacturing a capacitor of a conventional semiconductor device will be described with reference to FIGS. 1A to 1E.
도 1a를 참조하면, 기판(10) 상에 비트라인(11) 및 층간절연막(12)을 형성한 후 캐패시터가 형성될 영역의 층간절연막(12)을 일부분을 식각하여 기판(10)이 노출되도록 건식식각방법으로 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상에 도프트 폴리실리콘층을 증착한 후 화학적 기계적연마(CMP)공정이나 에치백(etch back) 공정으로 콘택 홀 내에만 도프트 폴리실리콘층을 남기고, 건식식각이나 습식식각으로 콘택 홀 내의 도프트 폴리실리콘막을 일부 제거하여 리세스(recess)를 갖는 콘택 플러그(13)를 형성한다.Referring to FIG. 1A, after the bit line 11 and the interlayer dielectric layer 12 are formed on the substrate 10, a portion of the interlayer dielectric layer 12 in the region where the capacitor is to be formed is etched to expose the substrate 10. Contact holes are formed by dry etching. After depositing the doped polysilicon layer on the entire structure including the contact hole, the doped polysilicon layer is left only in the contact hole by chemical mechanical polishing (CMP) process or etch back process, and dry etching or wet etching is performed. Thus, a part of the doped polysilicon film in the contact hole is removed to form a contact plug 13 having a recess.
도 1b를 참조하면, 콘택 플러그(13) 상의 리세스 부분에 TiSi2막(14) 및 TiN막(15)이 적층된 확산방지막(16)을 형성한다.Referring to FIG. 1B, a diffusion barrier film 16 including a TiSi 2 film 14 and a TiN film 15 is formed in a recess on the contact plug 13.
도 1c를 참조하면, 전체 상부면에 Pt막(17) 및 하드마스크층(18)을 순차적으로 증착한 후 하부전극용 마스크를 이용한 사진 및 건식각공정으로 패터닝한다.Referring to FIG. 1C, the Pt layer 17 and the hard mask layer 18 are sequentially deposited on the entire upper surface, and then patterned by a photo and dry etching process using a mask for a lower electrode.
도 1d를 참조하면, 캐패시터의 하부전극을 형성하기 위하여 패터닝된 하드 마스크층(18)을 식각 마스크로 이용하여 층간절연막(12)이 노출될때까지 Pt막(17)을 건식 식각하여 하부전극(17a)을 형성한다.Referring to FIG. 1D, by using the patterned hard mask layer 18 as an etching mask to form the lower electrode of the capacitor, the Pt layer 17 is dry-etched until the interlayer insulating layer 12 is exposed, thereby lowering the lower electrode 17a. ).
도 1e는 하드마스크인 TiN막(18)을 제거하기 위한 식각공정을 실시하게 되는 데, 식각공정동안 층간절연막(12) 일부분이 제거된 상태의 단면도로서, 하드마스크 식각공정시 TiN막(18)과 비교하여 층간절연막(12)의 식각선택비가 크므로 원하지 않는 식각이 일어난다.FIG. 1E illustrates an etching process for removing the TiN film 18, which is a hard mask, in which a portion of the interlayer insulating film 12 is removed during the etching process, and the TiN film 18 during the hard mask etching process. Compared with the etching selectivity of the interlayer insulating film 12 is large, so that unwanted etching occurs.
상기한 원하지 않는 층간절연막(12) 식각으로 추후 고유전체막 증착 공정 및 상부 전극 형성공정에서 상부 전극 노드의 단선을 유발하게 되거나 하부 비트라인(11)과 접촉되어 소자의 신뢰성을 저하 시키는 문제가 발생된다.The unwanted interlayer insulating layer 12 is etched to cause disconnection of the upper electrode node or contact with the lower bit line 11 in the high dielectric film deposition process and the upper electrode formation process, thereby lowering the reliability of the device. do.
따라서, 본 발명은 하부전극 형성용 하드마스크 식각공정시 하부 층간절연막이 식각되는 것을 원천적으로 방지하여 상부 전극의 단선을 막고 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a capacitor of a semiconductor device capable of preventing the lower interlayer insulating layer from being etched during the hard mask etching process for forming the lower electrode, thereby preventing disconnection of the upper electrode and improving the electrical characteristics of the device. There is a purpose.
상기한 목적을 달성하기 위한 반도체 소자의 캐패시터 제조방법은 층간절연막에 콘택 홀이 형성된 반도체 기판이 제공되는 단계; 상기 콘택 홀에 콘택 플러그 및 확산방지막을 형성하는 단계; 전체 상부면에 Pt막 및 TiN 하드마스크층을 순차적으로 증착한 후 상기 TiN하드 마스크층을 패터닝하는 단계; 상기 패터닝된 TiN하드마스크층을 식각마스크로 이용한 식각공정으로 상기 Pt막을 식각하여 하부전극을 형성하는 단계; 및 상기 패터닝된 TiN 하드마스크층을 습식 식각방법으로 제거한 후 고유전체막 및 상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A method of manufacturing a capacitor of a semiconductor device for achieving the above object comprises the steps of providing a semiconductor substrate having a contact hole formed in the interlayer insulating film; Forming a contact plug and a diffusion barrier in the contact hole; Sequentially depositing a Pt film and a TiN hard mask layer on the entire upper surface and patterning the TiN hard mask layer; Forming a lower electrode by etching the Pt layer by an etching process using the patterned TiN hard mask layer as an etching mask; And removing the patterned TiN hard mask layer by a wet etching method to form a high dielectric film and an upper electrode.
도 1a 내지 도 1e는 종래 반도체 소자의 캐패시터 제조방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 및 20 : 기판 11 및 21 : 비트라인10 and 20: substrate 11 and 21: bit line
12 및 22 : 층간절연막 13 및 23 : 콘택 플러그12 and 22: interlayer insulating film 13 and 23: contact plug
14 및 24 : TiSi2막 15 및 25 : TiN막14 and 24: TiSi 2 film 15 and 25: TiN film
16 및 26 : 확산방지막 17 및 27 : Pt막16 and 26: diffusion barrier 17 and 27: Pt film
17a 및 27a : 하부전극 29 : 고유전체막17a and 27a: lower electrode 29: high dielectric film
30 : 상부 전극 18 및 28 : 하드마스크층30: upper electrode 18 and 28: hard mask layer
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 소자의 단면도이다.2A to 2E are cross-sectional views of devices for describing a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2a를 참조하면, 기판(20) 상에 비트라인(21) 및 층간절연막(22)을 형성한 후 캐패시터가 형성될 영역의 층간절연막(22)을 일부분을 식각하여 기판(20)이 노출되도록 건식식각방법으로 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상에 도프트 폴리실리콘층을 증착한 후 화학적 기계적연마(CMP)공정이나 에치백(etch back) 공정으로 콘택 홀 내에만 도프트 폴리실리콘층을 남기고, 건식식각이나 습식식각으로 콘택 홀 내의 도프트 폴리실리콘막을 일부 제거하여 리세스(recess)를 갖는 콘택 플러그(23)를 형성한다.Referring to FIG. 2A, after the bit line 21 and the interlayer dielectric layer 22 are formed on the substrate 20, a portion of the interlayer dielectric layer 22 in the region where the capacitor is to be formed is etched to expose the substrate 20. Contact holes are formed by dry etching. After depositing the doped polysilicon layer on the entire structure including the contact hole, the doped polysilicon layer is left only in the contact hole by chemical mechanical polishing (CMP) process or etch back process, and dry etching or wet etching is performed. As a result, a part of the doped polysilicon film in the contact hole is removed to form a contact plug 23 having a recess.
도 2b를 참조하면, 콘택 플러그(23) 상의 리세스 부분에 TiSi2막(24) 및 TiN막(25)이 적층된 확산방지막(26)을 형성한다.Referring to FIG. 2B, a diffusion barrier film 26 including a TiSi 2 film 24 and a TiN film 25 is formed in a recessed portion on the contact plug 23.
상기에서, 확산방지막(26)을 형성하기 전에 도프트 폴리실리콘막(23) 상부면에 형성된 자연산화막을 제거한다. TiSi2막(24)은 100 내지 300Å 두께로 Ti 막을 증착한 후 500 내지 900℃ 온도에서 열공정을 하여 콘택 플러그(23) 상부면에 형성된다. TiSi2막(24) 형성후에 잔존하는 Ti막을 H2SO4/H2O2혼합용액을 이용하여 제거한다. TiN막(25)은 스퍼터링 방법 또는 화학기상증착방법으로 TiN 을 100 내지 500Å 두께로 증착한 후 화학적 기계적 연마공정을 실시하여 TiSi2막(24) 상에 형성된다.In the above, the natural oxide film formed on the upper surface of the doped polysilicon film 23 is removed before the diffusion barrier 26 is formed. The TiSi 2 film 24 is formed on the top surface of the contact plug 23 by a thermal process at a temperature of 500 to 900 ° C. after depositing the Ti film to a thickness of 100 to 300 Å. The Ti film remaining after the TiSi 2 film 24 is formed is removed using a H 2 SO 4 / H 2 O 2 mixed solution. The TiN film 25 is formed on the TiSi 2 film 24 by depositing TiN to a thickness of 100 to 500 kPa by a sputtering method or a chemical vapor deposition method, followed by a chemical mechanical polishing process.
도 2c를 참조하면, 전체 상부면에 Pt막(27) 및 하드마스크층(28)을 순차적으로 증착한 후 하부전극용 마스크를 이용한 사진 및 건식각공정으로 패터닝한다.Referring to FIG. 2C, the Pt layer 27 and the hard mask layer 28 are sequentially deposited on the entire upper surface, and then patterned by photo and dry etching using a mask for a lower electrode.
상기에서, Pt막(27)은 스퍼터링 방법, 화학기상증착방법 및 도금법 중 어느 하나의 방법으로 1000 내지 3000Å 두께로 형성한다. 하드마스크층(28)은 TiN을 스퍼터링방법 또는 화학기상증착방법으로 200 내지 1000Å 두께로 증착하여 형성한다.In the above, the Pt film 27 is formed to have a thickness of 1000 to 3000 kPa by any one of a sputtering method, a chemical vapor deposition method and a plating method. The hard mask layer 28 is formed by depositing TiN to a thickness of 200 to 1000 Å by a sputtering method or a chemical vapor deposition method.
도 2d를 참조하면, 캐패시터의 하부전극을 형성하기 위하여 패터닝된 하드 마스크층(28)을 식각 마스크로 이용하여 층간절연막(22)이 노출될때까지 Pt막(27)을 건식 식각하여 하부전극(27a)을 형성한다.Referring to FIG. 2D, by using the patterned hard mask layer 28 as an etching mask to form the lower electrode of the capacitor, the Pt layer 27 is dry-etched until the interlayer insulating layer 22 is exposed to dry etching the lower electrode 27a. ).
도 2e를 참조하면, 패터닝된 하드마스크층(28)을 습식 식각방법으로 제거한 후 고유전체막(29) 및 상부전극(30)을 형성한다.Referring to FIG. 2E, the patterned hard mask layer 28 is removed by a wet etching method to form a high dielectric film 29 and an upper electrode 30.
상기에서, TiN 하드마스크층(28)을 제거하기 위하여 H2SO4/H2O2혼합용액 또는 HN4OH/H2O2/H2O 혼합용액 중 어느 하나를 이용한다. H2SO4/H2O2혼합용액을 이용한 습식식각방법은 H2SO4: H2O2의 혼합비를 2 : 1 내지 6 : 1 로 하고, 60 내지 140℃ 온도에서 1 내지 120 분간 실시한다. HN4OH/H2O2/H2O 혼합용액을 이용한 습식식각방법은 HN4OH : H2O2:H2O 의 혼합비를 0.1 : 1 : 5 내지 1 : 1 : 5 로 하고, 25 내지 100℃ 온도에서 1 내지 120 분간 실시한다.In the above, in order to remove the TiN hard mask layer 28, any one of a H 2 SO 4 / H 2 O 2 mixed solution or HN 4 OH / H 2 O 2 / H 2 O mixed solution is used. In the wet etching method using the H 2 SO 4 / H 2 O 2 mixed solution, the mixing ratio of H 2 SO 4 : H 2 O 2 is 2: 1 to 6: 1, and is performed at 60 to 140 ° C. for 1 to 120 minutes. do. In the wet etching method using the HN 4 OH / H 2 O 2 / H 2 O mixed solution, the mixing ratio of HN 4 OH: H 2 O 2 : H 2 O is set to 0.1: 1: 5 to 1: 1: 5, 25 It is carried out for 1 to 120 minutes at a temperature of -100 ℃.
고유전체막(29)은 스퍼터링 방법 또는 화학기상증착방법으로 BST를 300 내지 500Å 두께로 증착하고, 상부전극(30)은 Pt 금속을 스퍼터링방법, 화학기상증착방법 및 도금법을 중 어느 하나를 이용하여 증착한다.The high-k dielectric layer 29 is formed by sputtering or chemical vapor deposition by depositing BST to a thickness of 300 to 500 mW. The upper electrode 30 is formed by sputtering, chemical vapor deposition, or plating using Pt metal. Deposit.
아래 표 1은 H2SO4/H2O2혼합용액과 HN4OH/H2O2/H2O 혼합용액의 습식 식각률을 설명하기 위한 표이다.Table 1 below is a table for explaining the wet etching rate of the H 2 SO 4 / H 2 O 2 mixed solution and HN 4 OH / H 2 O 2 / H 2 O mixed solution.
표 1에서와 같이 H2SO4/H2O2혼합용액과 HN4OH/H2O2/H2O 혼합용액은 Pt 및 산화막에 대하여 TiN의 습식 식각 선택비가 우수하다. Pt 및 산화막은 H2SO4/H2O2혼합용액과 HN4OH/H2O2/H2O 혼합용액에서 거의 식각되지 않으나, TiN은 1500Å 정도가 10분 내에 완전히 식각된다. 따라서, 하부 전극 Pt 건식식각 후 하드마스크인 TiN을 제거할 경우 층간절연막의 손상없이 하드마스크인 TiN을 효과적으로 제거할 수 있다.As shown in Table 1, the H 2 SO 4 / H 2 O 2 mixed solution and the HN 4 OH / H 2 O 2 / H 2 O mixed solution have excellent wet etching selectivity of TiN with respect to Pt and the oxide film. Pt and oxide films are hardly etched in the H 2 SO 4 / H 2 O 2 mixed solution and the HN 4 OH / H 2 O 2 / H 2 O mixed solution, but the TiN is completely etched in about 1500 kPa within 10 minutes. Therefore, when removing the hard mask TiN after the dry etching of the lower electrode Pt, the hard mask TiN may be effectively removed without damaging the interlayer insulating layer.
상술한 바와같이, 본 발명에서는 하부전극을 패터닝하기 위한 하드마스크인 TiN막을 H2SO4/H2O2혼합용액 또는 HN4OH/H2O2/H2O 혼합용액 중 어느 하나의 용액을 이용한 습식식각방법으로 제거하므로 종래 하드마스크를 제거하기 위한 공정에서 원하지 않는 식각이 발생하는 것을 방지하여 상부 전극 노드의 단선 및 하부 비트라인이 노출되는 것을 원천적으로 방지하므로 캐패시터의 전기적 특성 및 소자의 신뢰성을 향상 시키는 효과가 있다.As described above, in the present invention, the TiN film, which is a hard mask for patterning the lower electrode, is a solution of any one of H 2 SO 4 / H 2 O 2 mixed solution or HN 4 OH / H 2 O 2 / H 2 O mixed solution. The wet etching method removes unwanted etching in the process of removing the conventional hard mask, thereby preventing the disconnection and the lower bit line of the upper electrode node. It has the effect of improving reliability.
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| KR19980026823A (en) * | 1996-10-11 | 1998-07-15 | 김광호 | Capacitor of Semiconductor Device and Manufacturing Method Thereof |
| KR19980082854A (en) * | 1997-05-09 | 1998-12-05 | 윤종용 | Capacitor Manufacturing Method Using Ferroelectric Film |
| KR19990065766A (en) * | 1998-01-16 | 1999-08-05 | 윤종용 | Platinum Etching Method of Semiconductor Device |
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| KR19980026823A (en) * | 1996-10-11 | 1998-07-15 | 김광호 | Capacitor of Semiconductor Device and Manufacturing Method Thereof |
| KR19980082854A (en) * | 1997-05-09 | 1998-12-05 | 윤종용 | Capacitor Manufacturing Method Using Ferroelectric Film |
| KR19990065766A (en) * | 1998-01-16 | 1999-08-05 | 윤종용 | Platinum Etching Method of Semiconductor Device |
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