KR100355220B1 - Method for contacting polycide with polycide - Google Patents
Method for contacting polycide with polycide Download PDFInfo
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- KR100355220B1 KR100355220B1 KR1019950002138A KR19950002138A KR100355220B1 KR 100355220 B1 KR100355220 B1 KR 100355220B1 KR 1019950002138 A KR1019950002138 A KR 1019950002138A KR 19950002138 A KR19950002138 A KR 19950002138A KR 100355220 B1 KR100355220 B1 KR 100355220B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 배선형성방법에 관한 것으로, 특히 폴리사이드와 폴리사이드간의 배선을 접촉시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring of a semiconductor device, and more particularly, to a method of bringing a wiring between a polyside and a polyside into contact.
반도체메모리의 디램(DRAM:Dynamic Random Acccess Memory)의 집적도가 향상됨에 따라 RC지연시간을 줄이기 위해 전극 및 배선물질로 저접촉저항을 갖는 재료들을 사용하고 있다. 저접촉저항을 갖는 물질중에서 고융점의 금속층을 폴리실리콘층 상에 형성하는 폴리사이드가 널리 이용되고 있다. 특히 최근에는 WSix 폴리실리콘으로 이루어진 텅스텐폴리사이드가 사용되고 있는데, 이를 게이트전극과 비트라인 배선재료로 동시에 사용하여 접촉을 형성할때에는 접촉저항이 증가되는 등의 문제점이 발생한다. 이러한 문제점의 원인은 첫째 WSix표면에 폴리실리콘을 증착하는조건이 500℃이상의 고온이므로 WSix산화가 생기고, 둘째, 폴리실리콘이 인으로 도핑되어 있고 WSix에서의 인의 확산속도가 빠르므로, 비트라인을 형성하는 폴리실리콘의 인이 게이트전극의 텡스텐실리사이드로 확산되어 비트라인의 폴리실리콘의 도핑농도가 저하때문이다.As the integration of dynamic random access memory (DRAM) in semiconductor memory is improved, materials having low contact resistance are used as electrodes and wiring materials to reduce RC delay time. Among the materials having low contact resistance, polysides for forming a high melting point metal layer on a polysilicon layer are widely used. In particular, recently, tungsten polysides made of WSix polysilicon have been used, which causes problems such as an increase in contact resistance when forming a contact using the gate electrode and the bit line wiring material simultaneously. The reason for this problem is that first, polysilicon deposition on WSix surface is higher than 500 ℃, and WSix oxidation occurs. Second, polysilicon is doped with phosphorus and the diffusion rate of phosphorus in WSix is high, thus forming bit lines Phosphorus of polysilicon is diffused into the tungsten silicide of the gate electrode, and the doping concentration of the polysilicon of the bit line is lowered.
따라서 본 발명의 목적은 텅스텐폴리사이드와 텅스텐폴리사이드간의 접촉저항을 낮추는 방법을 제공하고자 한다.Accordingly, an object of the present invention is to provide a method for lowering the contact resistance between tungsten polyside and tungsten polyside.
본 발명의 목적을 달성하기 위해, 반도체 기판에 형성된 소오스/드레인을 가지는 반도체 장치의 폴리사이드간의 접촉방법은, 상기 소오스와 드레인 사이에 해당하는 상기 반도체 기판 상에 제 1폴리실리콘층과 제 1금속실리사이드층을 형성하여 제 1폴리사이드를 형성하는 단계, 결과물 전면에 층간절연막을 도포하고 패턴화하여 상기 제 1폴리사이드의 소정부분이 노출되게 하는 접촉구를 형성하는 단계, 상기 층간절연막의 상면, 상기 접촉구의 내측벽 및 상기 제 1폴리사이드의 상면에 금속층을 형성하는 단계, 상기 금속층을 금속순간어닐링하여 상기 접촉구의 상면에 형성된 금속층을 금속실리사이드층으로 변환시키는 단계, 및 상기 금속층과 금속실리사이드층 위에 제 2폴리실리콘층과 제 2실리사이드층을 순차적으로 형성하고 패턴화하여 제 2폴리사이드를 형성하는 단계를 구비한다. 여기서, 상기 제 1 및 제 2폴리사이드가 WSix/폴리실리콘층 TiSix/폴리실리콘층, TaSix/폴리실리콘층 중의 어느 하나일 수 있다. 특히 금속층이 TiN층일때는 800℃에서 10-30초간 질소가스 분위기에서 열처리하여 금속실리사이드층이 TiSix 층을 얻을 수 있다.In order to achieve the object of the present invention, a method of contact between polysides of a semiconductor device having a source / drain formed on a semiconductor substrate, the first polysilicon layer and a first metal on the semiconductor substrate corresponding to the source and drain Forming a silicide layer to form a first polyside, applying and patterning an interlayer insulating film over the entire surface of the resultant to form a contact hole for exposing a predetermined portion of the first polyside, an upper surface of the interlayer insulating film, Forming a metal layer on an inner sidewall of the contact hole and an upper surface of the first polyside, converting the metal layer formed on the upper surface of the contact hole into a metal silicide layer by instantaneously annealing the metal layer, and the metal layer and the metal silicide layer The second polysilicon layer and the second silicide layer are sequentially formed thereon and patterned to form a second pole Forming a reside. Here, the first and second polysides may be any one of a WSix / polysilicon layer TiSix / polysilicon layer and a TaSix / polysilicon layer. Particularly, when the metal layer is a TiN layer, the metal silicide layer may obtain a TiSix layer by heat treatment at 800 ° C. for 10-30 seconds in a nitrogen gas atmosphere.
따라서 제 1폴리사이드와 제 2폴리사이드 간에 금속실리사이드층을 형성하여폴리사이드의 폴리실리콘의 인의 원하지 않는 확산을 방지할 수 있고 폴리사이드와 폴리사이드 간의 접촉저항을 줄일 수 있다.Thus, a metal silicide layer may be formed between the first polyside and the second polyside to prevent unwanted diffusion of phosphorus of the polysilicon of the polyside and to reduce the contact resistance between the polyside and the polyside.
이하 본 발명을 제 2A도 내지 제 2C도를 참조로 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2C.
제 2A도는 금속층을 형성하는 단계를 나타낸다.2A illustrates the step of forming the metal layer.
필드분리산화막(3)에 의해 정의되는 반도체기판(1)의 활성영역에 소오스/드레인(5)이 형성된다 소오스/드레인 사이에 해당하는 반도체기판의 상면에 게이트전극을 형성한다. 게이트전극은 제 1폴리실리콘층(7)과 제 1텅스텐실리사이드층(9)으로 구성되며 이는 제 1텅스텐폴리사이드가 된다. 결과물 전면에 층간절연막(10)을 도포하고 패턴화하여 제 1텅스텐실리사이드층(9)의 소정부분을 노출시키는 접촉구(12)를 형성한다. 또한 인접하는 타 소오스 또는 드레인 영역을 노출시키는 접촉구도 형성된다. 접촉구는 통상의 포토리토그래피방법으로 형성한다. 다음 층간절연막(10)의 상면, 상기 접촉구(12)의 내측벽, 상기 제 1텅스텐실리사이드층(9)의 상면 및 인접하는 소오스(드레인)의 상면에 금속층을 형성한다. 여기서의 금속층은 TiN층이다. TiN층(15)은 아르곤의 가스분위기, 바람직하게는 질소농도가 10-20%인 분위기에서 스퍼터링하여 Ti와 N의 비율이 1.0이상이 되게 한다.The source / drain 5 is formed in the active region of the semiconductor substrate 1 defined by the field separation oxide film 3. A gate electrode is formed on the upper surface of the semiconductor substrate corresponding to the source / drain. The gate electrode is composed of a first polysilicon layer 7 and a first tungsten silicide layer 9, which becomes a first tungsten polyside. The interlayer insulating film 10 is coated on the entire surface of the resultant and patterned to form a contact hole 12 exposing a predetermined portion of the first tungsten silicide layer 9. Contact holes are also formed that expose adjacent other sources or drain regions. The contact hole is formed by a conventional photolithography method. A metal layer is formed on an upper surface of the next interlayer insulating film 10, an inner wall of the contact hole 12, an upper surface of the first tungsten silicide layer 9, and an upper surface of an adjacent source (drain). The metal layer here is a TiN layer. The TiN layer 15 is sputtered in an argon gas atmosphere, preferably in an atmosphere having a nitrogen concentration of 10-20%, so that the ratio of Ti and N is 1.0 or more.
제 2B도는 금속실리사이드층(17)을 형성하는 단계를 나타낸다. TiN층을 800℃에서 10-30초간 질소가스분위기에서 급속순간어닐링하여 TiN층과 소오스/드레인의 실리콘층 또는 게이트전극의 제 1실리사이드층과의 접촉면 및 TiN층과 인접하는 소오스와의 접촉면에 TiSix의 금속실리사이드층(17)을 형성한다. 금속층을 텅스텐(W)나 탄탈륨(Ta)을 사용하면 금속실리사이드층은 WSix 또는 TaSix이 된다.2B shows the step of forming the metal silicide layer 17. The TiN layer was rapidly annealed in a nitrogen gas atmosphere at 800 ° C. for 10-30 seconds to form a TiSix on the contact surface between the TiN layer and the silicon layer of the source / drain or the first silicide layer of the gate electrode and the contact surface between the TiN layer and the source. The metal silicide layer 17 is formed. When tungsten (W) or tantalum (Ta) is used for the metal layer, the metal silicide layer becomes WSix or TaSix.
제 2C도는 제 2폴리사이드를 형성하는 단계를 나타낸다.2C shows the step of forming the second polyside.
TiN층(15)과 TiSix층(17) 전면에 제 2폴리실리층(11)과 제 2텅스텐실리사이드층(13)을 순차적으로 도포한다. 다음 TiN층과 상기 제 2폴리실리층(11)과 제 2텅스텐실리사이드층(13)을 패턴화하여 제 2텅스텐폴리사이드를 형성한다.The second polysilicon layer 11 and the second tungsten silicide layer 13 are sequentially applied to the TiN layer 15 and the TiSix layer 17 over the entire surface. Next, the TiN layer, the second polysilicon layer 11, and the second tungsten silicide layer 13 are patterned to form a second tungsten polyside.
이상에서 종래의 제 1 및 제 2텅스텐폴리사이드 사이에 금속실리사이드층(17)을 형성하여 하기의 효과를 얻을 수 있다. 첫재 TiN층(15)을 게이트전극과 비트라인 사이에 위치하므로 비트라인을 형성하는 폴리실리콘층의 인의 원하지 않는 확산을 방지 할 수 있다.In the above, the metal silicide layer 17 is formed between the conventional first and second tungsten polysides to obtain the following effects. Since the first TiN layer 15 is positioned between the gate electrode and the bit line, unwanted diffusion of phosphorus in the polysilicon layer forming the bit line can be prevented.
둘째, 200℃ 하에서 TiN층을 게이트전극을 구성하는 제 1텅스텐실리사이드층(9) 위에 형성하고 고온의 제2폴리실리콘층(1)을 형성하기 때문에 제 1텅스텐실리사이드층(9)와 소오스(드레인) 표면에 산화막이 형성을 방지한다. 셋째, 비트라인과 인접하는 소오스(드레인)간에도 접촉저항을 낮출 수 있다. 넷째, TiSix층이 접촉구내에서 형성되므로 후속 열처리 공정에서 Ti의 확산으로 인한 누설전류 증가를 막을 수 있다.Second, since the TiN layer is formed on the first tungsten silicide layer 9 constituting the gate electrode at 200 ° C. and the high temperature second polysilicon layer 1 is formed, the first tungsten silicide layer 9 and the source (drain) are formed. The oxide film is prevented from forming on the surface. Third, the contact resistance can be lowered even between the bit line and the adjacent source (drain). Fourth, since the TiSix layer is formed in the contact hole, it is possible to prevent the leakage current increase due to the diffusion of Ti in the subsequent heat treatment process.
이상에서 본 발명을 실시예를 들어 설명하였으나 본 발명은 이에 한정되지 않고 당해 기술분야의 통상의 지식을 가진 자에게 본원 발명의 사상의 범위 내의 각종 변형이 가능함이 자명하다.The present invention has been described above by way of examples, but the present invention is not limited thereto, and various modifications within the scope of the spirit of the present invention are obvious to those skilled in the art.
제1도는 종래의 방법에 따른 폴리사이드와 폴리사이드간의 접촉상태를 나타내는 단면도이다.1 is a cross-sectional view showing a contact state between a polyside and a polyside according to a conventional method.
제2A도 내지 제2C도는 본 발명에 따른 폴리사이드와 폴리사이드간의 접촉방법을 나타내는 단면도이다.2A to 2C are cross-sectional views showing a contact method between a polyside and a polyside according to the present invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950002138A KR100355220B1 (en) | 1995-02-07 | 1995-02-07 | Method for contacting polycide with polycide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950002138A KR100355220B1 (en) | 1995-02-07 | 1995-02-07 | Method for contacting polycide with polycide |
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| Publication Number | Publication Date |
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| KR960032601A KR960032601A (en) | 1996-09-17 |
| KR100355220B1 true KR100355220B1 (en) | 2002-12-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950002138A KR100355220B1 (en) | 1995-02-07 | 1995-02-07 | Method for contacting polycide with polycide |
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| KR100430687B1 (en) * | 1996-12-31 | 2004-08-02 | 주식회사 하이닉스반도체 | Method of forming metal line of semiconductor device for improving anti-diffusion performance and electrical properties |
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1995
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