KR100237016B1 - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor device Download PDFInfo
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- KR100237016B1 KR100237016B1 KR1019930021066A KR930021066A KR100237016B1 KR 100237016 B1 KR100237016 B1 KR 100237016B1 KR 1019930021066 A KR1019930021066 A KR 1019930021066A KR 930021066 A KR930021066 A KR 930021066A KR 100237016 B1 KR100237016 B1 KR 100237016B1
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- metal wiring
- semiconductor device
- tin
- diffuse reflection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로, 반도체 소자의 제조공정 중 DLM(Double Layer Metalization) 공정에서 하부층 금속배선에 발생되는 보이드(Viod)를 방지하기 위하여, Al 합금층과 난반사막인 TiN 막 사이에 얇은 티타늄(Ti)을 증착하는 방법으로 하부층 금속배선을 제조하므로써, 효과적으로 보이드 발생을 억제하여 고신뢰성을 갖는 반도체 소자를 제조할 수 있도록 한 반도체 소자의 금속배선을 제조하는 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal wiring of a semiconductor device. In order to prevent voids generated in the lower layer metal wiring in a double layer metallization (DLM) process, an Al alloy layer and a diffuse reflection film are used. A method of manufacturing a metal wiring of a semiconductor device in which a lower layer metal wiring is manufactured by depositing thin titanium (Ti) between TiN films, thereby effectively suppressing the generation of voids and manufacturing a semiconductor device having high reliability. Are described.
Description
제1도는 종래기술에 의해 하부층 금속배선이 형성된 반도체 소자의 DLM 구조를 도시한 단면도.1 is a cross-sectional view showing a DLM structure of a semiconductor device in which a lower layer metal wiring is formed according to the prior art.
제2도는 본 발명에 의해 하부층 금속배선이 형성된 반도체 소자의 DLM 구조를 도시한 단면도.2 is a cross-sectional view showing a DLM structure of a semiconductor device in which a lower layer metal wiring is formed according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 층간 절연막 2 : 제1중간 절연막1: interlayer insulating film 2: first intermediate insulating film
3 : SOG막 4 : 제2중간 절연막3: SOG film 4: Second intermediate insulating film
5 : 상부층 금속막 10 : 하부층 금속배선5: upper layer metal film 10: lower layer metal wiring
11 : Ti 막 12 : TiN 막11: Ti film 12: TiN film
13 : Al 합금층 14 : TiN 막(난반사막)13 Al alloy layer 14 TiN film (reflective film)
15 : Ti 막(확산 방지층)15 Ti film (diffusion prevention layer)
본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로, 특히 반도체 소자의 제조공정 중 DLM(Double Layer Metalization) 공정에서 하부층 금속배선에 발생되는 보이드(Viod)를 방지하기 위하여, Al 합금층과 난반사막인 TiN 막 사이에 얇은 티타늄(Ti)을 증착하는 방법으로 하부층 금속 배선을 제조하므로써, 효과적으로 보이드 발생을 억제하여 고신뢰성을 갖는 반도체 소자를 제조할 수 있도록 한 반도체 소자의 금속배선을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing metal wiring of a semiconductor device. In particular, an Al alloy layer and a diffuse reflection film in order to prevent voids generated in a lower layer metal wiring in a double layer metallization (DLM) process during a manufacturing process of a semiconductor device. In the method of manufacturing the metal wiring of the semiconductor device to manufacture a semiconductor device having a high reliability by effectively suppressing the generation of voids by manufacturing the lower layer metal wiring by depositing thin titanium (Ti) between the TiN film. It is about.
일반적으로 DLM 공정은 반도체 소자의 제조공정 중 DRAM 소자의 기초가 되는 트랜지스터와 캐패시터가 형성된 이후의 공정으로 정보전달의 원활화와 소자크기의 감소를 위해 하부층 및 상부층 금속배선을 설정하는 공정이다. 상기 하부층 금속배선은 Ti/TiN/Al 합금/TiN 막으로 형성되고, 상기 상부층 금속배선과의 사이에는 SOG막등의 절연막이 형성된다. 하부층 금속배선상에 도포되는 SOG막은 경화공정을 실시하게 되는데, 이때 SOG 자체에 내포되어 있는 탄소 및 수분성분이 하부층으로 확산되어 하부층 금속배선에 보이드의 발생을 유발시키는 문제점이 있다.In general, the DLM process is a process after the transistors and capacitors, which are the basis of DRAM devices, are formed in the semiconductor device manufacturing process to set up the lower and upper metal wirings to facilitate information transfer and reduce the device size. The lower layer metal wiring is formed of a Ti / TiN / Al alloy / TiN film, and an insulating film such as an SOG film is formed between the upper layer metal wiring and the upper layer metal wiring. The SOG film applied on the lower layer metal wiring is subjected to a curing process. At this time, the carbon and moisture components contained in the SOG itself are diffused into the lower layer to cause the generation of voids in the lower metal wiring.
따라서, 본 발명은 SOG 경화공정시 하부층 금속배선으로 침투되는 탄소 및 수분성분을 차단하여 보이드 없는 금속배선을 제조하는 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a void-free metal wiring by blocking carbon and moisture components penetrating into the lower metal wiring during the SOG curing process.
이러한 목적을 달성하기 위한 본 발명은 하부층 금속배선상에 조밀한 결정구조를 갖는 Ti 막을 얇게 형성하는 것을 특징으로 한다.The present invention for achieving the above object is characterized by forming a thin Ti film having a dense crystal structure on the lower layer metal wiring.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 종래 기술에 의해 하부층 금속배선이 형성된 반도체 소자의 DLM 구조를 도시한 단면도로서, 실리콘 기판상에 소정의 트랜지스터 및 캐패시터(도시않음)를 형성한 후 층간 절연막(BPSG)(1)을 형성한 상태에서, 하부층 금속배선(10)을 형성하고, 그 상부에 제1중간 절연막(2)을 증착한 후, 평탄화를 위해 SOG막(Spin on Glass)(3)을 도포 및 경화한 다음, 제2중간 절연막(4)을 증착하고, 그 상부에 상부층 금속막(5)을 증착한 상태를 도시한 것이다.FIG. 1 is a cross-sectional view showing a DLM structure of a semiconductor device in which a lower layer metal wiring is formed according to the prior art, and after forming a predetermined transistor and a capacitor (not shown) on a silicon substrate, an interlayer insulating film (BPSG) 1 is formed. In one state, a lower layer metal wiring 10 is formed, a first intermediate insulating film 2 is deposited thereon, and an SOG film (Spin on Glass) 3 is applied and cured for planarization. The state where the intermediate | middle insulating film 4 was deposited and the upper layer metal film 5 was deposited on it is shown.
상기 하부층 금속배선(10)은 상기 층간 절연막(1) 상부에 Ti 막(11), TiN 막(12), Al 합금층(13) 및 난반사막으로 TiN 막(14)을 순차적으로 적층한 후, 마스크 공정 및 식각공정으로 소정부분을 식각하여 형성한다.The lower layer metal wiring 10 is a Ti film 11, TiN film 12, Al alloy layer 13 and a diffuse reflection film sequentially stacked TiN film 14 on the interlayer insulating film 1, A predetermined portion is etched and formed by a mask process and an etching process.
그러나, 상기 하부층 금속배선(10) 형성 후 SOG막(3) 경화공정시 SOG 자체에 내포되어 있는 탄소 및 수분성분이 제1중간 절연막(3)과 난반사막인 TiN 막(4)을 통과하여 하부층 금속배선(10)에 보이드 발생을 유발시키므로 인해 반도체 소자의 신뢰성 저하의 요인으로 작용된다.However, after the formation of the lower layer metal wiring 10, the carbon and moisture components contained in the SOG itself pass through the first intermediate insulating film 3 and the TiN film 4, which is a diffuse reflection film, during the curing process of the SOG film 3. Since it causes the generation of voids in the metal wiring 10, it acts as a factor of lowering the reliability of the semiconductor device.
금속배선의 보이드를 억제하기 위한 방법으로 난반사막인 TiN 막(4)을 두껍게 증착하여 후속공정의 SOG막 경화공정시 탄소 및 수분성분의 확산을 방지하는 방법이 있으나, 이러한 방법은 반사도의 저하로 금속배선형성을 위한 포토레지스트 공정시 문제점이 발생되며, 다른 방법으로서 금속배선의 두께를 두껍게 형성하여 후속공정의 SOG막 경화공정으로 인한 보이드 발생에도 불구하고 금속배선의 특성을 유지하는 방법이 있으나, 이 또한 단차가 열악하여 후속공정진행시 문제점이 발생된다.As a method for suppressing voids in the metal wiring, a TiN film 4, which is a diffuse reflection film, is deposited thickly to prevent diffusion of carbon and moisture components in the SOG film curing process in a subsequent process. There is a problem in the photoresist process for forming the metal wiring, and another method is to form a thick metal wiring to maintain the characteristics of the metal wiring despite the generation of voids due to the SOG film curing process in the subsequent process, In addition, the step is poor, the problem occurs during the subsequent process.
따라서, 금속배선의 두께를 원하는 두께로 유지시키되 반사도를 변화시키지 않으면서 SOG에 의한 보이드 발생을 억제하기 위하여, 첨부된 제2도를 참조하여 설명하기로 한다.Therefore, in order to maintain the thickness of the metal wiring at a desired thickness but to suppress the generation of voids by SOG without changing the reflectivity, a description will be given with reference to FIG. 2.
제2도는 본 발명에 의해 하부층 금속배선이 형성된 반도체 소자의 DLM 구조를 도시한 단면도로서, DLM 형성을 위한 기본적인 공정단계는 전술한 제1도와 동일하므로 상세한 설명은 생략하기로 한다.FIG. 2 is a cross-sectional view illustrating a DLM structure of a semiconductor device in which a lower layer metal wiring is formed by the present invention. Since the basic process steps for forming the DLM are the same as those of FIG. 1, the detailed description thereof will be omitted.
본 발명에 의한 하부층 금속배선(10)의 구성은 제1도에서 설명한 종래기술에 의한 하부층 금속배선(10)과 달리 Al 합금층(13)을 형성한 후, Ti 막(15)을 얇게 증착한 다음, 그 상부에 난반사막인 TiN 막(14)을 증착하여 하부층 금속배선을 제조한다.In the structure of the lower layer metal wiring 10 according to the present invention, unlike the lower layer metal wiring 10 according to the related art described in FIG. 1, after forming the Al alloy layer 13, the Ti film 15 is thinly deposited. Next, a TiN film 14, which is a diffuse reflection film, is deposited on the upper portion, thereby manufacturing a lower layer metal wiring.
상기 Al 합금층(13)상에 증착되는 Ti 막(15)은 결정구조가 매우 조밀하여 후공정의 SOG막(3) 경화공정시 SOG 자체에 내포되어 있는 탄소 및 수분성분이 Al 합금층(13)으로 확산되는 것을 방지하는 확산 방지층 역할을 하여 보이드 발생이 없는 특성이 우수한 금속배선이 되게한다.The Ti film 15 deposited on the Al alloy layer 13 has a very dense crystal structure, so that the carbon and water components contained in the SOG itself during the curing process of the SOG film 3 in the later process are Al alloy layer 13. It acts as a diffusion barrier layer that prevents diffusion into), resulting in excellent metal wiring without voids.
또한, 확산방지층 역할을 하는 Ti 막(15)은 그 두께가 얇기 때문에 전체적인 토폴러지(Topology)에 영향을 주지않는다.In addition, since the thickness of the Ti film 15 serving as the diffusion barrier layer is thin, it does not affect the overall topology.
한편, Al 합금층(13), 확산 방지층인 Ti 막(15) 및 난반사막인 TiN 막(14)의 증착은 종래와 같이 전체막 증착동안 대기 노출없이 연속적으로 진행된다.On the other hand, deposition of the Al alloy layer 13, the Ti film 15 as the diffusion barrier layer and the TiN film 14 as the diffuse reflection film proceeds continuously without atmospheric exposure during the entire film deposition as in the prior art.
상술한 바와같이 본 발명은 SOG막의 경화공정시 확산되는 탄소 및 수분성분의 확산을 Ti 막으로 방지하여 금속배선에 보이드 발생을 억제하므로 반도체 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention can prevent the diffusion of carbon and moisture components during the curing process of the SOG film with the Ti film to suppress the generation of voids in the metal wiring, thereby improving the reliability of the semiconductor device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930021066A KR100237016B1 (en) | 1993-10-12 | 1993-10-12 | Manufacture of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930021066A KR100237016B1 (en) | 1993-10-12 | 1993-10-12 | Manufacture of semiconductor device |
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| KR950012690A KR950012690A (en) | 1995-05-16 |
| KR100237016B1 true KR100237016B1 (en) | 2000-01-15 |
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| KR1019930021066A KR100237016B1 (en) | 1993-10-12 | 1993-10-12 | Manufacture of semiconductor device |
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| KR100312376B1 (en) * | 1995-07-11 | 2003-08-06 | 주식회사 하이닉스반도체 | Method for forming intermetal dielectric of semiconductor device |
| KR20010094667A (en) * | 2000-03-31 | 2001-11-01 | 박태호 | Fatliquoring agent with esterification and oxidation reaction of fatty acid and monomer |
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