KR970013023A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

Info

Publication number
KR970013023A
KR970013023A KR1019950023876A KR19950023876A KR970013023A KR 970013023 A KR970013023 A KR 970013023A KR 1019950023876 A KR1019950023876 A KR 1019950023876A KR 19950023876 A KR19950023876 A KR 19950023876A KR 970013023 A KR970013023 A KR 970013023A
Authority
KR
South Korea
Prior art keywords
insulating film
contact hole
semiconductor device
forming
rtp
Prior art date
Application number
KR1019950023876A
Other languages
Korean (ko)
Other versions
KR0175414B1 (en
Inventor
이태종
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950023876A priority Critical patent/KR0175414B1/en
Publication of KR970013023A publication Critical patent/KR970013023A/en
Application granted granted Critical
Publication of KR0175414B1 publication Critical patent/KR0175414B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment

Abstract

본 발명은 반도체 방법에 관한 것으로서, 반도체 기판에 다층의 절연막을 형성하고, 제1, 제2 사진식각의 공정을 통하여 콘택 홀을 형성하고, 금속을 증착하기 이전에 RTP를 이용한 리플로우를 시킴으로써 완만한 경사면의 콘택홀 프로파일을 형성함으로써 향상된 스텝 커버리지를 획득하게되어 금속배선의 신뢰성을 향상시키고, 각 콘택 홀의 스텝 커버리지 산포가 감소하는 효과를 가지는 반도체 장치의 콘택 홀 형성 방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor method, comprising forming a multilayer insulating film on a semiconductor substrate, forming contact holes through first and second photolithography, and reflowing using RTP prior to depositing a metal. By forming a contact hole profile of one inclined surface, improved step coverage is obtained, thereby improving the reliability of metal wiring and reducing the step coverage distribution of each contact hole.

Description

반도체 장치의 콘택 홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가) 내지 (다)는 본 발명에 의한 반도체 장치의 콘택 홀 형성 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2C are cross-sectional views showing a method for forming a contact hole in a semiconductor device according to the present invention in accordance with the process procedure.

Claims (6)

반도체 기판에 다층의 절연막을 형성하는 제1 공정, 상기 다층의 절연막을 사진식각하여 콘택 홀을 형성하는 제2공정, 상기 콘택 홀이 형성되어 있는 상기 반도체 기판을 RTP를 이용하여 리플로우하는 제3공정을 포함하는 반도체 장치의 제조 방법.A first step of forming a multilayer insulating film on a semiconductor substrate, a second step of forming a contact hole by photo etching the multilayer insulating film, and a third step of reflowing the semiconductor substrate on which the contact hole is formed using RTP The manufacturing method of the semiconductor device containing the process. 제1항에서, 상기 다층의 절연막은 도핑되지 않은 절연막과 도핑된 절연막을 포함하는 반도체 장치의 제조 방법.The method of claim 1, wherein the multilayer insulating film comprises an undoped insulating film and a doped insulating film. 제2항에서, 상기 다층의 절연막에 상기 도핑된 절연막 위해 식각 속도가 빠른 제1 절연막과 식각 속도가 상기 도핑된 절연막과 같은 제2 절연막의 이중층으로 더 포함하여 형성하는 반도체 장치의 제조 방법.The method of claim 2, wherein the multilayer insulating film further comprises a double layer of a first insulating film having a high etch rate and a second insulating layer having an etch rate of the doped insulating film. 제1항에서, 상기 다층의 절연막의 사진식각하는 공정은 상기 절연막의 일부를 등방성 습식 식각하고 나머지의 절연막을 이방성 건식 식각으로 하는 반도체 장치의 제조 방법.2. The method of claim 1, wherein the photolithography of the multilayer insulating film comprises anisotropic wet etching a portion of the insulating film and anisotropic dry etching the remaining insulating film. 제1항에서, 상기 RTP의 온도를 850 ~ 1000℃으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of said RTP is 850-1000 degreeC. 제1항에 또는 제5항에서, 상기 RTP를 10초 ~ 1분 동안 진행하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1 or 5, wherein the RTP is performed for 10 seconds to 1 minute.
KR1019950023876A 1995-08-02 1995-08-02 Method for forming contact hole in semiconductor device KR0175414B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950023876A KR0175414B1 (en) 1995-08-02 1995-08-02 Method for forming contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023876A KR0175414B1 (en) 1995-08-02 1995-08-02 Method for forming contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR970013023A true KR970013023A (en) 1997-03-29
KR0175414B1 KR0175414B1 (en) 1999-04-01

Family

ID=19422695

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950023876A KR0175414B1 (en) 1995-08-02 1995-08-02 Method for forming contact hole in semiconductor device

Country Status (1)

Country Link
KR (1) KR0175414B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100671607B1 (en) * 2002-07-09 2007-01-18 주식회사 하이닉스반도체 Method for manufacturing flash memory

Also Published As

Publication number Publication date
KR0175414B1 (en) 1999-04-01

Similar Documents

Publication Publication Date Title
KR950034678A (en) A method for forming a conductive connection in an integrated circuit and a conductive member in the circuit
KR940022801A (en) Contact formation method of semiconductor device
KR970013023A (en) Contact hole formation method of semiconductor device
JPS57145340A (en) Manufacture of semiconductor device
KR980005592A (en) Self-aligned contact hole forming method
KR0172261B1 (en) Method of forming contact hole of semiconductor device
KR970052303A (en) Metal wiring formation method of semiconductor device
KR100219509B1 (en) Method for forming metal layer in semiconductor device
KR930011116A (en) Manufacturing Method of Semiconductor Device
KR970013032A (en) Contact Forming Method for Highly Integrated Semiconductor Devices
KR100236060B1 (en) Method of fabricating semiconductor device
KR970000220B1 (en) Method for producing dram cell capacitor
KR19990055175A (en) Metal wiring formation method of semiconductor device
KR970008347A (en) Metal layer formation method of semiconductor device
KR960026239A (en) Contact hole formation method of semiconductor device
KR940008014A (en) Method of forming interlayer insulating film in semiconductor device
KR950007066A (en) Metal wiring formation method of semiconductor device
KR950021102A (en) Metal wiring formation method of semiconductor device
KR960019535A (en) Semiconductor device manufacturing method
KR910003761A (en) Multi-layer metallization process method of semiconductor device
KR970018115A (en) Metal wiring formation method of semiconductor device
KR960015796A (en) Metal wiring layer formation method of a semiconductor device
KR970053557A (en) Manufacturing method of semiconductor device
KR940027100A (en) Method for forming multilayer wiring of semiconductor device
KR970013029A (en) Contact hole formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061030

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee