JP2559829B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

The present invention relates to a wiring forming method for a semiconductor device.

[Prior Art] In a silicon semiconductor integrated circuit, aluminum is mainly used as a wiring material. However, with the miniaturization of the integrated circuit, disconnection of wiring due to migration of aluminum atoms due to current and stress is a big problem. Is becoming.

In addition, tungsten and molybdenum, which have strong resistance to migration, have a large electric resistance, which causes a problem of voltage drop and delay in wiring due to miniaturization.

Therefore, it is considered to use copper for the wiring as a material having a high migration resistance and a low resistance. As a method of burying copper in a fine contact hole, a selective growth method of a copper thin film (Japanese Patent Application No. 63-124006) utilizing the difference in catalytic activity on metal and metal silicide has already been proposed.

[Problems to be Solved by the Invention] In this method, it has been proposed to sandwich the upper and lower sides of a copper wiring with various metals in order to improve the adhesion to the underlayer and the insulating film for selective growth. However, when the sandwiched metal is pure copper, the resistance to stress and electromigration is not sufficient.

The present invention has been made in view of the above points, and particularly in a multilayer wiring of a semiconductor device, it is possible to satisfactorily fill fine inter-layer contact holes with copper and to form a copper alloy having strong migration resistance as a wiring material. It is an object of the present invention to provide a manufacturing method that satisfies both requirements, and to provide a semiconductor device having a wiring in which fine contact holes are satisfactorily filled with copper and which has strong migration resistance.

[Means for Solving the Problems] At least one surface of the semiconductor device of the present invention is covered with at least one metal selected from zirconium, chromium, cadmium and silver, and at least one of the metals containing copper as a main component is contained therein. It is characterized by comprising a wiring structure having a metal containing a seed.

According to the method of the present invention, in the step of forming a multilayer wiring of a semiconductor device, after forming a first film made of one kind of zirconium, chromium, cadmium and silver on an insulating film, copper is deposited on the film and Zirconium, chromium,
A step of depositing a third film made of one of cadmium and silver to form a multi-layer film, and processing the multi-layer film to form wiring, and then forming an insulating film thereon, and forming a hole A step of selectively forming copper only in the opened region by a chemical vapor deposition method, and then forming an upper copper wiring, and a part of the metal of the first and third films by a heat treatment. Alternatively, the method is characterized by having a step of alloying by diffusing all in copper.

[Operation] In the present invention, zirconium, which has good adhesion to an insulator and copper, has a large electric conductivity of an alloy with copper, has migration resistance, and is a base for good selective growth of copper, Since chromium, cadmium or silver is formed on the upper and lower sides of the copper wiring and these metals are used as the base for the selective growth of copper and alloyed by heat treatment, higher performance wiring is possible as compared with the conventional method.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows an example of a semiconductor device manufacturing process according to the present invention. After forming the metal silicide barrier 3 in the diffusion layer 2 of the single crystal silicon 1, copper 4 is selected by a method utilizing the difference in catalytic activity disclosed in Japanese Patent Application No. 63-124006, for example.
CVD is performed and the silicon oxide 5 is taken out from the hole. Further, zirconium, chromium, cadmium, or silver 6 is deposited as a base material for the wiring of the first layer, then copper 7 is deposited, and zirconium, chromium, cadmium, or silver 8 is further deposited thereon (see FIG. )). Zirconium, chromium, cadmium or silver as the base of the copper wiring enhances the adhesion to the base insulating material and improves the reliability of the semiconductor device.

The above metal deposited on the copper wiring can form a contact wiring of a good and good copper film as a base of copper selectively grown in the contact hole.

After processing this multilayer film by ion milling or reactive ion etching of a gas containing chlorine to form wiring,
An insulating film such as silicon oxide 9 is deposited and a hole is formed (FIG. 1 (B)).

Copper 10 is selectively deposited in the openings by chemical vapor deposition utilizing the difference in catalytic activity (FIG. 1 (C)).

The conditions for chemical vapor deposition are, for example, using a low pressure CVD apparatus,
Hexafluoroacetylacetonato copper heated to 0 ℃ was transported into the reaction chamber at 100cc / min hydrogen gas, and the total gas pressure was 1000P.
a, Sample temperature can be deposited at 350 ℃.

Further, as the second layer wiring, a multilayer film composed of the film 11 made of zirconium, chromium, silver or cadmium, the copper 12, the film 13 made of zirconium, chromium, silver or cadmium is formed again and processed (see FIG. )).

Furthermore, by heating this in an inert gas atmosphere at 400 ° C. or higher, a part of the metal of the films 11 and 13 is diffused in the silver 12 to form an alloy 14 (FIG. 1 (E)).

FIG. 2 is an example of a semiconductor having a multilayer wiring formed in this way. In the figure, 15 is metal silicide, 16 is polycrystalline silicon, 17 is a gate oxide film, 18 is an isolation oxide film, and 19 is silicon oxide.

The copper alloy 14 is alloyed by diffusing zirconium, chromium, silver or cadmium in copper, but its alloy composition is 95 at% or more, more preferably 99 at% or more so as not to significantly reduce the conductivity. To be included. The alloy composition can be controlled by adjusting the heat treatment temperature and time. Since the surface of copper is covered with zirconium, chromium, silver or cadmium, it has excellent migration resistance.

FIG. 3 shows an example in which the metals of the films 11 and 13 are completely diffused into copper to form a copper alloy 14.

Also in this case, the alloy composition should contain 95 at% or more, more preferably 99 at% or more of copper. By controlling the thickness of the metal layers 11 and 13 and the copper layer 12, the composition of the alloy layer formed by diffusion can be controlled.
By alloying, the migration resistance can be improved without significantly reducing the conductivity of the wiring layer.

[Effects of the Invention] As described above, the present invention has the following effects.

Zirconium, chromium, silver, and cadmium as the base of the copper wiring enhance the adhesion with the base insulating material and improve the reliability of the semiconductor device.

The above metal deposited on the copper wiring can form a contact wiring of a good and good copper film as a base of copper selectively grown in the contact hole.

When the metal diffuses into copper, migration resistance can be improved without significantly reducing the conductivity of copper.

As described above, a fine wiring structure having migration resistance can be realized.

[Brief description of drawings]

FIG. 1 is a process drawing of an embodiment of the manufacturing method of the present invention, and FIGS. 2 and 3 are sectional views of the embodiment of the present invention. 1 …… single crystal silicon, 2 …… diffusion layer, 3,15 …… metal silicide, 4,7,10,12 …… copper, 5 …… silicon oxide, 6,8,11,13 …… metal (zirconium , Chrome, silver or cadmium), 9 ... Silicon oxide, 14 ... Copper alloy, 16 ... Polycrystalline silicon, 17 ... Gate oxide film, 18 ... Isolation oxide film.

Claims (2)

(57) [Claims] 1. A wiring having at least one surface thereof covered with at least one metal selected from zirconium, chromium, cadmium and silver, and having a metal containing copper as a main component and at least one metal selected from the above metals. A semiconductor device having a structure. 2. In a process of forming a multi-layer wiring of a semiconductor device,
After forming a first film made of one kind of zirconium, chromium, cadmium and silver on the insulating film, copper is deposited on the film, and further on the film, zirconium, chromium, cadmium and silver A step of depositing a third film of one kind to form a multi-layer film; a step of processing the multi-layer film to form wiring, then forming an insulating film thereon and forming a hole; A step of selectively forming copper only in the opened region by a phase growth method and then forming an upper copper wiring; and a part or all of the metal of the first and third films by heat treatment. A method of manufacturing a semiconductor device, comprising a step of diffusing in copper to form an alloy.