KR20010063028A - Method for forming copper interconnects - Google Patents
Method for forming copper interconnects Download PDFInfo
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- KR20010063028A KR20010063028A KR1019990059862A KR19990059862A KR20010063028A KR 20010063028 A KR20010063028 A KR 20010063028A KR 1019990059862 A KR1019990059862 A KR 1019990059862A KR 19990059862 A KR19990059862 A KR 19990059862A KR 20010063028 A KR20010063028 A KR 20010063028A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
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- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
Abstract
Description
본 발명은 구리배선 형성방법에 관한 것으로서, 특히 다마신 또는 이중 다마신 공정에 의한 구리배선 형성방법에 관한 것이다.The present invention relates to a method for forming copper wiring, and more particularly, to a method for forming copper wiring by a damascene or double damascene process.
반도체 소자의 고집적화에 따라 금속배선의 최소 선폭은 계속적으로 축소되고 있으며, 이에 따라, RC 지연에 따른 동작속도의 저하가 문제점으로 대두되고 있다. 따라서, 최근에는 반도체 소자의 고속동작에 대한 요구를 만족시키기 위해 도전율이 높은 구리가 종래의 알루미늄을 대체할 재료로서 많이 연구되고 있다.Due to the high integration of semiconductor devices, the minimum line width of metal wiring is continuously reduced, and as a result, a decrease in operating speed due to RC delay has become a problem. Therefore, in recent years, in order to satisfy the demand for high speed operation of semiconductor devices, copper having high conductivity has been studied as a material to replace conventional aluminum.
구리는 도전율이 높기 때문에 반도체 소자의 고속화로 인해 도선에 흐르는 전자량이 증대하더라도 이에 따른 내성을 유지할 수 있다는 이점을 가진다. 그러나, 구리는 알루미늄에 비해 식각하기가 어렵고, 또한 고온에서 증착이 이루어지기 때문에 PR 마스크(photoresist mask)를 이용한 선택적 증착이 어려운 난점이 있다. 따라서, 구리배선을 형성시키는 방법으로, 구리배선의 하부에 위치할 절연막에 미리 회로 도선부에 대응하는 도랑(trench)을 형성하고 그곳에 구리를 채워넣는 다마신(damascene) 공정이 적용되고 있다. 또한, 아래층 도선부와의 연결에 필요한 비아홀을 도랑과 함께 형성하고 비아홀과 도랑을 한꺼번에 채우는 이중 다마신 공정(dual damascene)도 적용되고 있다.Since copper has high conductivity, it has the advantage that the resistance can be maintained even if the amount of electrons flowing through the conductive wire increases due to the high speed of the semiconductor device. However, since copper is more difficult to etch than aluminum and is deposited at a high temperature, selective deposition using a PR mask (photoresist mask) is difficult. Therefore, as a method of forming copper wiring, a damascene process is formed in which trenches corresponding to circuit lead portions are formed in advance in an insulating film to be positioned below the copper wiring and filled with copper therein. In addition, a dual damascene process has been applied, in which via holes necessary for connection with the lower conductive parts are formed together with the trenches, and the via holes and the trenches are simultaneously filled.
다마신 또는 이중 다마신 공정의 간단한 일 예를 살펴보면 다음과 같다. 먼저, 절연막에 구멍이나 도랑을 형성한 다음에, 구리와 절연막과의 상호반응을 방지하기 위하여 질화탄탈륨(TaN)으로 이루어진 확산방지막을 형성한다. 이어서, 확산방지막이 형성된 결과물상에 구리 씨앗층을 스퍼터링법으로 형성한 후에, 구리 씨앗층을 전극으로 사용하여 전기도금법으로 기판 전면을 구리막으로 덮는다.A simple example of a damascene or dual damascene process is as follows. First, holes or trenches are formed in the insulating film, and then a diffusion barrier film made of tantalum nitride (TaN) is formed to prevent mutual reaction between copper and the insulating film. Subsequently, after forming a copper seed layer by the sputtering method on the resultant on which the diffusion barrier film was formed, the whole surface of a board | substrate is covered with a copper film by the electroplating method using a copper seed layer as an electrode.
이와 같은 방법으로 현재 250nm 및 180nm 폭을 가지는 구리배선을 효과적으로 형성하고는 있지만, 앞으로 배선폭이 더욱 작아지면 전기도금의 전극으로 사용하기 위한 구리 씨앗층을 스퍼터링법으로 형성하는 것은 바람직하지 않게 된다. 왜냐하면, 스퍼터링법은 직시형(line of sight) 증착특성을 가져서 단차피복성(step coverage)이 나쁘기 때문이다. 즉, 스퍼터링법에 의할 경우에는 큰 종횡비(aspect ratio)를 가지는 구멍이나 도랑의 내부에 구리 씨앗층이 제대로 형성되지 않기 때문이다. 따라서, 구리 씨앗층을 형성함에 있어서는 단차도포성이 좋은 화학증착법을 이용하는 것이 바람직하다.In this way, copper wires having 250 nm and 180 nm widths are effectively formed. However, when the wire width becomes smaller, it is not preferable to form a copper seed layer for use as an electrode for electroplating by sputtering. This is because the sputtering method has a line of sight deposition characteristic and thus poor step coverage. That is, in the case of the sputtering method, the copper seed layer is not properly formed inside the hole or the trench having the large aspect ratio. Therefore, in forming the copper seed layer, it is preferable to use a chemical vapor deposition method having good step coating properties.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 다마신 또는 이중 다마신 공정을 이용하여 구리배선을 형성함에 있어서, 화학증착법으로 구리 씨앗층을 형성한 후에, 전기도금법으로 두터운 구리막을 형성하는 구리배선 형성방법을 제공하는 데 있다.Therefore, the technical problem to be achieved by the present invention, in forming a copper wiring by using a damascene or double damascene process, after forming a copper seed layer by a chemical vapor deposition method, forming a copper wiring to form a thick copper film by the electroplating method To provide a way.
도 1a 내지 1e는 본 발명의 일 예에 따른 구리배선 형성방법을 설명하기 위한 공정 단면도들;1A to 1E are cross-sectional views illustrating a method of forming a copper wiring according to an embodiment of the present invention;
도 2a 및 2c는 본 발명의 다른 예에 따른 구리배선 형성방법을 설명하기 위한 공정 단면도들이다.2A and 2C are cross-sectional views illustrating a method of forming a copper wiring according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
100 … 기판 110 … 절연막100... Substrate 110. Insulating film
120 … 구멍 또는 도랑 130 … 질화탄탈륨 확산방지막120... Hole or groove 130... Tantalum nitride diffusion barrier
140 … 구리막 150 … 표면촉매140. Copper film 150. Surface catalyst
144, 160 … 구리 씨앗층 170 … 매립용 구리144, 160... Copper seed layer 170... Landfill copper
상기 기술적 과제를 달성하기 위한 본 발명의 구리배선 형성방법은, 후속 공정으로서 다마신 또는 이중 다마신 공정을 진행하기 전에, 구멍이나 도랑이 형성된 절연막 상에 표면촉매를 이용한 화학증착법으로 구리 씨앗층을 형성한 다음, 상기 구리 씨앗층을 전극으로 사용하는 전기도금법으로 상기 구멍이나 도랑에 구리를 채워넣는 것을 특징으로 한다.In order to achieve the above technical problem, the method for forming a copper wiring according to the present invention may include forming a copper seed layer by chemical vapor deposition using a surface catalyst on an insulating film having holes or grooves before proceeding with a damascene or double damascene process. Next, the copper is filled in the hole or the trench by an electroplating method using the copper seed layer as an electrode.
여기서, 사용되는 표면촉매는 대한민국 특허출원 제98-53575호에 개시된 바와 같이 증착되는 막에 매몰되지 아니하고 그 막의 표면으로 이동하여 화학증착반응을 촉진하는 역할을 한다. 본 발명에서는 상기 표면촉매가 아이오딘 또는 브롬을 함유하는 것이 바람직하다.Here, the surface catalyst used is not buried in the deposited film as disclosed in Korean Patent Application No. 98-53575 and serves to promote the chemical deposition reaction by moving to the surface of the film. In the present invention, it is preferable that the surface catalyst contains iodine or bromine.
한편, 상기 구리와 절연막과의 상호반응을 방지하기 위하여, 상기 구리 씨앗층을 형성하기 전에 상기 절연막상에 질화티타늄(TiN), 질화탄탈륨(TaN), 탄탈륨-규소-질소(Ta-Si-N), 또는 티타늄-규소-질소(Ti-Si-N) 등으로 이루어진 확산방지막을 더 형성하는 것이 바람직하다.Meanwhile, in order to prevent interaction between the copper and the insulating film, before the copper seed layer is formed, titanium (TiN), tantalum nitride (TaN), and tantalum-silicon-nitrogen (Ta-Si-N) are formed on the insulating film. ) Or a diffusion barrier film made of titanium-silicon-nitrogen (Ti-Si-N) or the like.
이 때, 상기 구리와 확산방지막 사이의 접착성이 약해서 후속되는 화학기계적 연마공정에서 문제가 생길 수 있다면 이를 피하기 위해, 상기 구리 씨앗층을 형성하기 전에 상기 확산방지막이 형성된 결과물상에 스퍼터링법으로 구리층을 더 형성할 수도 있다.At this time, in order to avoid problems in the subsequent chemical mechanical polishing process due to weak adhesion between the copper and the diffusion barrier film, copper is formed by sputtering on the resultant on which the diffusion barrier film is formed before the copper seed layer is formed. Further layers may be formed.
상기한 본 발명의 개념은, 구멍과 도랑이 연통하여 형성된 절연막 상에서 이루어지는 이중 다마신공정에도 적용될 수 있다. 즉, 구멍과 도랑이 연통하여 형성된 절연막 위에 표면촉매를 이용한 화학증착법으로 구리 씨앗층을 형성함과 동시에 구멍을 채우는 단계를 먼저 진행하고, 그 다음에, 상기 구리 씨앗층을 전극으로 사용하는 전기도금법으로 상기 도랑에 구리를 채워넣는 단계를 진행하여 공극이 없는 구리 배선을 쉽게 형성한다.The above concept of the present invention can also be applied to a dual damascene process formed on an insulating film formed by communicating a hole and a trench. That is, forming a copper seed layer by chemical vapor deposition using a surface catalyst on the insulating film formed in communication with the hole and simultaneously filling the hole, and then using an electroplating method using the copper seed layer as an electrode. Filling the groove with copper proceeds to easily form a copper wiring free of voids.
이하, 본 발명의 바람직한 실시예를 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1e는 본 발명의 일 예에 따른 구리배선 형성방법을 설명하기 위한 공정 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming a copper wiring according to an embodiment of the present invention.
도 1a를 참조하면, 먼저, 다마신 또는 이중 다마신 공정을 적용하기 위하여 기판(100) 위의 절연막(110)에 구멍이나 도랑(120)을 형성한다.Referring to FIG. 1A, first, holes or trenches 120 are formed in the insulating film 110 on the substrate 100 to apply a damascene or dual damascene process.
그 다음, 도 1b에 도시된 바와 같이, 스퍼터링 방법으로 질화탄탈륨막(130)과 구리막(140)을 순차적으로 형성한다. 여기서, 질화탄탈륨막(130)은 향후에 그 위에 형성될 구리의 확산을 방지하기 위한 것이다. 그리고, 구리막(140)을 스퍼터링법으로 증착하는 것은 절연막(110)과 잘 접착되도록 하는 것이다. 물론, 스퍼터링법에 의하기 때문에 종횡비가 큰 구멍이나 도랑에는 제대로 형성되지 않을 수도 있으나, 여기서의 구리를 형성시키는 목적은 전기도금에서의 전극을 만들기 위한 것이 아니라 단지 접착력을 개선시키기 위한 것이므로 그 역할을 할 정도로만 형성되면 족하다. 여기에서는 현재 사용하고 있는 스퍼터링 방법으로 형성한 질화탄탈륨 확산방지막과 구리 접착층을 예로 들었지만 폭이 좁은 구리 배선에 적용하기 위해 화학 증착법으로 형성한 확산 방지막을 사용하거나 확산방지막과 구리 사이의 접착력을 좋게 하기 위한 다른 방법을 사용하는 경우에도 마찬가지로 본 발명을 적용할 수 있다.Next, as shown in FIG. 1B, the tantalum nitride film 130 and the copper film 140 are sequentially formed by the sputtering method. Here, the tantalum nitride film 130 is for preventing diffusion of copper to be formed thereon in the future. The deposition of the copper film 140 by the sputtering method is to adhere to the insulating film 110 well. Of course, due to the sputtering method, it may not be formed properly in a hole or a ditch having a high aspect ratio, but the purpose of forming copper here is not to make electrodes in electroplating but merely to improve adhesion, and thus play a role. It is enough to form only. Here, we have used tantalum nitride diffusion barriers and copper adhesive layers formed by the sputtering method currently used, but using diffusion barriers formed by chemical vapor deposition for narrow copper wiring or improving adhesion between the diffusion barrier and copper The same can be applied to the case of using other methods.
다음에 도 1c에 도시한 바와 같이, 구리막(140)이 형성된 결과물상에 아이오딘을 함유하는 표면촉매(150)를 도입한다.Next, as shown in FIG. 1C, a surface catalyst 150 containing iodine is introduced on the resultant product on which the copper film 140 is formed.
그 후에 도 1d와 같이, 구리의 화학증착원료로서 (hfac)Cu(vtms)를 공급하여 화학증착방법으로 구리 씨앗층(160)을 형성한다. 이 때, 구리 씨앗층이 전기도금의전극으로서의 역할을 할 수 있도록, 구리 씨앗층은 충분히 두껍게 형성해야 한다.Thereafter, as shown in FIG. 1D, the copper seed layer 160 is formed by chemical vapor deposition by supplying (hfac) Cu (vtms) as a chemical vapor deposition material of copper. At this time, the copper seed layer should be formed thick enough so that the copper seed layer can serve as an electrode of electroplating.
이어서, 도 1e에 도시한 바와 같이, 구리 씨앗층(160)이 형성된 결과물을 전기도금장치로 옮겨 구멍이나 도랑을 매립용 구리(170)로 채운다.Subsequently, as shown in FIG. 1E, the resultant formed with the copper seed layer 160 is transferred to the electroplating apparatus, and the hole or the trench is filled with the buried copper 170.
한편, 구리 배선의 폭이 좁아질수록 이중 다마신공정에서 전기도금법을 적용하여 도랑 밑의 구멍을 채우는 것은 도랑을 채우는 것에 비해 어렵다. 그러나, 본 발명자들의 선행 한국특허출원 제 99-57939호에 의하면, 표면 촉매를 이용한 화학증착법은 구멍을 바닥부터 채우는 특성이 있기 때문에 핀치오프없이 구멍을 채울 수 있다. 따라서, 구리 씨앗층을 화학증착법으로 형성하는 동안 이중 다마신 구조의 구멍을 채우면 뒤따르는 전기도금에서 도랑만을 채우면 되므로 공극이 없는 구리 배선을 쉽게 형성할 수 있다.On the other hand, as the width of the copper wiring becomes narrower, it is more difficult to fill the hole under the trench by applying the electroplating method in the dual damascene process as compared with filling the trench. However, according to the prior Korean Patent Application No. 99-57939 of the present inventors, the chemical vapor deposition method using a surface catalyst can fill the hole without pinching off because it has the property of filling the hole from the bottom. Therefore, filling the hole of the double damascene structure during the formation of the copper seed layer by chemical vapor deposition, only the grooves in the subsequent electroplating can be easily formed, thereby forming a copper wiring without voids.
도 2a 및 2c는 상기한 구조에서 구리배선을 형성하는 방법을 설명하기 위한 공정 단면도들이다. 도 2a 및 2c에서, 도 1a 내지 1e와 동일한 구성요소는 동일한 참조번호를 붙이고 자세한 설명을 생략하기로 한다.2A and 2C are cross-sectional views illustrating a method of forming a copper wiring in the above structure. In FIGS. 2A and 2C, the same components as in FIGS. 1A through 1E are denoted by the same reference numerals, and detailed description thereof will be omitted.
도 2a를 참조하면, 기판(100) 상에 도전층 패턴(142)와 더불어 평탄화된 층(110)이 형성되어 있으며, 그 위에는 도전층 패턴(142)에 대한 콘택구멍(122)을 가지는 제1 절연층(112)이 형성되어 있다. 제1 평탄 절연층(112) 위에는 얇은 식각저지층(200)이 있으며, 그 위에 콘택구멍(122)과 연통되는 도랑(124)을 가지는 제2 절연층(114)가 형성되어 있다.Referring to FIG. 2A, a planarized layer 110 is formed on the substrate 100 along with a conductive layer pattern 142, and a first hole having a contact hole 122 for the conductive layer pattern 142 is formed thereon. The insulating layer 112 is formed. A thin etch stop layer 200 is formed on the first flat insulating layer 112, and a second insulating layer 114 having a trench 124 communicating with the contact hole 122 is formed thereon.
이와 같이 구멍(122)과 도랑(124)이 있는 구조에서 이중 다마신 공정을 진행하기 위해, 본 발명의 다른 예에서는 도 2b에 도시한 바와 같이 구멍을 표면촉매를 이용한 화학증착법으로 채워 구리 씨앗층(144)을 형성한다. 이 단계에서는 도 1a 내지 1e에서 설명된 공정이 그대로 적용될 수 있다.In order to proceed with the dual damascene process in the structure having the holes 122 and the trench 124 as described above, in another example of the present invention, as shown in FIG. 2B, the hole is filled by chemical vapor deposition using a surface catalyst, and the copper seed layer. 144 is formed. In this step, the process described in FIGS. 1A to 1E may be applied as it is.
그 다음 도 2c에 도시한 바와 같이, 도랑(124)을 매립용 구리(170)로 채운다.Then, as shown in FIG. 2C, the trench 124 is filled with the buried copper 170.
상기한 방법을 사용하면, 도랑 밑의 구멍의 폭이 아주 좁은 경우라도, 용이하게 공극없이 매립이 가능하다.Using the above-described method, even if the width of the hole under the trench is very narrow, it is possible to easily bury without voids.
상술한 바와 같은 본 발명에 따른 구리배선 형성방법에 의하면, 구리 씨앗층을 화학증착법으로 증착하기 때문에, 스퍼터링법으로 구리 씨앗층을 형성할 수 없을 만큼 구멍이나 도랑의 폭이 좁은 경우에도 용이하게 그 구멍이나 도랑에 구리 씨앗층을 형성시킬 수 있다. 따라서, 결과적으로 미세한 콘택홀이나 비아홀도 공극없이 구리로 채울 수 있어 특히 다층배선의 형성에 적합하다.According to the method for forming a copper wiring according to the present invention as described above, since the copper seed layer is deposited by chemical vapor deposition, even if the width of the hole or the trench is narrow so that the copper seed layer cannot be formed by the sputtering method, the copper seed layer is easily formed. A copper seed layer can be formed in the hole or ditch. Therefore, as a result, fine contact holes or via holes can be filled with copper without voids, and are particularly suitable for forming multilayer wiring.
또한, 전기도금법으로 구리를 증착하기 어렵거나 불가능한 부분에만 화학증착법으로 구리를 증착시키고, 나머지 대부분의 구리는 공정비용이 싼 전기도금법으로 증착시키기 때문에, 값비싼 구리 화학증착원료의 사용에 따른 공정비용을 감소시킬 수 있다.In addition, since copper is deposited by chemical vapor deposition only where it is difficult or impossible to deposit copper by electroplating, and most of the other copper is deposited by inexpensive electroplating, the cost of using expensive copper chemical vapor deposition materials is high. Can be reduced.
본 발명은 상기 실시예에만 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
Claims (10)
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990059862A KR20010063028A (en) | 1999-12-21 | 1999-12-21 | Method for forming copper interconnects |
| KR10-2002-7007693A KR100465982B1 (en) | 1999-12-15 | 2000-12-15 | Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst |
| DE60041522T DE60041522D1 (en) | 1999-12-15 | 2000-12-15 | METHOD FOR PRODUCING COPPER INTERCONNECTIONS AND THIN FILMS BY CVD AND A CATALYST |
| PCT/KR2000/001474 WO2001045149A1 (en) | 1999-12-15 | 2000-12-15 | Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst |
| US09/738,213 US6720262B2 (en) | 1999-12-15 | 2000-12-15 | Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst |
| EP00983564A EP1247292B1 (en) | 1999-12-15 | 2000-12-15 | Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst |
| JP2001545352A JP3925780B2 (en) | 1999-12-15 | 2000-12-15 | Method for forming copper wiring and thin film using catalyst and chemical vapor deposition |
| JP2006336417A JP2007123924A (en) | 1999-12-15 | 2006-12-13 | Method of forming copper interconnection and thin film using catalyst and chemical vapor deposition method |
| JP2006336416A JP4792379B2 (en) | 1999-12-15 | 2006-12-13 | Method for forming copper wiring and thin film using catalyst and chemical vapor deposition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990059862A KR20010063028A (en) | 1999-12-21 | 1999-12-21 | Method for forming copper interconnects |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010063028A true KR20010063028A (en) | 2001-07-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990059862A KR20010063028A (en) | 1999-12-15 | 1999-12-21 | Method for forming copper interconnects |
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| KR (1) | KR20010063028A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447232B1 (en) * | 2001-12-28 | 2004-09-04 | 주식회사 하이닉스반도체 | Method for Forming Metal Line in Dual Damascene Structure |
| KR100772551B1 (en) * | 2001-12-19 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
| CN113056107A (en) * | 2021-02-07 | 2021-06-29 | 深圳明阳芯蕊半导体有限公司 | Novel circuit structure and manufacturing process thereof |
-
1999
- 1999-12-21 KR KR1019990059862A patent/KR20010063028A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772551B1 (en) * | 2001-12-19 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
| KR100447232B1 (en) * | 2001-12-28 | 2004-09-04 | 주식회사 하이닉스반도체 | Method for Forming Metal Line in Dual Damascene Structure |
| CN113056107A (en) * | 2021-02-07 | 2021-06-29 | 深圳明阳芯蕊半导体有限公司 | Novel circuit structure and manufacturing process thereof |
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