CN113056107A - Novel circuit structure and manufacturing process thereof - Google Patents
Novel circuit structure and manufacturing process thereof Download PDFInfo
- Publication number
- CN113056107A CN113056107A CN202110181570.5A CN202110181570A CN113056107A CN 113056107 A CN113056107 A CN 113056107A CN 202110181570 A CN202110181570 A CN 202110181570A CN 113056107 A CN113056107 A CN 113056107A
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- Prior art keywords
- layer
- carrying
- copper
- manufacturing process
- circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
Abstract
The invention provides a manufacturing process of a novel circuit structure and the novel circuit structure, wherein the manufacturing process comprises the following steps: s11: forming a circuit layer and an insulating layer covering the circuit layer by a lamination method; s12: forming a trench on the insulating layer; s13: carrying out plasma cleaning, and sputtering bottom copper or chemically depositing copper; s14: pasting a film and carrying out exposure development; s15: carrying out pattern electroplating; s16: film removing treatment; s17: the bottom copper is etched. The manufacturing process of the novel circuit structure improves the fineness of the circuit structure, enhances the binding force between the circuit and the substrate and the conduction performance of the circuit, and is simpler.
Description
Technical Field
The invention relates to the field of circuit structures, in particular to a manufacturing process of a novel circuit structure and the novel circuit structure.
Background
The current manufacturing process of the circuit structure is not beneficial to forming a fine circuit, the bonding force between the circuit and the substrate and the conduction performance of the circuit are poor, and the process flow is complex.
Therefore, it is desirable to improve the manufacturing process of the circuit structure in the prior art to improve the fineness of the circuit structure, enhance the bonding force between the circuit and the substrate and the conductive performance of the circuit, and simplify the manufacturing process.
Disclosure of Invention
In order to solve the technical problem, the invention discloses a manufacturing process of a novel circuit structure, which comprises the following steps: s11: forming a circuit layer and an insulating layer covering the circuit layer by a lamination method; s12: forming a trench on the insulating layer; s13: carrying out plasma cleaning, and sputtering bottom copper or chemically depositing copper; s14: pasting a film and carrying out exposure development; s15: carrying out pattern electroplating; s16: film removing treatment; s17: the bottom copper is etched.
Further, the insulating layer is one of the following layers: PP layer, ABF layer, ceramic resin layer, PI layer and solder mask.
Further, in step S12, grooves are formed by laser drilling and laser grooving, or by exposure and development.
Furthermore, the depth of the groove is 5-25 μm, and the width is 5-50 μm.
Further, steps S14-S17 are replaced with the following steps: S14A: carrying out chemical copper deposition and flash plating; S15A: printing a circuit; S16A: and (6) carrying out surface treatment.
The embodiment of the invention also discloses a manufacturing process of the novel circuit structure, which comprises the following steps: s21: depositing a copper layer on the circuit layer; s22: pasting a film and carrying out exposure development; s23: electroplating the copper column; s24: film removing treatment; s25: etching the copper layer; s26: carrying out laser grooving; s27: sputtering a seed layer; s28: carrying out hole filling electroplating; s29: performing CMP or micro etching; s290: and performing pattern making and surface treatment.
Further, steps S27-S290 are replaced with the following steps: S27A: carrying out chemical copper deposition and flash plating; S28A: printing a circuit: S29A: and (6) carrying out surface treatment.
The embodiment of the invention also provides a manufacturing process of the novel circuit structure, which comprises the following steps: s31: depositing a copper layer on the circuit layer; s32: pasting a film and carrying out exposure development; s33: electroplating the copper column; s34: film removing treatment; s35: etching the copper layer; s36: laminating an insulating layer dielectric material; s37: coating a photoresist and carrying out exposure development; s38: sputtering a seed layer; s39: filling holes and electroplating; s390: performing CMP or micro etching; s391: and (4) pattern making and surface treatment.
The embodiment of the invention also discloses a novel circuit structure which is manufactured by the manufacturing process.
Drawings
FIG. 1 is a flow chart of a process for fabricating a circuit structure according to an embodiment of the present invention;
FIG. 2 is a process flow diagram for fabricating a circuit structure according to an alternative embodiment of the present invention;
FIG. 3 is a flow chart of a process for fabricating a circuit structure according to another embodiment of the present invention;
FIG. 4 is a flow chart of a process for fabricating a circuit structure according to another embodiment of the present invention;
FIG. 5 is a diagrammatic illustration of the novel wiring structure of the present invention;
fig. 6 is a schematic diagram of the novel circuit structure of the present invention.
Detailed Description
The technical solution of the present invention will be further described with reference to the following specific examples, but the present invention is not limited to these examples.
Referring to fig. 1, the manufacturing process of the novel circuit structure of the present invention includes the following steps: s11: forming a wiring layer and an insulating layer covering the wiring layer by a lamination method (as shown in fig. 1 (a)); s12: forming a trench on the insulating layer (as shown in (b) of fig. 1); s13: performing plasma cleaning, and sputtering bottom copper or chemical deposition copper (as shown in (c) of fig. 1); s14: pasting a film (dry film) and performing exposure and development (as shown in (d) of fig. 1); s15: performing pattern plating (as shown in fig. 1 (e)); s16: a film stripping treatment (as shown in (f) of fig. 1); s17: the bottom copper is etched (as shown in fig. 1 (g)).
Further, the insulating layer is one of the following layers: PP layer, ABF layer, ceramic resin layer, PI layer and solder mask.
Further, in step S12, grooves are formed by laser drilling and laser grooving, or by exposure and development.
Furthermore, the depth of the groove is 5-25 μm, and the width is 5-50 μm.
Referring to fig. 2, an alternative embodiment of fig. 1 is shown, which differs from the embodiment of fig. 1 in that steps S14-S17 are replaced with the following steps: S14A: performing electroless copper plating and flash plating (as shown in fig. 2 (a)); S15A: a printed wiring (as shown in fig. 2 (b)); S16A: surface treatment is performed (as shown in fig. 2 (c)).
Referring to fig. 3, another embodiment of the present invention further discloses a manufacturing process of a novel circuit structure, which includes the following steps: s21: depositing a copper layer on the wiring layer (as shown in fig. 3 (a)); s22: pasting a film (dry film) and performing exposure and development (as shown in fig. 3 (b)); s23: plating copper pillars (as shown in fig. 3 (c)); s24: a film removal treatment (as shown in fig. 3 (d)); s25: etching the copper layer (as shown in fig. 3 (e)); s26: performing laser grooving (as shown in (f) of fig. 3); s27: a sputtering seed layer (nickel, copper; titanium, nickel, copper, etc.) (as shown in fig. 3 (g)); s28: performing hole-filling electroplating (as shown in (h) of fig. 3); s29: performing CMP or micro etching (as shown in (i) of fig. 3); s290: patterning and surface treatment were performed (see (j) in fig. 3).
Further, in an alternative embodiment of the present invention, the steps S27-S290 in the above-described embodiment of fig. 3 may be replaced with the following steps: S27A: carrying out chemical copper deposition and flash plating; S28A: printing a circuit: S29A: and (6) carrying out surface treatment.
Another embodiment of the present invention further provides a process for manufacturing a novel circuit structure, which includes the following steps: s31: depositing a copper layer on the wiring layer (as shown in fig. 4 (a)); s32: pasting a film (dry film) and performing exposure and development (as shown in fig. 4 (b)); s33: plating copper pillars (as shown in fig. 4 (c)); s34: a film removal treatment (as shown in fig. 4 (d)); s35: etching the copper layer (as shown in fig. 4 (e)); s36: laminating the dielectric material of the insulating layer (as shown in (f) of fig. 4); s37: coating a photoresist and performing exposure development (as shown in (g) of fig. 4); s38: a seed layer (nickel, copper; titanium, nickel, copper, etc.) (as shown in fig. 4 (h)); s39: hole-filling electroplating (as shown in (i) of fig. 4); s390: performing CMP or micro etching (as shown in (j) of fig. 4); s391: patterning and surface treatment (see (k) of fig. 4).
Referring to fig. 4 and 5, a schematic diagram and a structural diagram of a novel circuit structure manufactured according to the above-described manufacturing process of the present invention are shown, respectively. In fig. 5, reference numeral 1 denotes a bottom layer circuit or a sub-layer circuit thereof, reference numeral 2 denotes a via hole (via filling plating) (laser processing), reference numeral 3 denotes an insulating material layer (e.g., PP, ABF, ceramic resin, PI, SolderMask, etc.), reference numeral 4 denotes a pattern plating via line on the via hole, reference numeral 5 denotes a non-via pattern plating line, reference numeral 6 denotes a trench, reference numeral 7 denotes a plating wire, and reference numeral 8 denotes a plated copper pillar or a soldered copper pillar.
In the manufacturing process, the hole filling electroplating is simpler than the pattern electroplating; negative film etching or laser copper removal is carried out, the pattern flatness is better, and fine circuit manufacturing is facilitated; is beneficial to manufacturing smaller hole-to-hole line-passing patterns. The manufacturing process and the novel circuit structure have the following advantages:
(1) the contact area between the circuit and the base material is increased, so that the bonding force between the circuit and the substrate is enhanced;
(2) the cross section area of the line is increased, the on-resistance is reduced, and the on-performance of the fine line is enhanced;
(3) the process flow is simple.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (9)
1. A manufacturing process of a novel circuit structure is characterized by comprising the following steps:
s11: forming a circuit layer and an insulating layer covering the circuit layer by a lamination method;
s12: forming a trench on the insulating layer;
s13: carrying out plasma cleaning, and sputtering bottom copper or chemically depositing copper;
s14: pasting a film and carrying out exposure development;
s15: carrying out pattern electroplating;
s16: film removing treatment;
s17: the bottom copper is etched.
2. The process of claim 1, wherein the insulating layer is one of the following layers: PP layer, ABF layer, ceramic resin layer, PI layer and solder mask.
3. The process of claim 1, wherein in step S12, the trench is formed by laser drilling and laser grooving or exposure development.
4. The process of claim 3, wherein the trench has a depth of 5-25 μm and a width of 5-50 μm.
5. The manufacturing process of claim 4, wherein the steps S14-S17 are replaced by the steps of:
S14A: carrying out chemical copper deposition and flash plating;
S15A: printing a circuit;
S16A: and (6) carrying out surface treatment.
6. A manufacturing process of a novel circuit structure is characterized by comprising the following steps:
s21: depositing a copper layer on the circuit layer;
s22: pasting a film and carrying out exposure development;
s23: electroplating the copper column;
s24: film removing treatment;
s25: etching the copper layer;
s26: carrying out laser grooving;
s27: sputtering a seed layer;
s28: carrying out hole filling electroplating;
s29: performing CMP or micro etching;
s290: and performing pattern making and surface treatment.
7. The manufacturing process of claim 6, wherein steps S27-S290 are replaced with the steps of:
S27A: carrying out chemical copper deposition and flash plating;
S28A: printing a circuit:
S29A: and (6) carrying out surface treatment.
8. A manufacturing process of a novel circuit structure is characterized by comprising the following steps:
s31: depositing a copper layer on the circuit layer;
s32: pasting a film and carrying out exposure development;
s33: electroplating the copper column;
s34: film removing treatment;
s35: etching the copper layer;
s36: laminating an insulating layer dielectric material;
s37: coating a photoresist and carrying out exposure development;
s38: sputtering a seed layer;
s39: filling holes and electroplating;
s390: performing CMP or micro etching;
s391: and (4) pattern making and surface treatment.
9. A novel circuit structure, characterized by being manufactured by the manufacturing process according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110181570.5A CN113056107A (en) | 2021-02-07 | 2021-02-07 | Novel circuit structure and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110181570.5A CN113056107A (en) | 2021-02-07 | 2021-02-07 | Novel circuit structure and manufacturing process thereof |
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| Publication Number | Publication Date |
|---|---|
| CN113056107A true CN113056107A (en) | 2021-06-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110181570.5A Pending CN113056107A (en) | 2021-02-07 | 2021-02-07 | Novel circuit structure and manufacturing process thereof |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010063028A (en) * | 1999-12-21 | 2001-07-09 | 이경수 | Method for forming copper interconnects |
| CN101312619A (en) * | 2007-05-21 | 2008-11-26 | 无锡江南计算技术研究所 | Manufacturing method for multi-layer high-density interconnected printed circuit board |
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| TW201003859A (en) * | 2008-07-15 | 2010-01-16 | Unimicron Technology Corp | Method for manufacturing structure with embedded circuit |
| TW201021658A (en) * | 2008-11-28 | 2010-06-01 | Phoenix Prec Technology Corp | Circuit board with embedded trace structure and method for preparing the same |
| CN103491729A (en) * | 2012-06-11 | 2014-01-01 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| CN108566734A (en) * | 2018-06-05 | 2018-09-21 | 上海美维科技有限公司 | A method of making printed circuit board using imprint process |
-
2021
- 2021-02-07 CN CN202110181570.5A patent/CN113056107A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010063028A (en) * | 1999-12-21 | 2001-07-09 | 이경수 | Method for forming copper interconnects |
| CN101312619A (en) * | 2007-05-21 | 2008-11-26 | 无锡江南计算技术研究所 | Manufacturing method for multi-layer high-density interconnected printed circuit board |
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| TW201003859A (en) * | 2008-07-15 | 2010-01-16 | Unimicron Technology Corp | Method for manufacturing structure with embedded circuit |
| TW201021658A (en) * | 2008-11-28 | 2010-06-01 | Phoenix Prec Technology Corp | Circuit board with embedded trace structure and method for preparing the same |
| CN103491729A (en) * | 2012-06-11 | 2014-01-01 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| CN108566734A (en) * | 2018-06-05 | 2018-09-21 | 上海美维科技有限公司 | A method of making printed circuit board using imprint process |
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Application publication date: 20210629 |
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