201003859 0802003 27878twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種内埋式線路結構的製作方法，且 .特別是有關於一種不具有電鍍線的内埋式線路結構的製作 方法。 【先前技術】 近年來，隨著電子技術的日新月異，以及高科技電子 《 產業的相I問世，使得更人性化、功能更佳的電子產品不 斷地推陳出新，並朝向輕、薄、短、小的趨勢邁進。在此 趨勢之下，由於線路板具有佈線細密、組裝緊凑及性能良 好等優點，因此線路板便成為承載多個電子元件以及使這 些電子元件彼此電性連接的主要媒介之一。 於驾知技術中，在製作線路板時，通常會在其外部之 線路層及圖案化防焊層（S〇lder mask layer)製作完^之後， 再於線路層所形成之許多接墊(b〇n(jing pa(j)的表面電鑛一 ° ^氧化層，例如一鎳金層(Ni/Au layer) ’以防止由銅製^的 這些接墊的表面氧化，並可增加這些接墊於銲接時的接合 強度。而且，以電鍍的方式形成抗氧化層具有形成速度快 的優點。 又、 、為了對這些接墊之表面進行電鍍製程，這些接墊可分 別連接至一電鍍線(platingbar)，進而與外部之電源相互電 怎並且，在電鐘完成抗氧化層之後’再切除電鑛線 與這些接㈣連結，以使這些接麵此之間 電性、、-邑緣。然而，電鑛線會佔用線路板上有限的線路佈局 5 201003859 vmiW3 2 /878twf doc/n 空間（layout Space)，並 【發明内容】 —^之線路佈局的自由度。 本發明提出一插由1 全面覆蓋線路層的W 構的製作方法，其藉由 局上具有較大的自㈣^成硫化層’ ϋ此其在線路佈 述。首先，提供一具有路結構的製作方法如下所 第二内埋線路的線路板，而埋線路、—核心層以及一 分別内埋於核心層的相對-弟—内埋線路與第二内埋線路 的至少一導電通‘以及二接著，形成貫穿線路板 以及一第二導電層， ，接^電通道的一第一導電層 線路，而第二導電層覆蓋且電性連接第一内埋 然後’於第—導電層上形内埋線路。 層具有至少1-開口以暴露出第：^錢層，第一阻鑑 面。並且，於第二導電芦上 一 —V電層的一第一表 層具有至少一第-門曰/ 一弟二阻鍍層，第二阻鍍 面。之後，於第::面^ -表面亡形成1二抗氧化層。&錢層，並且於弟 接著，移除第-崎層、第 及第二導電層 崎層、第-導電層以 然後，形成1 ίΞΓ 路以及第二内埋線路。 焊層具有ΐ❹第—_線路，且第-防 層。之後，形成—第_幢/—開口暴露出第一抗氧化 -叫層具有至少—細開口 ⑽線路且弟 弟四開D暴露出第二抗氧 201003859 ϋ8ϋ20ϋ3 2 /878twf.doc/n 化層。 在本發明之一實施例中，在形成第一阻鍍層之前，更 包括薄化第一導電層與第二導電層。 在本發明之一實施例中’在薄化第一導電層與第二導 電層之前，更包括在第一導電層與第二導電層之位於導電 通道上的部分分別形成一第一保護層與—第二保護層，並 在薄化第一導電層與第二導電層之後，移除第一保護層與 第二保護層。 在本發明之一實施例中’形成第一抗氧化層與第二抗 氧化層的方法包括電鍍法或無電電鍍法。 在本發明之一實施例中，無電電鍍法包括化學沉積法 或物理沉積法。 在本發明之-實施例中，第一抗氧化層與第二抗氧化 層的材質為鎳與金。 在本發明之一實施例中，移除第—導電層以及第二導 電層的方法包括餘刻。 本發明提出一種内埋式線路結構的製作方法如下所 述。首先，提供一具有至少一内埋線路以及一核心層的線 路板而内埋線路内埋於核心層的—表面。接著，&成貫 穿核心層以及内埋線路的至少一導電通道以及電性連 電通道的-導電層，導電層覆蓋且電性連__ 後，於導電層上形成一阻鍍層，阻鍍層暴露出導電層的二 表面。之後，於第一表面上形成一抗氧化層。接著，移陝 阻鍍層以及未被第一抗氧化層覆蓋的導電層，以顯露内二 201003859 0802003 27878twf.doc/n 線路。然後，形成一防焊層以覆蓋内埋線路，且防焊層暴 露出抗氧化層。 在本發明之一實施例中，在形成阻鍍層之前，更包括 薄化導電層。 在本發明之一實施例中，在薄化導電層之前，更包括 在導電層之位於導電通道上的部分分別形成一保護層，並 在薄化導電層之後，移除保護層。 在本發明之一實施例中，抗氧化層的材質包括鎳與 金。 在本發明之一實施例中，移除導電層的方法包括钱 刻。 本發明提出一種内埋式線路結構包括一核心層、一第 一内埋線路、一第一導電通道、一第一導電層、一第一抗 氧化層與一第一防焊層。第一内埋線路内埋於核心層的一 表面。第一導電通道貫穿核心層以及第一内埋線路的一第 一接墊。第一導電層覆蓋第一接墊以及第一導電通道。第 一抗氧化層形成於第一導電層上。第一防焊層覆蓋第一内 埋線路，且暴露出第一抗氧化層。 在本發明之一實施例中，第一抗氧化層的材質包括鎳 與金。 在本發明之一實施例中，内埋式線路結構更包括一第 二内埋線路、一第二導電通道、一第二導電層、一第二抗 氧化層與一第二防焊層。第二内埋線路内埋於核心層的另 一表面。第二導電通道貫穿核心層以及第二内埋線路的一 201003859 u6uzuuj> z /878twf.doc/n 第二接墊。第二導電層覆蓋第二接墊以及 第二抗氧化層形成於第二導電層上。第二啤 内埋線路，且暴露出第二抗氧化層。 ㈢设里弟一 與金在本發明之—實施财，第^氧化層的材質包括錄 由於本發明是藉由導電層形成抗氧化声， =:=，成習知的電鍍線。因此，=在 線路佈局上具有較大的自由度， 乃隹 的訊號線（即非電鍍線的線路）。' 可配置較多 為讓本發^之上述和其他目的、特徵和優點能更明顯 下。’下文鱗實施例，並配合所關式，作詳細說明[ 【實施方式】 製程:二〜：= 線路結構的圖圖。2〇為本發明另一實施例之内埋式 獻f先，請參照圖1A，提供一線路板110。線路板110 爲疋-内埋式線路板，且内埋式線路板可以是單層或錐 2埋式線路板，本實_是讀層岐式線路板ς 况明，但並非用以限定本發明。 、線，板110具有-第-内埋線路U2、-核心層114 ^及—第二内埋線路116 ’其中核心層114具有-上表面 4a與-下表面U4b，而第—内埋線路ιΐ2與第二内埋線 路116分別内埋於核心層m的上表面_與下表面 9 201003859 u^uzuuj ^/878twf.d〇c/n 114b。第一内埋線路112具有多個第一接墊，第二内埋 線路116具有多個第二接墊P2。 接著，吻參照圖1B’形成貫穿線路板U〇的二導電通 ^ 一以及電性連接導電通紅的―第—導電層⑽以及— ΐίΧ電層13G’這些導電通道c貫穿第—接墊P1與第二 上並变Λ具^而言’第™導電層120配置於上表面114a 埋二= 生路第 112、:且第-導電層12〇與第-内 連接弟二導電層13〇配置於下表面 埋線ί二:内埋線路116 ’且第二導電層130與第二内 屯性連接。值得注意的是，本發明並不限定導 的數量，舉例來說，導電通道c的數量可以是^ 夺☆於線路板11G具有平坦的上表面114a以及下 表面114b，因此筮„道卜 方式形成於上^^%層12G與第二導電層13G以電鍍 的表面，以游:羽a與下表面114b時，也能具有平坦 料無法均勻、、* =知線路板的表面凹凸過大而造成導電材 電屏n二:二積或漏鍍。此外，第一導電層120與第二導 作i掸加U鍍導電通道C時-起形成的，不需分開製 的步驟’因此線路板的製程可進—步簡化。 層1二第：^ 1C ’於本實施例中’薄化第一導電 第一導帝屏〗電層130 ’且薄化的方法包括钱刻，以使 接著，：照圖fi)第二Ϊ電層130的厚度剩下1〜6微米。 層140，且第二 於第一導電層120上形成一第一阻鐵 第—導電声鍍層14G具有―第—開° 〇P1以暴露出 曰 的—第—表面122。並且，於第二導電層 201003859 0802003 27878twf.d〇c/n 130上形成 開口 OP2以暴露出第二導電層削的—第二表面印。详 細而吕，第一開口 OP1暴露出第一導電層12〇之位 接整P1上的部分，而第二開口 0P2暴露出第二導電声⑽ 之位於第二接墊P2上的部分。 曰 "之後，請再次參照圖1D，於第—表面122上形 弟-抗氧化層160,並且於第二表面13 氧化層17〇,其中第—抗氧化層⑽與第j = j ⑽與第二抗氧卿 ===第一導電層12。與第二;電層= ”或電壓的方式，在第—表面122 別形成抗氧化層160與第二抗氧化層⑽。 刀 1, •丨且鍍層150’第二阻鍍層15〇具有 詩意的是’相較於習知技術^在線路層t形成 與第二導⑽=軸“化層，本實_是藉由第一 170。如此；，本二〇丨，弟—與第二抗氧化層160、 M60、17G不會影響第—與第 t = 路佈局，也不會佔用線路板m上的線16的線 f貫施例在線路佈局上具有較大的自由:板 110上可西？曰田度且在線路板 J配置較多的訊號線（即 =第-抗_ _第二抗 疋無電電鍍法，無雷兩辦半 的方法逖可以 法，豆中化學&熟电、又/ 疋化學沉積法或物理沉積 予/儿積法例如是化學氣相沈積，物理沉積法可 11 201003859 umzuuj ^/878twf.d〇c/n 為物^相沈積（例如雜法或蒸鑛法）。 声150、H參^圖1E’移除第一阻鑛層140、第二阻鏟 路及第二導電層咖㈣露第一 與第二抗氧化層_⑽覆i的ΐ ΐ201003859 0802003 27878twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a buried wiring structure, and particularly relates to a buried wiring without an electroplating line The method of making the structure. [Prior Art] In recent years, with the rapid development of electronic technology and the advent of high-tech electronics, the industry's phase I has made more humanized and functional electronic products continue to evolve, and are light, thin, short and small. The trend is moving forward. Under this trend, since the circuit board has the advantages of fine wiring, compact assembly, and good performance, the circuit board becomes one of the main media for carrying a plurality of electronic components and electrically connecting the electronic components to each other. In the driving technique, when the circuit board is fabricated, a plurality of pads formed by the circuit layer are usually formed after the external circuit layer and the patterned solder mask layer are formed. 〇n (jing pa (j) surface electric ore 1 ° ^ oxide layer, such as a nickel / gold layer (Ni / Au layer) 'to prevent the surface of these pads made of copper oxide, and can increase these pads The bonding strength at the time of soldering. Moreover, the formation of the anti-oxidation layer by electroplating has the advantage of rapid formation speed. Moreover, in order to perform electroplating processes on the surfaces of these pads, these pads can be respectively connected to a plating bar. And then with the external power supply, and after the electric clock completes the anti-oxidation layer, 'recut the electric ore line and connect these four (four), so that these junctions are electrically connected to each other. However, electricity The mine line will occupy a limited line layout on the circuit board. 5 201003859 vmiW3 2 /878twf doc/n space (layout space), and [invention content] - the degree of freedom of the line layout. The present invention proposes a plug-in 1 full coverage line Layer W structure It has a large self-disintegration layer on the board, which is described in the line. Firstly, a circuit board having a road structure is provided as follows: the second buried circuit board, and the buried line, a core layer and at least one conductive pass embedded in the core layer and at least one conductive line of the buried circuit and the second buried circuit, and then forming a through-circuit board and a second conductive layer, and connecting the electrical path a first conductive layer line, and the second conductive layer covers and electrically connects the first buried layer and then forms a buried line on the first conductive layer. The layer has at least 1-opening to expose the first: And a first surface layer of the first-V electrical layer on the second conductive reed has at least one first-threshold/first two-resistive plating layer, and the second resisting plating surface. Thereafter, in the first: Face ^ - surface dies to form a second antioxidant layer. & money layer, and then the younger brother, remove the first-sand layer, the second and second conductive layer, the first conductive layer and then form a 1 ΞΓ road and The second buried line. The solder layer has a ΐ❹-- line and a first-proof layer. Forming - the first block / - opening exposes the first antioxidant - the layer has at least a thin opening (10) line and the younger brother D opens a second antioxidant 201003859 ϋ 8 ϋ 20 ϋ 3 2 / 878 twf. doc / n layer. In one embodiment, before forming the first plating resist layer, further including thinning the first conductive layer and the second conductive layer. In one embodiment of the invention, 'before thinning the first conductive layer and the second conductive layer And further comprising forming a first protective layer and a second protective layer on the portions of the first conductive layer and the second conductive layer on the conductive path, and after thinning the first conductive layer and the second conductive layer, moving In addition to the first protective layer and the second protective layer. In one embodiment of the invention, the method of forming the first anti-oxidation layer and the second anti-oxidation layer includes electroplating or electroless plating. In an embodiment of the invention, the electroless plating method comprises a chemical deposition method or a physical deposition method. In an embodiment of the invention, the first anti-oxidation layer and the second anti-oxidation layer are made of nickel and gold. In one embodiment of the invention, the method of removing the first conductive layer and the second conductive layer includes a residual. The present invention proposes a method of fabricating a buried wiring structure as follows. First, a circuit board having at least one buried line and a core layer is provided and the buried line is buried in the surface of the core layer. Next, & is formed into at least one conductive channel of the core layer and the buried circuit and the conductive layer of the electrical connection channel. After the conductive layer is covered and electrically connected, a resist layer is formed on the conductive layer, and the plating layer is formed. The two surfaces of the conductive layer are exposed. Thereafter, an oxidation resistant layer is formed on the first surface. Next, the plating resist and the conductive layer not covered by the first anti-oxidation layer are removed to reveal the inner line 201003859 0802003 27878twf.doc/n. Then, a solder resist layer is formed to cover the buried wiring, and the solder resist layer exposes the oxidation resistant layer. In an embodiment of the invention, the conductive layer is further thinned prior to forming the barrier layer. In an embodiment of the invention, before the conductive layer is thinned, a portion of the conductive layer on the conductive path is respectively formed with a protective layer, and after the conductive layer is thinned, the protective layer is removed. In an embodiment of the invention, the material of the oxidation resistant layer comprises nickel and gold. In one embodiment of the invention, the method of removing the conductive layer includes engraving. The present invention provides a buried circuit structure including a core layer, a first buried circuit, a first conductive via, a first conductive layer, a first anti-oxidation layer and a first solder resist layer. The first buried circuit is buried in a surface of the core layer. The first conductive path extends through the core layer and a first pad of the first buried line. The first conductive layer covers the first pad and the first conductive channel. The first anti-oxidation layer is formed on the first conductive layer. The first solder resist layer covers the first buried wiring and exposes the first anti-oxidation layer. In an embodiment of the invention, the material of the first oxidation resistant layer comprises nickel and gold. In an embodiment of the invention, the buried circuit structure further includes a second buried circuit, a second conductive path, a second conductive layer, a second oxidation resistant layer and a second solder resist layer. The second buried circuit is buried in another surface of the core layer. The second conductive path penetrates the core layer and the second buried circuit of a second pad. The second conductive layer covers the second pad and the second oxidation resistant layer is formed on the second conductive layer. The second beer buried the line and exposed the second antioxidant layer. (3) Setting up Lidi and Jin in the invention - the implementation of the material, the material of the oxide layer includes the recording. Since the present invention forms an anti-oxidation sound by a conductive layer, =:=, a conventional electroplating line. Therefore, = there is a greater degree of freedom in the layout of the line, which is the signal line of the ( (ie, the line of the non-plated line). ' Configurable more to make the above and other purposes, features and advantages of this issue more obvious. The following scale embodiment is described in detail in conjunction with the closed type [Embodiment] Process: 2::= Diagram of the line structure. 2A is a built-in type of another embodiment of the present invention. Referring to FIG. 1A, a circuit board 110 is provided. The circuit board 110 is a 疋-embedded circuit board, and the buried circuit board can be a single layer or a cone 2 buried circuit board, and the actual _ is a read layer 线路 type circuit board, but it is not used to limit the present. invention. The line 110 has a first-embedded line U2, a core layer 114^, and a second buried line 116', wherein the core layer 114 has an upper surface 4a and a lower surface U4b, and the first buried circuit ι2 The second buried circuit 116 is buried in the upper surface _ and the lower surface 9 of the core layer m respectively. 201003859 u^uzuuj ^/878twf.d〇c/n 114b. The first buried line 112 has a plurality of first pads, and the second buried line 116 has a plurality of second pads P2. Next, the kiss is formed with reference to FIG. 1B' to form a two-conducting conductive through-layer U 以及 and a conductive conductive red-transferred "first conductive layer (10) and - ΐ Χ electric layer 13G'. These conductive paths c penetrate through the first pad P1 and The second upper conversion cooker ^the 'the TM conductive layer 120 is disposed on the upper surface 114a, the second conductive layer 112, and the first conductive layer 12 and the first inner conductive layer 13 are disposed under The surface embedding line ί 2: the buried line 116 ′ and the second conductive layer 130 is connected to the second inner raft. It should be noted that the present invention does not limit the number of the conductive. For example, the number of the conductive paths c may be such that the circuit board 11G has a flat upper surface 114a and a lower surface 114b, so that the conductive path c is formed. When the surface of the upper layer 12G and the second conductive layer 13G are plated to swim the feather a and the lower surface 114b, the flat material may not be uniform, and the surface of the circuit board may be excessively uneven. The material screen n 2: two or leakage plating. In addition, the first conductive layer 120 and the second conductive layer are formed by the U-plated conductive channel C, without the need to separate the steps 'therefore the circuit board process Step-by-step simplification. Layer 1 2: ^ 1C 'In this embodiment, 'thinning the first conductive first conductive screen〗 electrical layer 130' and the method of thinning includes money engraving, so that: Figure fi) The thickness of the second electric layer 130 is 1 to 6 micrometers. The layer 140, and the second conductive layer 120 is formed on the first conductive layer 120. The first conductive conductive coating 14G has a "first-open" 〇 P1 to expose the 第-surface 122. And, in the second conductive layer 201003859 0802003 27878twf.d〇c The opening OP2 is formed on the /n 130 to expose the second surface of the second conductive layer. In detail, the first opening OP1 exposes the portion of the first conductive layer 12, which is aligned with P1, and The second opening OP2 exposes a portion of the second conductive sound (10) located on the second pad P2. After that, referring again to FIG. 1D, the first surface 122 is formed on the first surface 122, and the second layer is formed on the first surface 122. Surface 13 oxide layer 17〇, wherein the first anti-oxidation layer (10) and the jth j (10) and the second anti-oxidation === the first conductive layer 12. And the second; the electric layer = ” or the voltage in the manner - Surface 122 forms an oxidation resistant layer 160 and a second oxidation resistant layer (10). Knife 1, • 丨 and plating 150' second barrier layer 15〇 is poetically 'compared with the conventional technique ^ in the formation of the circuit layer t and the second guide (10) = axis "chemical layer, this is _ by One 170. So; the second, the younger brother - and the second antioxidant layer 160, M60, 17G will not affect the first - and t = way layout, nor will it occupy the line f of the line 16 on the board m The embodiment has a large freedom in the layout of the circuit: the signal line on the board 110 can be west and the circuit board J is arranged with a large number of signal lines (ie, the first anti- _ _ second anti-electrostatic electroless plating method, no The method of Ray's two-and-a-half method can be used, the chemical in the bean, the electric power, the chemical deposition method, or the physical deposition method. For example, chemical vapor deposition, physical deposition can be 11 201003859 umzuuj ^/878twf. D〇c/n is the phase deposition of the material (for example, the hybrid method or the steaming method). Acoustic 150, H, and FIG. 1E' remove the first barrier layer 140, the second barrier layer, and the second conductive layer (4) Exposing the first and second antioxidant layers _(10) covering ΐ ΐ
旳弟與弟二導電層12〇、13〇。此 ::’移除第—導電層12〇以及第二導電層心 時線路板110的上表面114a和下表面⑽為 藥劑=高洗殘留的侧液、光阻劑等化學 ^然後，请參照圖1F，形成一第一防焊層180與一第二 防焊層19G以分職蓋第—内埋線路112與第二内埋線路 116。第一防焊層18〇具有一第三開口 ，且第三開口 OP3暴露出第-抗氧化層16〇。第二防焊層刚具有一第 四開口 OP4’且第四開口 〇Ρ4暴露出第二抗氧化層17〇。 此外，請參照圖2A，於其他實施例中，在薄化第一 導電層120與第二導電層130之前，可先在第一導電層12〇 與第二導電層13〇之位於第一接墊P1與第二接墊P2上的 部分分別形成一第一保護層210與一第二保護層22〇。 接著’請參照圖2B，薄化第一導電層120與第二導 電層130。詳細而言，由於第一保護層21〇與第二保護層 22〇分別覆蓋第一導電層120與第二導電層13〇之位於導 電通道C上的部分，因此僅可薄化第一導電層與第二 12 201003859 0802003 27878twf.doc/n 導電層no之未被第一保護層2 的部分。如此—來，第—導ft層22。覆蓋 位於™i與第二===電層⑽之 護層_—保護層训與第二保 更Η 之後可接績圖1D〜 的内埋式線路結構200。值得、、主。日的’而传到圖奶 120盘第-導雷居㈣传/主思的疋’由於第一導電層 弟一¥電層13〇之位於第一接墊p 上的部分較厚，因此當以麵的方式於 接替打 綜上料，树明域㈣咖彡成抗^易漏鑛此 知的電鍍線。如此-來，二二 ==:線路佈局空間。因此，本發明1二 :有較大的自由度，且線路板上可配錄 之I::鍍線的線路）。此外’本發明還可在薄化導電； 二 =層以增厚導電層之位於第一接塾與第= 漏Si況Ϊ:降低之後形成抗氧化層時的電阻並可避免 雖然本發明已以實施例揭露如上 ::二任何所卿具有通常知識者’在=; 明it1，，當可作些許之更動與潤，，因此本發 之保護關當視後附之申請專職圍所界定者為準。 【圖式簡單說明】 圖1A〜gj 1F為本發明—實闕之内埋式線路結構的 13 201003859 usu^uuj 2/878iwf.doc/n 製程剖面圖。 圖2A〜圖2D為本發明另一實施例之内埋式線路結構 的製程剖面圖。 【主要元件符號說明】 110 :線路板 112 :第一内埋線路 114 :核心層 114a :上表面 114b :下表面 116 :第二内埋線路 120 :第一導電層 122 :第一表面 130 :第二導電層 132 :第二表面 140 :第一阻鍍層 150 :第二阻鍍層 160 :第一抗氧化層 170 :第二抗氧化層 180 :第一防焊層 190 :第二防焊層 200 :内埋式線路結構 210 :第一保護層 220 :第二保護層 C :導電通道 14 201003859 usu/uuj ^7878twf.doc/n OPl :第一開口 0P2 :第二開口 0P3 :第三開口 0P4 :第四開口 P1 :第一接墊 P2 :第二接墊The younger brother and the younger two conductive layers 12〇, 13〇. Here:: 'When the first conductive layer 12〇 and the second conductive layer core are removed, the upper surface 114a and the lower surface (10) of the wiring board 110 are chemicals such as a side liquid, a photoresist, etc. of the drug=high wash residue, and then, please refer to 1F, a first solder resist layer 180 and a second solder resist layer 19G are formed to cover the first buried circuit 112 and the second buried line 116. The first solder resist layer 18 has a third opening, and the third opening OP3 exposes the first anti-oxidation layer 16A. The second solder mask has just a fourth opening OP4' and the fourth opening 〇Ρ4 exposes the second anti-oxidation layer 17〇. In addition, referring to FIG. 2A, in other embodiments, before the first conductive layer 120 and the second conductive layer 130 are thinned, the first conductive layer 12 and the second conductive layer 13 may be first connected. A portion of the pad P1 and the second pad P2 respectively form a first protective layer 210 and a second protective layer 22A. Next, please refer to FIG. 2B to thin the first conductive layer 120 and the second conductive layer 130. In detail, since the first protective layer 21〇 and the second protective layer 22〇 respectively cover the portions of the first conductive layer 120 and the second conductive layer 13 that are located on the conductive path C, only the first conductive layer can be thinned. With the second 12 201003859 0802003 27878twf.doc / n conductive layer no is not part of the first protective layer 2. So, come, the first ft layer 22. Covering the buried circuit structure 200 of Figure 1D~ after covering the protective layer of the TMi and the second === electrical layer (10), the protective layer training and the second security. Worth, Lord. The day's pass to the figure 120, the first dish-guided Leiju (four) pass / the main thought of the 疋 'Because the first conductive layer of the younger layer of the electric layer 13 〇 is located on the first pad p is thicker, so when In the face of the way to take over the mining, the tree Ming domain (four) curry into the resistance of the easy to mine this known plating line. So - come, two two ==: line layout space. Therefore, the present invention has a greater degree of freedom and can record the I:: plating line of the circuit board). In addition, the present invention can also be used to thin the conductive; the second layer is used to thicken the conductive layer in the first interface and the first drain and the drain state, and the resistance is formed after the formation of the anti-oxidation layer, and although the present invention has been The embodiment discloses the above: 2: Any person who has the usual knowledge 'in the =; Ming it1, when a little change and run can be made, therefore, the protection of the issue is defined by the application of the full-time enclosure. quasi. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to gj 1F are cross-sectional views of a process of a buried circuit structure of the present invention, which is 13 201003859 usu^uuj 2/878iwf.doc/n. 2A to 2D are cross-sectional views showing a process of a buried circuit structure according to another embodiment of the present invention. [Main component symbol description] 110: circuit board 112: first buried circuit 114: core layer 114a: upper surface 114b: lower surface 116: second buried wiring 120: first conductive layer 122: first surface 130: The second conductive layer 132: the second surface 140: the first plating resist 150: the second plating resist 160: the first anti-oxidation layer 170: the second anti-oxidation layer 180: the first solder resist layer 190: the second solder resist layer 200: Buried line structure 210: first protective layer 220: second protective layer C: conductive path 14 201003859 usu/uuj ^7878twf.doc/n OPl: first opening 0P2: second opening 0P3: third opening 0P4: Four openings P1: first pad P2: second pad