KR101069630B1 - Method for fabricating metal line using adsorption inhibitor in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device using an adsorption inhibitor, the method for forming a metal wiring of a semiconductor device according to the present invention, forming an insulating layer on a semiconductor substrate having a lower structure, and on the insulating layer Forming a trench or via hole in a predetermined pattern; On the semiconductor substrate having the trench or via hole formed thereon, a deposition process for depositing the conductive material and an adsorption suppression process for suppressing adsorption of the conductive material are continuously and stepped until the trench or via hole is filled with the conductive material. Performing the at least one method selected from a cyclic method to form a conductive layer; Forming a metal wiring by removing the conductive layer except for the trench or via hole by performing the conductive layer removing process until the upper portion of the insulating layer is exposed. According to the present invention, there is an advantage that uniform deposition without voids or connecting lines is possible when forming metal wiring.

Deposition, Voids, Adsorption Inhibitors, Copper, Trench

Description

Method for fabricating metal line using adsorption inhibitor in semiconductor device

The present invention relates to a method for forming a metal wiring of a semiconductor device using an adsorption inhibitor, and more specifically, to the metal wiring through the uniform deposition by selectively performing the adsorption suppression process and the conductive material deposition process during the deposition for forming the metal wiring It relates to a method for forming metal wiring of a semiconductor device using the adsorption inhibitor to form a.

Recently, due to the increase in the degree of integration of semiconductor devices, the minimum line width of metal wirings has been reduced, the aspect ratio has been increased, and the wiring structure has been multilayered. In order to manufacture integrated circuit (IC) devices having such a structure, reliability, speed, and manufacturing cost reduction issues have been raised, and new wiring processes and material development for this issue have been of great concern in the related field.

In order to form such a metal wire, conventionally, aluminum was used as a material. However, such a metal wiring using aluminum cannot satisfy problems such as securing reliability, improving speed, and securing stability of devices, and at present, semiconductor devices using copper as a metal wiring material have been manufactured. In addition, since the resistivity of the deposited metal is increased in the wiring structure having a nanoscale, it is difficult to secure the reliability of the device. Thus, the metal wiring using the copper alloy that can alleviate the increase in resistance due to the reduction of the cross-sectional area is used. Research is also in progress.

In the case of forming the metal wiring through copper or copper alloy, the specific resistance is lower than that of conventional aluminum to increase the signal transmission speed, and the melting point is high, so the resistance to electro-migration (EM) is large. It is known that the stability of the. In addition, the copper alloy is known to have an effect of suppressing the increase of the resistivity, corrosion and peeling phenomenon due to the reduction of the cross-sectional area when applied to the nanoscale metal wiring structure.

In the case of forming the metal wiring using the copper or copper alloy, it is difficult to remove through the etching process, a process technology called damascene has been introduced to overcome this problem. The damascene process is a method of forming a trench for circuit wiring in an insulating layer on which a copper metal wiring is to be located, and forming the copper metal wiring by completely filling the trench with copper or a copper alloy. The damascene process technology is well known to those skilled in the art to which the present invention pertains, and further description thereof will be omitted.

For the damascene process, the following method is used as a method of filling the inside of the trench with a conductive material. That is, electro-plating, electroless plating, physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD), and the like.

In the case of the physical vapor deposition method (PVD), due to the inherent straightness of the deposited copper particles can not satisfy the step coverage and buried characteristics required in the nano-scale high aspect ratio trench or via hole. have.

In the case of the electroplating method, it has a low manufacturing cost and excellent step coverage, but a copper seed layer capable of promoting homogeneous copper nucleation must be premised, and a nanoscale high aspect ratio trench or via hole is generated. There is a limitation in forming a copper alloy which can solve the increase in the resistivity of the copper thin film.

In the case of the electroless plating method, there is a disadvantage that the deposition rate of the copper thin film is very slow.

The organic metal chemical vapor deposition method has a lower deposition rate and higher cost than the electroplating method, but does not require a copper seed layer, and can solve problems of relatively excellent step coverage and increase in specific resistance caused by nanoscale wiring. The advantage is that the deposition of copper alloys is relatively easy.

In the case of depositing copper or a copper alloy through the above-described deposition methods, for example, voids or connecting lines in the deposition process in a copper metal wiring process having a high aspect-ratio at nanoscale. seam) is formed, thereby deteriorating the reliability of the semiconductor device. Therefore, there is a need for a method of uniformly depositing a conductive layer from the bottom of the trench to the top inlet without voids or connecting lines.

Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device using an adsorption inhibitor that can overcome the above-mentioned conventional problems.

Another object of the present invention is to provide a method for forming metal wirings of a semiconductor device using an adsorption inhibitor that can be uniformly deposited without voids or connecting lines.

It is still another object of the present invention to provide a method for forming metal wiring of a semiconductor device using an adsorption inhibitor that can improve the reliability of the metal wiring and the semiconductor device.

Still another object of the present invention is to provide a method for forming metal wirings of a semiconductor device using an adsorption inhibitor suitable for forming nanoscale metal wirings.

According to an embodiment of the present invention for achieving some of the technical problems described above, the method for forming a metal wiring of the semiconductor device according to the present invention, forming an insulating layer on a semiconductor substrate on which a lower structure is formed, and a predetermined on the insulating layer Forming trenches or via holes in the pattern; On the semiconductor substrate where the trench or via hole is formed, a deposition process for depositing the conductive material and an adsorption suppression process for suppressing adsorption of the conductive material are continuously performed until the trench or via hole is filled with the conductive material. Performing at least one method selected from a stepwise and a cyclic method to form a conductive layer; Forming a metal wiring by removing the conductive layer except for the trench or via hole by performing the conductive layer removing process until the upper portion of the insulating layer is exposed.

After forming the trench or via hole and before forming the conductive layer, the method may further include forming a diffusion barrier layer on the semiconductor substrate on which the trench or via hole is formed to prevent diffusion of the conductive layer. have.

After forming the diffusion barrier layer and before forming the conductive layer, forming a metal barrier layer on the semiconductor substrate on which the diffusion barrier layer is formed to improve nucleation and adhesion strength during deposition of the conductive material. It may be further provided.

The conductive material may be copper or a copper alloy.

The conductive layer may be formed by organometallic chemical vapor deposition (MOCVD).

The formation of the conductive layer using the copper may be performed using any one copper precursor selected from (hfac) CuVTMOS series, (hfac) CuTMVS series, and (hfac) CuDMB series.

Formation of the conductive layer using the copper alloy, aluminum (Al), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta) to the copper precursor ), And tin (Sn) may be performed by further adding at least one precursor among the metal precursors including as a main component.

The adsorption suppression process is performed by adsorption inhibitor gas molecules or radicals to form the conductive material on the upper surface of the trench or via hole and the upper surface of the semiconductor substrate except for the inside of the trench or via hole. It may be a process for suppressing deposition.

The adsorption inhibitor is any one selected from gas molecules with hydrogen (H) including H ₂ , NH ₃ , N ₂ H ₂ , H ₂ S, HI, CH ₄ , C ₂ H ₂ , and C ₂ H ₆ Gas radicals or hydrogen radicals generated from a plasma of any one of the gas molecules selected above, and the radicals may be diluted with nitrogen (N ₂ ) or argon (Ar) gas.

The diffusion barrier layer and the metal barrier layer may be formed through an atomic layer deposition (ALD) method.

The diffusion barrier layer may be made of any one material selected from Ti, TiN, TiSiN, Ta, TaN, TaSiN, W, and WN.

The metal barrier layer may be made of any one material selected from Cu, Os, Ir, Ru, Co, and Pd.

After forming the metal barrier layer, a lower surface of the trench may be treated with a surface catalyst to increase the growth rate of the conductive material.

The removal of the conductive layer in the step of removing the conductive layer except for the trench or via hole is performed through a chemical mechanical polishing (CMP) process in which the semiconductor substrate on which the conductive layer is formed is polished until the insulating layer is exposed. Can be performed.

The conductive layer may have a structure formed on the semiconductor substrate and electrically connected to a separate metal line existing under the trench or via hole.

According to the present invention, there is an advantage that uniform deposition without voids or connecting lines is possible when forming metal wiring. Through this, it is possible to secure the reliability of the metal wiring and the semiconductor device. In addition, there is an advantage that is suitable for forming a metal aspect of the nano-scale high aspect ratio trench or via hole.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings without intending to intend to provide a thorough understanding of the present invention to a person having ordinary skill in the art to which the present invention belongs.

1 to 6 are cross-sectional views of a process sequence for forming a metal wiring of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1, the insulating layer 110 is formed on the semiconductor substrate 100 on which the lower structure is formed at a predetermined thickness.

Although not shown in the drawings, the lower structure of the semiconductor substrate 100 may include a transistor including a source, a drain, and a gate, a word line, a bit line, and the like. It may also include wiring or contacts connected to the transistor, the word line, or the bit line. That is, the metal wiring formed by the present invention may be for being electrically connected to at least one lower wiring or contact included in the lower structure of the semiconductor substrate, or electrically connected to the lower structure of the semiconductor substrate. It may be to be connected to other parts (adjacent elements, wiring, etc.) without being. Therefore, the upper surface of the semiconductor substrate 100 in contact with the insulating layer 110 may be formed of various insulating layers, various conductive layers, or some insulating layers and some conductive layers.

The insulating layer 110 may be formed of an insulating material having a low dielectric constant value. For example, the insulating layer 110 may be an insulator such as boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), plasma enhanced-tetra ethyl ortho silicate (PE-TEOS), or high density plasma (HDP) oxide. In addition, various insulating materials known to those skilled in the art may be used to form the insulating layer 110. The insulating layer 110 may be trenched in a subsequent process. It may be formed to a thickness enough to form a via hole.

As shown in FIG. 2, a portion of the insulating layer 110 is etched to form a trench or via hole (hereinafter referred to as a trench) 120. An inner bottom portion of the trench 120 may be formed to expose the semiconductor substrate 100.

The trench 120 may be formed through a photo process and an etching process. Methods of forming the trenches are well known to those of ordinary skill in the art.

If necessary, an etch stop layer (not shown) may be first formed on the semiconductor substrate 100, and then the insulating layer 120 may be formed. The etch stopper layer is to prevent damage to the semiconductor substrate 100 due to overetching when the trench 120 is formed. The etch stop layer may be formed of a material having a different etching selectivity from the insulating layer 110, for example, a nitride film. At this time, the etch stop layer remaining on the bottom of the trench 120 is removed through a separate process.

As shown in FIG. 3, the diffusion barrier layer 130 and the metal barrier layer 140 are sequentially formed on the semiconductor substrate 100 on which the trench 120 is formed. In some cases, the process of forming the diffusion barrier layer 130 and the metal barrier layer 140 or any one of them may be omitted.

The diffusion barrier layer 130 is formed to prevent the deposited conductive material from diffusing into the insulating layer 110 during the deposition of a conductive material for forming a metal wiring in a subsequent process. This may be necessary, especially when depositing copper or copper alloys. However, when the insulating layer 110 has a unique material to prevent the diffusion of the conductive material, or when the conductive material has a material that does not diffuse into the insulating layer 110, the diffusion barrier layer 130 The formation process of may be omitted.

 The diffusion barrier layer 130 may be formed of any one material selected from Ti, TiN, TiSiN, Ta, TaN, TaSiN, W, and WN.

The metal barrier layer 140 may be formed to improve nucleation and adhesion of the conductive material in a subsequent deposition process of the conductive material. Therefore, when the nucleation and adhesion of the conductive material are not required, the process of forming the metal barrier layer 140 may be omitted.

The metal barrier layer 140 may be formed of any one material selected from Cu, Os, Ir, Ru, Co, and Pd. In addition, the metal barrier layer 140 may be formed of 1 ~ 5nm.

The diffusion barrier layer 130 and the metal barrier layer 140 may be formed using atomic layer deposition (ALD) with excellent step coverage for uniform formation in the high aspect ratio trench of the nanoscale. When the trench 120 formed in FIG. 2 is not a nano-scale high aspect ratio trench, in addition to the atomic layer deposition method (ALD), deposition methods well known to those having ordinary skill in the art to which the present invention pertains may be made. The diffusion barrier layer 130 and the metal barrier layer 140 may be formed.

After the metal barrier layer 140 is formed, if necessary, a surface catalyst is treated on the surface of the metal barrier layer 140 in the lower portion of the trench, so that the conductive material is deposited during the deposition process of the conductive material for forming metal wiring in a subsequent process. Processes to speed up growth may be included.

As shown in FIGS. 4 and 5, the conductive layers 150a and 150b may be formed by depositing a conductive material on the semiconductor substrate 100 on which the diffusion barrier layer 130 and the metal barrier layer 140 are formed. The deposition process is performed.

4 is a cross-sectional view illustrating the conductive layer 150a when the deposition of the conductive material is about halfway, and FIG. 5 is a cross-sectional view of the conductive layer 150b when the deposition of the conductive material is completed.

Unlike the conventional method, the deposition process is performed in parallel with a process through adsorption inhibitor gas molecules or radicals. The adsorption inhibitor inhibits deposition or adsorption of the conductive material on the upper portion of the trench 120. In other words, the adsorption inhibitor treatment process and the deposition process of the conductive material may be performed through a method selected from among various methods (eg, continuous, stepwise, cyclic, etc.) as necessary. Here, continuous refers to continuously injecting and treating the adsorption inhibitor while the conductive material is deposited, and stepping refers to continuously treating the adsorption inhibitor with a certain period during the deposition of the conductive material. The term "cyclic" means alternating deposition of the conductive material and treatment of an adsorption inhibitor.

Deposition of the conductive material at the same time as the treatment of the adsorption inhibitor gas molecules or radicals can suppress the growth of the copper thin film on the trench 120. The concept is as follows.

When the adsorption inhibitor gas molecules or radicals are processed into the reactor of the manufacturing apparatus, the adsorption inhibitor gas molecules or radicals do not reach the lower portion of the nanoscale high aspect ratio trench, and are adsorbed only on the upper portion of the high aspect ratio trench 120 to remain. Done. Adsorption inhibitor gas molecules or radicals remaining on the upper portion of the high aspect ratio trench 120 prevent the conductive material from adsorbing on the upper portion of the trench 120. Accordingly, the conductive material 150 reaches the lower portion of the trench 120 where the adsorption inhibitor gas molecules or radicals are difficult to reach, thereby inducing a chemical reaction and forming the conductive layer 150.

The adsorption inhibitor gas molecules or radicals are treated with hydrogen (H ₂ ), ammonia (NH ₃ ), hydrazine (N ₂ H ₂ ), hydrogen sulfide (H ₂ S), hydrogen iodide (HI), methane (CH ₄ ), ethyne Gas molecules containing hydrogen such as (C ₂ H ₂ ), ethane (C ₂ H ₆ ), radicals containing hydrogen generated from plasma thereof, and diluting nitrogen (N ₂ ) or argon (Ar) to these gases Treatment is performed using any one selected from one of the gases.

As described above, when the adsorption inhibitor treatment and the deposition of the conductive material are combined, it is possible to prevent the generation of voids or connecting wires, which was pointed out as a problem in the conventional case, so that the uniform conductive layer, that is, the uniform metal wiring Formation is possible.

The conductive material for forming the metal wire may be copper or a copper alloy. In addition, the deposition of the conductive material may use an organometallic chemical vapor deposition (MOCVD).

The copper precursor used when the conductive layers 150a and 150b are formed of copper may be any one material selected from (hfac) CuVTMOS series, (hfac) CuTMVS series, and (hfac) CuDMB series.

In addition, when the copper alloy conductive layers 150a and 150b are formed, aluminum (Al), silver (Ag), cobalt (Co), tungsten (W), and titanium may be formed on any one of the copper precursors selected from the above copper precursors. Synthetic materials added by selecting at least one of organometallic precursors including (Ti), nickel (Ni), tantalum (Ta), tin (Sn), and the like as main components may be used. Wherein the copper alloy may be a composition ratio of 0.1 to 10 at.% Of the additive to the copper.

As illustrated in FIG. 5, the conductive layer 150b having completed the deposition through the deposition process through the adsorption inhibitor treatment has a structure that enables a uniform thin film without voids or connecting lines.

As shown in FIG. 6, the conductive layer of the remaining portion except for the conductive layer 150b (which is included in the case where the diffusion barrier layer 130 and the metal barrier layer 140 are formed) is formed in the trench 120. 150b (including the diffusion barrier layer 130 and the metal barrier layer 140) is removed. That is, the removal process is performed such that the conductive layer 150b (including the diffusion barrier layer 130 and the metal barrier layer 140) is present only in the trench 120.

The removal process is performed through a planarization process, and is generally performed through a chemical mechanical polishing (CMP) process until the upper surface of the insulating layer 110 is exposed. Accordingly, the metal wiring 150c is formed in the trench 120.

Thereafter, a washing process may be additionally performed.

The foregoing description of the embodiments is merely illustrative of the present invention with reference to the drawings for a more thorough understanding of the present invention, and thus should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention.

1 to 6 are process cross-sectional views illustrating metal wiring formation according to an embodiment of the present invention in a process order.

* Description of the symbols for the main parts of the drawings *

100: semiconductor substrate, 110: insulating layer

120: trench 130: diffusion barrier layer

140: metal barrier layer 150a, 150b: conductive layer

150c: metal wiring

Claims (17)

In the metallization method of the semiconductor device: Forming an insulating layer on the semiconductor substrate on which the substructure is formed, and forming a trench or via hole in a predetermined pattern on the insulating layer; On the semiconductor substrate on which the trench or via hole is formed, a deposition process for depositing a conductive material and an adsorption suppression process for suppressing adsorption of the conductive material are continuously, stepwise, until the trench or via hole is filled with the conductive material. Performing at least one method selected from a cyclic method to form a conductive layer; Forming a metal wiring by removing the conductive layer except for the trench or via hole by performing the conductive layer removing process until the upper portion of the insulating layer is exposed; The adsorption suppression process adsorbs an adsorption inhibitor gas molecule or radical onto a surface, thereby conducting the conductive layer on an upper surface of the trench or via hole and an upper surface of the semiconductor substrate except for the inside of the trench or via hole. To suppress the deposition of materials, The adsorption inhibitor is any one selected from gas molecules with hydrogen (H) including H ₂ , NH ₃ , N ₂ H ₂ , H ₂ S, HI, CH ₄ , C ₂ H ₂ , and C ₂ H ₆ And a gas molecule selected from radicals including hydrogen generated from the plasma of any one selected gas molecule . The method according to claim 1, And forming a diffusion barrier layer on the semiconductor substrate on which the trench or via hole is formed, before forming the trench or via hole, to prevent diffusion of the conductive layer. Metal wire forming method characterized in that. The method according to claim 2, After forming the diffusion barrier layer and before forming the conductive layer, forming a metal barrier layer on the semiconductor substrate on which the diffusion barrier layer is formed to improve nucleation and adhesion strength during deposition of the conductive material. Metal wiring forming method characterized in that it further comprises. The method according to claim 1 or 3, The conductive material is a metal wiring forming method, characterized in that the copper or copper alloy. The method according to claim 4, Forming the conductive layer is a metal wiring formation method, characterized in that the organic metal chemical vapor deposition (MOCVD) is used. The method according to claim 5, Forming the conductive layer using the copper is a metal wiring forming method characterized in that it is performed using any one of the copper precursor (precursor) selected from (hfac) CuVTMOS series, (hfac) CuTMVS series, and (hfac) CuDMB series . The method according to claim 6, Formation of the conductive layer using the copper alloy, aluminum (Al), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta) to the copper precursor And at least one precursor from among metal precursors containing any one selected from tin) and tin (Sn) as a main component. The method of claim 7, The copper alloy is a metal wiring forming method, characterized in that the composition ratio of the additive to copper is 0.1 ~ 10 at.% delete The method according to claim 1, The adsorption inhibitor is a metal wiring formation method, characterized in that the radical containing the hydrogen diluted with nitrogen (N ₂ ) or argon (Ar) gas. The method of claim 3, The diffusion barrier layer and the metal barrier layer is formed through the atomic layer deposition (ALD) method. The method of claim 11, The diffusion barrier layer is any one selected from titanium, TiN, and TiSiN-based materials including titanium, Ta, TaN, and TaSiN-based materials including tantalum-based materials, and W and WN-based materials. Metal wiring forming method characterized in that. The method according to claim 12, The metal barrier layer is a metal wiring forming method, characterized in that the material of any one selected from Cu, Os, Ir, Ru, Co, Pd. 14. The method of claim 13, The metal barrier layer is a metal wiring forming method, characterized in that having a thickness of 1 ~ 5nm. The method according to claim 14, And forming a surface catalyst under the trench to increase the growth rate of the conductive material after the metal barrier layer is formed. The method according to claim 4, The removal of the conductive layer in the step of removing the conductive layer except for the trench or via hole is performed through a chemical mechanical polishing (CMP) process in which the semiconductor substrate on which the conductive layer is formed is polished until the insulating layer is exposed. Method for forming metal wiring, characterized in that carried out. The method according to claim 4, And the conductive layer is formed on the semiconductor substrate and has a structure electrically connected to a separate metal wire existing under the trench or via hole.

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