KR20090034035A - Method of manufacturing metal wiring for semiconductor device - Google Patents

Method of manufacturing metal wiring for semiconductor device Download PDF

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Publication number
KR20090034035A
KR20090034035A KR1020070099174A KR20070099174A KR20090034035A KR 20090034035 A KR20090034035 A KR 20090034035A KR 1020070099174 A KR1020070099174 A KR 1020070099174A KR 20070099174 A KR20070099174 A KR 20070099174A KR 20090034035 A KR20090034035 A KR 20090034035A
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KR
South Korea
Prior art keywords
forming
diffusion barrier
semiconductor device
metal wiring
film
Prior art date
Application number
KR1020070099174A
Other languages
Korean (ko)
Inventor
최중일
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070099174A priority Critical patent/KR20090034035A/en
Publication of KR20090034035A publication Critical patent/KR20090034035A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating

Abstract

In the method of forming a metal wiring of a semiconductor device according to the present invention, forming an insulating film having a damascene pattern on the semiconductor substrate, forming a diffusion barrier on the insulating film including the damascene pattern, the surface of the diffusion barrier Pretreating a surface of the diffusion barrier to remove oxides, forming a metal layer using an electroless plating method to embed the damascene pattern on the pretreated diffusion barrier, and forming the metal layer and the diffusion barrier Removing the insulating film until the insulating film is exposed.

Description

METHODS OF MANUFACTURING METAL WIRING FOR SEMICONDUCTOR DEVICE

The present invention relates to a metal wiring of a semiconductor device and a method of forming the same, and more particularly, to a metal wiring and a method of forming a semiconductor device that can improve the deposition characteristics of the copper film when forming a copper wiring using the electroless plating method. It is about.

In general, a metal element is formed in the semiconductor element to electrically connect the element and the element, or the interconnection and the interconnection, and a contact plug is formed to connect the upper metal interconnection and the lower metal interconnection.

On the other hand, according to the trend of high integration of semiconductor devices, design rules are reduced, and the aspect ratio of contact holes in which the contact plugs are formed is gradually increasing. Therefore, the difficulty and importance of the process of forming the metal wiring and contact plug is increasing.

Aluminum (Al) and tungsten (W), which have excellent electrical conductivity, have been mainly used as the material for the metallization, and in recent years, the RC signal delay in high-integrated high-speed operation devices has much higher electrical conductivity and lower resistance than the aluminum and tungsten. Research into using copper (Cu) as a next-generation metallization material that can solve the problem is being conducted.

However, in the case of copper, since it is not easy to dry-etch in the form of wiring, a new process technology called damascene is used to form metal wiring with copper. The damascene metal interconnection process is a technique of forming a damascene pattern by etching an interlayer insulating film, and forming the metal interconnection by embedding the damascene pattern with a copper film. It can be divided into dual-Damascene process.

In the case of applying the damascene process, not only the upper metal wiring and the contact plug for contacting the upper metal wiring and the lower metal wiring in the multi-layer metal wiring can be formed at the same time, but also the steps generated by the metal wiring can be eliminated. As it can be removed, there is an advantage of facilitating subsequent processes.

Here, in the case where the copper film is applied to the lower metal interconnection and the multilayer metal interconnection of the aluminum film is applied to the upper metal interconnection using the damascene process as described above, the high-resistance compound may be A silicide film which functions as a diffusion barrier or a diffusion barrier should be formed at the contact interface between the copper film and the aluminum film to prevent the formation.

On the other hand, as a copper deposition method for forming a copper wiring, sputtering, chemical vapor deposition (CVD), or electroless plating is generally used.

The copper wiring forming method by the electroless plating method has disadvantages of environmental pollution, but has advantages such as high deposition rate, low test cost, convenience of deposition, and selective deposition of copper film.

However, in the above-described prior art, when the metal wiring of the semiconductor device using copper is formed, excellent adhesion property to copper is required to the diffusion barrier film. When the copper film is deposited by the electroless plating method, the diffusion is performed. The prevention film falls to the adhesion characteristic with respect to a copper film.

In particular, when the copper film is deposited by the electroless plating method as described above, due to the oxides generated on the surface of the silicide film during the formation of the diffusion barrier film such as silicide, the adhesion property to the copper film on the silicide film is lower than that of the diffusion barrier film. Will be.

The present invention provides a method for forming a metal wiring of a semiconductor device capable of removing oxides when forming a diffusion barrier layer in a metal wiring of a semiconductor device using copper.

In addition, the present invention provides a method for forming a metal wiring of a semiconductor device that can improve the adhesion characteristics to copper by removing the oxide when forming a diffusion barrier in the metal wiring of the semiconductor device to which copper is applied as described above.

In accordance with another aspect of the present invention, a method of forming a metal wiring of a semiconductor device includes: forming an insulating film having a damascene pattern on a semiconductor substrate; Forming a diffusion barrier on the insulating film including the damascene pattern; Pretreating the surface of the diffusion barrier to remove oxides on the surface of the diffusion barrier; Forming a metal film by using an electroless plating method to fill the damascene pattern on the pretreated diffusion barrier film; And removing the metal layer and the diffusion barrier layer until the insulating layer is exposed.

The damascene pattern is formed in a single structure.

The damascene pattern is formed in a dual structure.

The diffusion barrier layer is formed of any one of TiSi, TaSi, CoSi, TiN, Ta, TaN, W, WN, Cr, and Nb.

And performing a N 2 plasma treatment on the semiconductor substrate including the insulating film on which the diffusion barrier is formed, between the forming of the diffusion barrier and performing the activation pretreatment process.

The N 2 plasma treatment was PECVD (Plamsa Enhanced Chemical) for a time of 40-80 minutes with a power of 90-110 W, a flow rate of 40-60 sccm and a process pressure of 600-640 mTorr at an initial vacuum pressure of 4-6 * 10 -6 Torr. Vapor Deposition).

The pretreatment process may be performed by using 0.01 to 0.05 g of PdCl 2 , 0.1 to 0.5 ml of HCl, 10 to 100 ml of glacial acetic acid, 10 to 50 ml of DI water, and 1 to 10 ml of HF mixed solution. Do it.

The forming of the metal film comprises 5 to 15 g / l CuSO 4.5H 2 O, 40 to 80 ml HCHO (37%), 250 to 350 ml / l CH 3 OH, 30 to 50 g / l NaOH and 25 using a plating solution KNa 2 H 4 O 8 .4H 2 O mixed electroless ~35g / l is carried out for 15-35 minutes at a temperature of 40~80 ℃.

Therefore, the present invention can remove oxides generated on the surface of the diffusion barrier film.

In addition, the present invention can promote the nucleation of copper by forming a Pd nucleus on the surface of the diffusion barrier film, it is possible to improve the adhesion properties of the diffusion barrier film to copper.

In addition, in the present invention, before performing the activation pretreatment, first, by performing N 2 plasma treatment, the oxide can be more effectively removed, thereby further improving the adhesion property of the diffusion barrier film to copper.

First, the technical principle of the present invention will be briefly described. In the present invention, when forming a metal wiring of a semiconductor device using copper, the diffusion barrier layer is formed, followed by activation pretreatment or N 2 plasma treatment and activation pretreatment. Then, a copper film is formed using an electroless plating method to form a metal wiring.

In this way, oxides generated on the surface of the diffusion barrier layer such as silicide can be removed by the above activation pretreatment, and Pd nuclei are formed on the surface of the diffusion barrier layer by the activation pretreatment. When forming a copper film using the electroless plating method, it is possible to promote the nucleation of copper.

Therefore, since nucleation of copper can be promoted due to Pd nucleation as described above, adhesion characteristics of the diffusion barrier film to copper can be improved.

In addition, by performing the N 2 plasma treatment before the activation pretreatment, the oxide may be more effectively removed, thereby further improving the adhesion property of the diffusion barrier to copper.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A through 1F are cross-sectional views illustrating processes for forming a metal wiring of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, an insulating film 102 is formed on a semiconductor substrate 100 on which substructures (not shown) such as gates and bit lines are formed. Then, a mask pattern (not shown) is formed on the insulating film 102 to form contact holes or trenches for forming subsequent metal wirings, and the insulating film 102 is formed by using the mask pattern as an etching mask. Is etched to form a damascene pattern (D).

The damascene pattern D may be formed by applying a single damascene structure having a trench or a contact hole or a dual structure having a trench and a contact hole.

Referring to FIG. 1B, the diffusion barrier layer 103 is formed on the insulating layer 102 including the damascene pattern D. Referring to FIG.

The diffusion barrier 103 is formed of any one of TiN, Ta, TaN, W, WN, Cr, and Nb or any one of silicide-based TiSi, TaSi, and CoSi.

Referring to FIG. 1C, an N 2 plasma treatment 104 is performed on the semiconductor substrate 100 on which the diffusion barrier layer 103 is formed.

The N 2 plasma treatment 104 is about 40 to 80 minutes at a power of about 90 to 110 W, a flow rate of about 40 to 60 sccm, and a process pressure of about 600 to 640 mTorr at an initial vacuum pressure of about 4 to 6 * 10 -6 Torr. It is preferable to perform by PECVD (Plasma Enhanced Chemical Vapor Deposition) method for a time of.

In this case, the N 2 plasma treatment 104 is performed before the subsequent activation pretreatment, so that the oxides generated on the surface of the diffusion barrier layer 103 can be more easily removed.

Referring to FIG. 1D, the activation pretreatment 106 is performed on the semiconductor substrate 100 on which the N 2 plasma treatment 103 has been performed.

The activation pretreatment 106 is 0.01 to 0.05 g of PdCl 2 , 0.1 to 0.5 ml of HCl, 10 to 100 ml of glacial acetic acid, 10 to 50 ml of ultrapure water (DI Water), and 1 to 10 ml of HF mixture. Preference is given to using the solution.

In this way, when the diffusion barrier film 103 is formed by the activation pretreatment 103, oxides generated on the surface thereof can be easily removed, and the Pd nucleus can be formed by the activation pretreatment 103. This facilitates the nucleation of copper.

Referring to FIG. 1E, a copper layer 108 is formed by performing an electroless plating method to fill the damascene pattern D with respect to the semiconductor substrate 100 on which the activation pretreatment 103 has been performed.

The electroless plating method is 5~15g / l amount of CuSO 4 .5H 2 O, HCHO ( 37%) of 40~80ml degree, the degree 250~350ml / l of the degree of CH 3 OH, 30~50g / l NaOH and using a plating solution KNa 2 H 4 O 8 .4H 2 O mixed electroless of about 25~35g / l preferably carried out at a temperature of about 40~80 ℃ for 15~35 minute.

Referring to FIG. 1F, the copper film 108 and the diffusion barrier film 103 formed by the electroless plating method as described above are removed by chemical mechanical polishing (CMP) until the insulating film 102 is exposed. The metal wiring 110 of the semiconductor device according to the embodiment is completed.

As described above, according to the present invention, after forming the metal wiring of the semiconductor device to which copper is applied, after the diffusion barrier is formed, the diffusion barrier is subjected to activation pretreatment or N 2 plasma treatment and activation pretreatment, followed by electroless plating. By forming the copper film, oxides generated on the surface of the diffusion barrier layer, such as silicide, can be removed by the activation pretreatment, and a Pd nucleus is formed on the surface of the diffusion barrier layer using a subsequent electroless plating method. When the copper film is formed, it is possible to promote nucleation of copper.

Therefore, since nucleation of copper can be promoted due to Pd nucleation as described above, adhesion characteristics of the diffusion barrier film to copper can be improved.

In addition, by performing the N 2 plasma treatment before the activation pretreatment, the oxide may be more effectively removed, thereby further improving the adhesion property of the diffusion barrier to copper.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1A to 1F are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

Claims (8)

Forming an insulating film having a damascene pattern on the semiconductor substrate; Forming a diffusion barrier on the insulating film including the damascene pattern; Pretreating the surface of the diffusion barrier to remove oxides on the surface of the diffusion barrier; Forming a metal film by using an electroless plating method to fill the damascene pattern on the pretreated diffusion barrier film; And Removing the metal layer and the diffusion barrier layer until the insulating layer is exposed; Metal wiring forming method of a semiconductor device comprising a. The method of claim 1, The damascene pattern is a metal wiring forming method of the semiconductor device, characterized in that formed in a single (Single) structure. The method of claim 1, The damascene pattern is a metal wiring forming method of the semiconductor device, characterized in that formed in a dual (Dual) structure. The method of claim 1, The diffusion barrier layer is formed of any one of TiSi, TaSi, CoSi, TiN, Ta, TaN, W, WN, Cr and Nb film forming a metal wiring of the semiconductor device. The method of claim 1, Between forming the diffusion barrier and performing the activation pretreatment process, Performing an N 2 plasma treatment on the semiconductor substrate including the insulating film on which the diffusion barrier is formed; Forming a metal wiring of the semiconductor device further comprising. The method of claim 5, wherein The N 2 plasma treatment is Plasma Enhanced Chemical (PECVD) for 40 to 80 minutes at a power of 90 to 110 W, a flow rate of 40 to 60 sccm, and a process pressure of 600 to 640 mTorr at an initial vacuum pressure of 4 to 6 * 10 -6 Torr. Method for forming a metal wiring of the semiconductor device, characterized in that carried out by a vapor deposition method. The method of claim 1, The pretreatment process may be performed by using 0.01 to 0.05 g of PdCl 2 , 0.1 to 0.5 ml of HCl, 10 to 100 ml of glacial acetic acid, 10 to 50 ml of DI water, and 1 to 10 ml of HF mixed solution. The metal wiring forming method of a semiconductor device, characterized in that performed by. The method of claim 1, The forming of the metal film comprises 5 to 15 g / l CuSO 4.5H 2 O, 40 to 80 ml HCHO (37%), 250 to 350 ml / l CH 3 OH, 30 to 50 g / l NaOH and 25 ~35g / l of KNa 2 H 4 O 8 .4H 2 O mixture electroless plating solution 15-35 minutes metal wiring formation method of a semiconductor device, characterized in that performing at a temperature of 40~80 ℃ using.
KR1020070099174A 2007-10-02 2007-10-02 Method of manufacturing metal wiring for semiconductor device KR20090034035A (en)

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