KR100630566B1 - Method for filling the gap of the dual damascene pattern in semiconductor device - Google Patents
Method for filling the gap of the dual damascene pattern in semiconductor device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000009977 dual effect Effects 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 19
- 229910002056 binary alloy Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 3
- 229910052709 silver Inorganic materials 0.000 claims abstract description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 230000027756 respiratory electron transport chain Effects 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000012790 adhesive layer Substances 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 229910002696 Ag-Au Inorganic materials 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052802 copper Inorganic materials 0.000 abstract description 15
- 239000010949 copper Substances 0.000 abstract description 15
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000036039 immunity Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000005012 migration Effects 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 46
- 239000010410 layer Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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Abstract
본 발명은 반도체 소자 제조 방법 중 듀얼 다마신 패턴 매립 방법에 관한 것으로, 보다 자세하게는 소정의 듀얼 다마신 패턴이 형성된 기판 상에 배리어 금속막을 증착하는 단계; 상기 배리어 금속막 상부에 백금막을 형성하는 단계; 상기 백금막 상부에 이원계 합금막을 형성하는 단계; 및 상기 이원계 합금막을 CMP로 평탄화하는 단계로 이루어짐에 기술적 특징이 있다.The present invention relates to a method for embedding a dual damascene pattern in a method of manufacturing a semiconductor device, and more particularly, depositing a barrier metal film on a substrate on which a predetermined dual damascene pattern is formed; Forming a platinum film on the barrier metal film; Forming a binary alloy film on the platinum film; And a step of planarizing the binary alloy film with CMP.
따라서, 본 발명의 반도체 소자의 듀얼 다마신 패턴 매립 방법은 구리 배선을 직접 이용하지 않기 때문에 구리 확산 문제가 없고 전자이동(Electron Migration)에 대한 면역성이 개선되어 신뢰성 향상은 물론 고성능을 발휘하는 장점이 있다.Therefore, since the dual damascene pattern embedding method of the semiconductor device of the present invention does not use copper wiring directly, there is no problem of copper diffusion and immunity to electron migration is improved, thereby improving reliability and high performance. have.
듀얼 다마신, 이원계 합금막, Ag, Au, RF Sputter, DC Sputter, ECP, 백금, ITODual damascene, binary alloy film, Ag, Au, RF Sputter, DC Sputter, ECP, Platinum, ITO
Description
도 1은 종래의 구리 배선을 사용한 반도체 소자의 듀얼 다마신 패턴 매립 방법을 나타낸 도면.BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the dual damascene pattern embedding method of the semiconductor element using the conventional copper wiring.
도 2는 본 발명에 의한 반도체 소자의 듀얼 다마신 패턴 매립 방법을 나타낸 도면.2 is a view showing a dual damascene pattern embedding method of a semiconductor device according to the present invention.
본 발명은 반도체 소자의 제조 방법 중 듀얼 다마신 패턴 매립 방법에 관한 것으로, 보다 자세하게는 ITO막을 배리어 금속막을 사용하며, 배리어 금속막 상부에 백금막을 형성하고, 백금막 상부에 이원계 합금막을 형성하여 듀얼 다마신 패턴을 매립하는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 매립 방법에 관한 것이다. The present invention relates to a dual damascene pattern embedding method of a semiconductor device manufacturing method, and more specifically, a barrier metal film is used as the ITO film, a platinum film is formed on the barrier metal film, and a dual alloy film is formed on the platinum film. It relates to a dual damascene pattern embedding method of a semiconductor device, characterized in that the damascene pattern is embedded.
일반적으로, 반도체 산업이 초대규모 직접회로(VLSI: Very Large-Scale Intergration), 극초대규모 집적회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 집적도, 미세화, 동작속도 등을 향상시키는 방향으로 기술이 발전하고 있다. 소자의 디자인 룰(Design Rule)이 협소화되면서 RC 지연시간(Resistance-Capacitance Delay Time) 문제를 해결하기 위한 일환으로 기존의 알루미늄 배선을 구리 배선으로 변경하고 있다. In general, the semiconductor industry is moving toward Very Large-Scale Intergration (VLSI) and Ultra Large Scale Integration (ULSI) to improve the integration, miniaturization and operation speed of devices. This is evolving. As the design rule of the device is narrowed, the existing aluminum wiring is changed to copper wiring as a solution to the problem of resistance-capacitance delay time.
하지만, 구리는 확산 속도가 빨라 트랜지스터의 부식 요인이 될 수 있으며, 배리어 금속막과 시드층 미세화 및 구리 기계화학적 연마(Chemical Mechanical Polishing, 이하 CMP)에도 많은 문제점들이 드러나고 있어, 최근 특히 전자 부품용으로 사용되는 박막으로서, 저전기 저항 또는 타고광학 반사율이라는 유익한 특징을 가지는 Ag 막 과 그 합금막이 주목을 받고 있다. However, copper has a high diffusion rate, which may cause corrosion of transistors, and many problems are exposed to barrier metal film, seed layer refinement, and copper mechanical mechanical polishing (CMP). As the thin film to be used, an Ag film and an alloy film thereof having an advantageous characteristic of low electrical resistance or riding optical reflectance have attracted attention.
일반적으로 듀얼 다마신 공정은 식각 정지막과 층간 절연막을 다층으로 적층하고 이들을 식각하여 비아홀(Via Hole)과 트렌치(Trench)를 형성한 후 확산 방지막 및 시드층을 비아홀 및 트렌치를 포함한 전체 구조 상부에 형성하고 전기 도금법으로 금속을 증착한 후 CMP 공정을 통해 금속을 평탄화하여 금속 배선을 한번에 형성하는 공정이다.In general, the dual damascene process stacks an etch stop layer and an interlayer insulating layer in multiple layers and etches them to form via holes and trenches, and then spreads the diffusion barrier and seed layer on top of the entire structure including the via holes and trenches. After forming and depositing the metal by the electroplating method, the metal wiring is formed at the same time by planarizing the metal through the CMP process.
도 1은 종래의 구리 배선을 사용한 반도체 소자의 듀얼 다마신 패턴 매립 방법을 나타낸 도면이다. 도 1에서 보는 바와 같이 소정의 듀얼 다마신 패턴이 형성된 기판(101) 상에 배리어 금속막(102)으로 Ta/TaN(102)와 구리 시드층(103)을 연속으로 증착한다. 이 후 ECP(Electro Chemical Plating)법으로 구리를 증착(104)하고 CMP로 평탄화하여 구리 배선을 완성한다. 1 is a view showing a dual damascene pattern embedding method of a semiconductor device using a conventional copper wiring. As shown in FIG. 1, Ta /
그러나, 상기와 같은 종래의 방법은 상기 TaN막이 하부의 IMD(Intermetal Dielectric)막과 접촉하여 접착성(Adhesion) 문제를 일으켜, 상기 반도체 소자를 장기간 사용할 때, 신뢰성 문제를 야기시키고, 구리 확산(Diffusion) 문제가 항상 있어 왔다.However, the conventional method as described above causes the adhesion problem due to the TaN film contacting the underlying intermetal dielectric (IMD) film, causing reliability problems when using the semiconductor device for a long time, and diffusing copper. There has always been a problem.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 구리 배선과 배리어 금속막으로 사용되는 Ta/TaN막을 이용하지 않고, ITO막을 배리어 금속막을 사용하며, 배리어 금속막 상부에 백금막을 형성하고, 백금막 상부에 이원계 합금막을 사용하므로써 구리 확산 문제와 배리어 금속막과의 접착성Adhesion)에 문제가 없고, 전자이동(Electron Migration)에 대한 면역성이 개선되어 신뢰성 향상은 물론 고성능을 발휘하는 반도체 소자의 듀얼 다마신 패턴 매립 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, without using a Ta / TaN film used as a copper wiring and a barrier metal film, ITO film using a barrier metal film, a platinum film on the barrier metal film By using a binary alloy film on top of the platinum film, there is no problem of copper diffusion problems and adhesion to the barrier metal film, and immunity to electromigration is improved to improve reliability and high performance. An object of the present invention is to provide a method for embedding a dual damascene pattern of a semiconductor device.
본 발명의 상기 목적은 소정의 듀얼 다마신 패턴이 형성된 기판 상에 배리어 금속막을 증착하는 단계; 상기 배리어 금속막 상부에 백금막을 형성하는 단계; 상기 백금막 상부에 이원계 합금막을 형성하는 단계; 및 상기 이원계 합금막을 CMP로 평탄화하는 단계로 이루어진 반도체 소자의 듀얼 다마신 패턴 매립 방법에 의해 달성된다.The above object of the present invention comprises the steps of depositing a barrier metal film on a substrate having a predetermined dual damascene pattern; Forming a platinum film on the barrier metal film; Forming a binary alloy film on the platinum film; And flattening the binary alloy film with CMP.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
도 2는 본 발명에 의한 반도체 소자의 듀얼 다마신 패턴 매립 방법을 나타낸 도면이다. 도 2에서 보는 바와 같이, 반도체 소자의 듀얼 다마신 패턴 매립 방법에 있어서, 소정의 듀얼 다마신 패턴이 형성된 기판(201) 상에 배리어 금속막(202)을 증착하고, 상기 배리어 금속막 상부에 백금막(203)을 형성한다. 이 때, 배리어 금속막은 ITO(Indium Tin Oxide)막을 RF Sputter법으로 형성하며, Indium막과 Tin막을 N2O 플라즈마 혹은 O2 플라즈마 상태에서 차례로 증착하는 것이 바람직하다. 또한, 상기 백금막은 상부에 형성될 이원계 합금막(204)과 상기 배리어 금속막 사이에 접착층(Adhesive Layer) 역할을 하며, 동시에 가혹 조건에서 발생하는 이원계 금속막의 전자이동 특성을 방지하는 역할도 수행한다. 2 is a view showing a dual damascene pattern embedding method of a semiconductor device according to the present invention. As shown in FIG. 2, in the dual damascene pattern embedding method of a semiconductor device, a
이어서, 상기 백금막 상부에 상기 이원계 합금막을 형성하고, 상기 이원계 합금막을 CMP로 평탄화하여 듀얼 다마신 패턴 매립을 완료한다. 상기 백금막은 DC Sputter법을 사용하며, 상기 이원계 합금막은 고용체(Solid Solution) 형성이 용이한 Ag와 Au로 구성하는 것이 바람직하며, ECP법을 사용한다. 이 때, Ag의 무게비는 전체 이원계 합금막의 50% 이하로 하며, 상기 배리어 금속막과 백금막의 두께를 각각 10Å내지 500Å 사이로 형성하는 것이 바람직하다. Subsequently, the binary alloy film is formed on the platinum film, and the dual alloy film is flattened with CMP to complete the dual damascene pattern filling. The platinum film is a DC Sputter method, the binary alloy film is preferably composed of Ag and Au, which is easy to form a solid solution, ECP method is used. At this time, the weight ratio of Ag is 50% or less of the total binary alloy film, and the thickness of the barrier metal film and the platinum film is preferably formed between 10 kPa and 500 kPa, respectively.
본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설 명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.The present invention has been shown and described with reference to the preferred embodiments as described above, but is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.
따라서, 본 발명의 반도체 소자의 듀얼 다마신 매립 방법은 구리 배선을 직접 이용하지 않기 때문에 구리 확산 문제가 없고 전자이동에 대한 면역성이 개선되어 신뢰성 향상은 물론 고성능을 발휘하는 장점이 있다.Therefore, since the dual damascene embedding method of the semiconductor device of the present invention does not use copper wiring directly, there is no problem of copper diffusion and immunity to electron transfer is improved, thereby improving reliability and exhibiting high performance.
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