KR100598295B1 - Method for forming the copper interconnection of semiconductor device - Google Patents

Method for forming the copper interconnection of semiconductor device Download PDF

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KR100598295B1
KR100598295B1 KR1020040106644A KR20040106644A KR100598295B1 KR 100598295 B1 KR100598295 B1 KR 100598295B1 KR 1020040106644 A KR1020040106644 A KR 1020040106644A KR 20040106644 A KR20040106644 A KR 20040106644A KR 100598295 B1 KR100598295 B1 KR 100598295B1
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film
copper wiring
semiconductor device
copper
forming
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KR20060067746A (en
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전인규
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 보다 자세하게는 듀얼 다마신 기법에 의해 형성되는 패턴 부위를 미리 USG막으로 채우고, 내부에 듀얼 다마신 패턴이 형성된 비아 및 트렌치 측벽에 있는 FSG막의 노출을 막음으로써, 불소와 공기 중의 수분과의 반응으로 인하여 후속 공정 진행시 발생되는 비아 결손을 예방하고, SM(Stress Migration) 및 EM(Electro Migration)과 같은 특성에 대한 면역성의 증가 및 추후 열처리 공정에서 형성되는 불필요한 절연막의 배제로 소자의 신뢰도를 향상시키는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, to a pattern region formed by a dual damascene technique, previously filled with a USG film, and having a dual damascene pattern formed therein. By preventing exposure, it prevents via defects generated during the subsequent process due to the reaction of fluorine with moisture in the air, increases immunity to properties such as stress migration (SM) and electro migration (EM), and further heat treatment process. The present invention relates to a method for forming a copper wiring of a semiconductor device to improve the reliability of the device by eliminating the unnecessary insulating film formed in.

구리 배선, 듀얼 다마신(Dual Damascene), FSG막, USG막, 비아 결손Copper Wiring, Dual Damascene, FSG Film, USG Film, Via Defects

Description

반도체 소자의 구리 배선 형성 방법{Method for forming the copper interconnection of semiconductor device} Method for forming the copper interconnection of semiconductor device             

도 1a 및 도 1b는 종래기술에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 단면도이다.1A and 1B are cross-sectional views showing a copper wiring formation method of a semiconductor device according to the prior art.

도 2a 내지 도2c는 본 발명에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 단면도이다. 2A to 2C are cross-sectional views showing a copper wiring formation method of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 보다 자세하게는 듀얼 다마신 기법에 의해 형성되는 패턴 부위를 미리 USG(Undoped Silica Glass)막으로 채우고, 내부에 듀얼 다마신(Dual Damascene) 패턴이 형성된 비아 및 트렌치 측벽에 있는 FSG(Fluorinated Silica Glass)막의 노출을 막음으로써, 불소와 공기 중의 수분과의 반응으로 인하여 후속 공정 진행시 발생되는 비아 결손(Via Defect)을 예방하고, SM(Stress Migration) 및 EM(Electro Migration)과 같은 특성 에 대한 면역성의 증가 및 추후 열처리 공정에서 형성되는 불필요한 절연막의 배제로 반도체 소자의 신뢰도를 향상시키는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. More particularly, a pattern portion formed by a dual damascene technique is pre-filled with an undoped silica glass (USG) film, and a dual damascene pattern is formed therein. By preventing exposure of the Fluorinated Silica Glass (FSG) film on the formed via and trench sidewalls, it prevents via defects generated during the subsequent process due to the reaction between fluorine and moisture in the air, and stress migration (SM) And a method for forming a copper wiring of a semiconductor device, which improves reliability of the semiconductor device by increasing immunity to characteristics such as EM (Electro Migration) and eliminating unnecessary insulating films formed in a later heat treatment process.

일반적으로, 반도체 산업이 초대규모 직접회로(VLSI: Very Large-Scale Intergration), 극초대규모 집적회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 집적도, 미세화, 동작속도 등을 향상시키는 방향으로 기술이 발전하고 있다. 소자의 디자인 룰(Design Rule)이 집적화되면서 RC 지연시간(Resistance-Capacitance Delay Time) 문제를 해결하기 위한 일환으로 기존의 알루미늄 배선을 구리 배선으로 변경하고 있다. In general, the semiconductor industry is moving toward Very Large-Scale Intergration (VLSI) and Ultra Large Scale Integration (ULSI) to improve the integration, miniaturization and operation speed of devices. This is evolving. As the design rules of the devices are integrated, the existing aluminum wiring is being replaced with copper wiring as a solution to the problem of resistance-capacitance delay time.

구리는 알루미늄에 비해 여러가지 잇점이 있다. 첫째, 전기전도도가 알루미늄에 비해 우수하여 반송전류를 일정하게 유지하면서 배선의 미세화와 고집적화의 실현이 가능하다. 따라서 사용하는 금속층의 양이 감소하고, 생산 코스트를 절감할 수 있게 된다. 낮은 저항 역시 반도체 소자의 고속성능을 구현한다. 둘째, 구리는 전해도금특성(내전해도금성)이 우수하여 디바이스의 신뢰도를 높일 수 있다. 셋째, 무엇보다도 구리는 동일하게 설계한 알루미늄 기반 디바이스에 비해 수율이 높다.Copper has several advantages over aluminum. First, the electrical conductivity is superior to that of aluminum, and it is possible to realize miniaturization and high integration of the wiring while keeping the carrier current constant. Therefore, the amount of the metal layer to be used is reduced, and the production cost can be reduced. Low resistance also enables high speed performance of semiconductor devices. Second, copper is excellent in electroplating characteristics (electrolytic plating resistance), thereby increasing the reliability of the device. Thirdly, copper has a higher yield than aluminum-based devices of the same design.

현재 사용이 가능한 구리 매립 방법 가운데 구리 매립 특성이 비교적 양호한 화학기상증착법(CVD)과 전해도금(Electroplating)법이 선호되고 있다. Among the currently available copper embedding methods, chemical vapor deposition (CVD) and electroplating methods which have good copper embedding characteristics are preferred.

구리의 경우 건식 식각이 어렵기 때문에 절연막으로 패턴을 형성한 다음, 비아 홀과 트렌치를 식각하는데 이 때 생긴 자리를 구리로 증착하는 듀얼 다마신 기법을 이용한다. 최근에는 절연막으로 FSG막을 사용하는 경우가 많다. In the case of copper, dry etching is difficult, so a pattern is formed using an insulating layer, and then via holes and trenches are etched. In recent years, an FSG film is often used as an insulating film.

도 1a 및 도 1b는 종래 기술에 의한 반도체 소자의 구리 배선 형성방법을 나타낸 단면도이다. 1A and 1B are cross-sectional views showing a copper wiring formation method of a semiconductor device according to the prior art.

먼저 도 1a에 도시된 바와 같이, 구리 배선이 형성된 기판 상에 질화막(Nitride Film, 예; SiN Film)(101)과 FSG막(102)을 쌓고, 후속으로 기존의 여러 가지 방법들로 듀얼 다마신 패턴을 형성한다. 이 때 절연막으로 사용되어진 FSG막(102)의 트렌치(Trench) 및 비아 홀(Via Hole)의 측벽은 공기 중에 노출된다. 다음으로 하부 구리 배선과의 연결을 위해 하부 배선의 캡핑(capping)막인 질화막(101)의 브레이크(Break) 공정이 따르고, 여기에 구리 배리어(barrier)막 형성 공정인 Ta/TaN막(103), 구리 시드층(seed layer)층 증착 및 구리 ECP(Electro Chemical Plating)공정을 수반하게 된다. First, as shown in FIG. 1A, a nitride film (eg, SiN film) 101 and an FSG film 102 are stacked on a substrate on which copper wiring is formed, followed by dual damascene using various conventional methods. Form a pattern. At this time, the sidewalls of the trench and the via hole of the FSG film 102 used as the insulating film are exposed to air. Next, a break process of the nitride film 101, which is a capping film of the lower wire, is followed to connect the lower copper wire, and a Ta / TaN film 103, which is a copper barrier film forming process, Copper seed layer deposition and copper ECP (Electro Chemical Plating) processes are involved.

다음 도1b에 도시된 바와 같이, FSG막(102) 상부와 하부에 별도의 USG 캡핑층(104)을 쌓는 구조에서도 마찬가지로 트렌치 및 비아 홀의 측벽에서는 FSG막이 공기 중에 노출되게 된다.Next, as shown in FIG. 1B, the FSG film is exposed to the air at the sidewalls of the trench and the via hole in a structure in which separate USG capping layers 104 are stacked on the upper and lower portions of the FSG film 102.

따라서, FSG막이 공기 중에 노출됨으로써 불소의 농도가 높아질수록 구리 배리어막인 Ta/TaN막과의 응착(Adhesion)이 나빠져 필링(Peeling) 현상을 유발시킬 수 있으며, 이는 SM 및 EM 특성에 대한 면역성을 저하시켜 반도체 소자의 신뢰도 문제를 야기시킬 수 있으며, 무엇보다도 FSG막의 불소 성분이 공기 중의 수분과 반응하여 하부 구리배선 표면에 SiOF 박막을 형성시켜, 결과적으로 후속 공정인 배리어 Ta/TaN막의 증착을 중도 차단시켜 비아 결손(Via Fail)이라는 반도체 소자에서 치명적인 문제점을 야기시킨다.Therefore, as the FSG film is exposed to air and the concentration of fluorine increases, adhesion to the Ta / TaN film, which is a copper barrier film, may worsen, causing peeling, which may cause immunity to SM and EM properties. This may cause a reliability problem of the semiconductor device, and above all, the fluorine component of the FSG film reacts with moisture in the air to form a SiOF thin film on the lower copper wiring surface. Blocking causes a fatal problem in a semiconductor device called via fail.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 듀얼 다마신 패턴 부위를 미리 USG막으로 채워 내부에 듀얼 다마신 패턴을 형성시켜 FSG막의 노출을 막음으로써 불소와 공기 중의 수분과의 반응으로 인한 비아 결손을 예방하고, SM 및 EM과 같은 특성에 대한 면역성의 증가 및 추후 열처리 공정에서 형성되는 불필요한 절연막의 배제로 반도체 소자의 신뢰도를 향상시키는 반도체 소자의 구리 배선 형성 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by filling the dual damascene pattern portion with the USG film in advance to form a dual damascene pattern therein to prevent the exposure of the FSG film and moisture in the fluorine and air It provides a method of forming a copper wiring of a semiconductor device to prevent via defects due to the reaction of the semiconductor device, to improve the reliability of the semiconductor device by increasing the immunity to properties such as SM and EM and eliminating unnecessary insulating films formed in a later heat treatment process. There is an object of the present invention.

본 발명의 상기 목적은 구리 배선이 형성된 반도체 기판 상에 질화막과 절연막을 형성하는 단계, 상기 기판 상에 감광막을 도포하고 패터닝하여 상기 질화막과 절연막을 식각하는 단계, 상기 식각된 절연막에 USG막을 증착시키는 단계, 상기 USG막이 증착된 기판을 물리화학적 연마(Chemical Physical Polishing, 이하 CMP)로 연마하는 단계, 상기 연마된 기판에 듀얼 다마신 패턴을 형성하는 단계, 상기 기판에 배리어 금속막을 형성하는 단계, 상기 배리어 금속막이 형성된 기판에 구리를 증착하는 단계로 이루어진 반도체 소자의 구리 배선 형성 방법에 의해 달성된다.The object of the present invention is to form a nitride film and an insulating film on a semiconductor substrate on which copper wiring is formed, by coating and patterning a photosensitive film on the substrate to etch the nitride film and the insulating film, depositing a USG film on the etched insulating film Polishing the substrate on which the USG film is deposited by chemical physical polishing (CMP); forming a dual damascene pattern on the polished substrate; forming a barrier metal film on the substrate; A copper wiring formation method of a semiconductor device comprising the step of depositing copper on a substrate on which a barrier metal film is formed.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설 명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 단면도이다. 2A to 2C are cross-sectional views showing a copper wiring formation method of a semiconductor device according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 구리 배선이 형성된 반도체 기판 상에 질화막(201)과 절연막(202)을 형성하고, 기판상에 감광막을 도포하고 패터닝하여 상기 질화막(201)과 절연막(202)을 식각한 다음, 형성된 패턴에 USG막(204)을 증착시키고, 상기 USG막을 CMP로 연마한다. 이 때, 상기 질화막(201)과 절연막(202)은 SiN막과 FSG막으로 하는 것이 바람직하며, 패터닝 시에 비아 홀 및 트렌치 영역에 목표하는 트렌치 크기보다 양쪽으로 더 넓게 패턴을 형성시켜 USG막(204)을 증착시킨후 CMP 공정을 통해 연마하는 것이 바람직하다. First, as shown in FIG. 2A, a nitride film 201 and an insulating film 202 are formed on a semiconductor substrate on which copper wiring is formed, and a photosensitive film is coated and patterned on the substrate to form the nitride film 201 and the insulating film 202. After etching, the USG film 204 is deposited on the formed pattern, and the USG film is polished with CMP. In this case, the nitride film 201 and the insulating film 202 may be a SiN film and an FSG film. The pattern of the nitride film 201 and the insulating film 202 may be wider on both sides of the via hole and the trench region than the target trench size during patterning. 204) is preferably polished through a CMP process after deposition.

다음, 도 2b 및 도 2c에 도시된 바와 같이, USG막(204)에 듀얼 다마신 패턴을 형성시킨 다음, 상기 듀얼 다마신 패턴에 배리어 금속막(203)을 형성시키고, 구리를 증착시킨다. 이 때 상기 구리 증착은 구리 시드층을 증착한 후, ECP 법으로 구리를 증착시키는 것이 바람직 하며, 배리어 금속막(203)은, Ti, TiN, W, TiW 등을 사용할 수 있으나 Ta/TaN이 바람직하다.Next, as shown in FIGS. 2B and 2C, a dual damascene pattern is formed on the USG film 204, a barrier metal film 203 is formed on the dual damascene pattern, and copper is deposited. In this case, the copper deposition may be performed by depositing a copper seed layer and then depositing copper by an ECP method. The barrier metal layer 203 may use Ti, TiN, W, TiW, etc., but Ta / TaN is preferable. Do.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 반도체 소자의 구리 배선 형성 방법은 듀얼 다마신 패턴 부위를 미리 USG막으로 채워 내부에 듀얼 다마신 패턴을 형성시켜 FSG막의 노출을 막음으로써, 불소와 공기 중의 수분과의 반응으로 인한 비아 결손을 예방할 수 있다. Therefore, in the method of forming a copper wiring of the semiconductor device of the present invention, the dual damascene pattern portion is previously filled with a USG film to form a dual damascene pattern therein, thereby preventing the exposure of the FSG film, resulting from the reaction between fluorine and water in the air. Via deficiency can be prevented.

또한, 기존의 측벽 FSG막과 배리어막의 응착(Adhesion) 문제를 제거하여 불소 농도를 더 높여 SM 및 EM과 같은 특성에 대한 면역성의 증가 및 추후 열처리 공정에서 형성되는 불필요한 절연막의 배제로 소자의 신뢰도를 향상시키는 효과가 있다. In addition, by eliminating the problem of adhesion between the sidewall FSG film and the barrier film, the fluorine concentration is increased to increase the immunity to properties such as SM and EM and to eliminate the need for unnecessary insulating films formed in the subsequent heat treatment process. It is effective to improve.

Claims (5)

반도체 소자의 구리 배선 형성 방법에 있어서,In the copper wiring formation method of a semiconductor element, 구리 배선이 형성된 반도체 기판 상에 질화막과 FSG막을 형성하는 단계;Forming a nitride film and an FSG film on the semiconductor substrate on which the copper wiring is formed; 상기 기판 상에 감광막을 도포하고 패터닝하여 식각 마스크로 상기 질화막과 FSG막을 식각하는 단계;Coating and patterning a photoresist on the substrate to etch the nitride film and the FSG film with an etch mask; 상기 식각된 FSG막에 USG막을 증착시키는 단계;Depositing a USG film on the etched FSG film; 상기 USG막을 증착된 기판을 CMP로 연마하는 단계;Polishing the USG film on the deposited substrate by CMP; 상기 연마된 기판에 듀얼 다마신 패턴을 형성하는 단계;Forming a dual damascene pattern on the polished substrate; 상기 기판에 배리어 금속막을 형성하는 단계; 및 Forming a barrier metal film on the substrate; And 상기 배리어 금속막이 형성된 기판에 구리를 증착하는 단계Depositing copper on a substrate on which the barrier metal film is formed 로 이루어짐을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.Copper wiring forming method of a semiconductor device, characterized in that consisting of. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 SiN막을 사용하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The said nitride film uses a SiN film, The copper wiring formation method of the semiconductor element characterized by the above-mentioned. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 배리어 금속막은 Ta/TaN막을 사용하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The barrier metal film is a copper wiring forming method of a semiconductor device, characterized in that using a Ta / TaN film. 제 1 항에 있어서, The method of claim 1, 상기 구리를 증착하는 방법은 구리 시드층을 증착시킨 후 ECP(Electronic Chemical Plating)법으로 증착하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of depositing copper is a copper wiring forming method of a semiconductor device, characterized in that by depositing a copper seed layer by ECP (Electronic Chemical Plating) method.
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