KR100841051B1 - Semiconductor device prevented chemical attack and method for fabricating the same - Google Patents

Semiconductor device prevented chemical attack and method for fabricating the same Download PDF

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KR100841051B1
KR100841051B1 KR1020060121416A KR20060121416A KR100841051B1 KR 100841051 B1 KR100841051 B1 KR 100841051B1 KR 1020060121416 A KR1020060121416 A KR 1020060121416A KR 20060121416 A KR20060121416 A KR 20060121416A KR 100841051 B1 KR100841051 B1 KR 100841051B1
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film
contact hole
contact
plug
semiconductor device
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KR1020060121416A
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Korean (ko)
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KR20070101101A (en
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서대영
김도형
홍기로
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Abstract

본 발명은 이웃하는 랜딩 플러그와 스토리지노드콘택플러그 간의 브릿지를 방지하는데 적합한 반도체 소자의 제조 방법을 제공하기 위한 것으로, 이를 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상에 제1콘택홀을 갖는 제1절연막을 형성하는 단계; 상기 제1콘택홀의 양측벽에 어택방지막을 형성하는 단계; 상기 제1콘택홀에 도전 물질을 매립하여 제1콘택플러그를 형성하는 단계; 상기 제1콘택플러그가 형성된 상기 제1절연막 상부에 제2절연막을 형성하는 단계; 상기 제2절연막의 소정 영역을 식각하여 상기 제1콘택플러그를 오픈시키는 제2콘택홀을 형성하는 단계, 및 상기 제2콘택홀에 상기 제1콘택플러그와 연결되는 제2콘택플러그를 매립하는 단계를 포함하며, 이에 따라 본 발명은, 이웃한 랜딩플러그와 스토리지노드콘택플러그간의 브릿지 현상을 방지하여 수율 향상을 기대할 수 있는 효과가 있다.The present invention provides a method for manufacturing a semiconductor device suitable for preventing a bridge between a neighboring landing plug and a storage node contact plug, the method of manufacturing a semiconductor device of the present invention has a first contact hole on a semiconductor substrate Forming a first insulating film; Forming an anti-attack film on both sidewalls of the first contact hole; Forming a first contact plug by filling a conductive material in the first contact hole; Forming a second insulating layer on the first insulating layer on which the first contact plug is formed; Etching a predetermined region of the second insulating layer to form a second contact hole for opening the first contact plug, and filling a second contact plug connected to the first contact plug in the second contact hole In this regard, the present invention has the effect of improving the yield by preventing the bridge phenomenon between the neighboring landing plug and the storage node contact plug.

스토리지노드콘택홀, 습식 케미컬, 브릿지, 어택방지막, 랜딩플러그 Storage Node Contact Hole, Wet Chemical, Bridge, Attack Barrier, Landing Plug

Description

케미컬어택을 방지한 반도체 소자 및 그의 제조 방법{SEMICONDUCTOR DEVICE PREVENTED CHEMICAL ATTACK AND METHOD FOR FABRICATING THE SAME}Semiconductor device preventing chemical attack and manufacturing method thereof {SEMICONDUCTOR DEVICE PREVENTED CHEMICAL ATTACK AND METHOD FOR FABRICATING THE SAME}

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자 제조 방법을 나타낸 단면도.1A and 1B are cross-sectional views showing a semiconductor device manufacturing method according to the prior art.

도 2는 본 발명의 실시예에 따른 반도체소자의 구조를 도시한 도면.2 is a view showing the structure of a semiconductor device according to an embodiment of the present invention.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 제1층간절연막21 semiconductor substrate 22 first interlayer insulating film

23 : 콘택홀 24 : 어택방지막23: contact hole 24: attack prevention film

25A, 25B : 랜딩플러그 26 : 제2층간절연막25A, 25B: Landing plug 26: Second interlayer insulating film

27 : 비트라인콘택 28 : 비트라인27: bit line contact 28: bit line

29 : 제3층간절연막 30 : 스토리지노드콘택홀29: third interlayer insulating film 30: storage node contact hole

31 : 스토리지노드콘택플러그31: Storage node contact plug

본 발명은 반도체 제조 기술에 관한 것으로, 특히 이웃하는 랜딩플러그와 스토리지노드콘택플러그간 브릿지를 방지한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device which prevents bridges between neighboring landing plugs and storage node contact plugs.

DRAM 소자 제조시에 집적도 증가에 따라 랜딩플러그(Landing plug)를 비트라인콘택 및 스토리지노드콘택플러그 아래에 형성해주어, 고밀도 및 고집적의 DRAM 소자를 제조할 수 있다.As DRAM chips are manufactured, a landing plug may be formed under the bit line contact and the storage node contact plug according to the increase in the density, thereby manufacturing a high density and high density DRAM device.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자 제조 방법을 나타낸 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 게이트 라인(도시하지 않음)을 형성한다. 그리고 나서, 게이트 라인을 포함하는 반도체 기판(11)의 전면에 제1층간절연막(12)을 증착하고, 랜딩 플러그가 형성될 예정 영역의 제1층간절연막(12)을 제거하여, 랜딩플러그콘택홀을 형성한다. 다음으로, 랜딩플러그콘택홀에 폴리실리콘막을 매립하여 랜딩플러그(13)를 형성한다. As shown in FIG. 1A, a gate line (not shown) is formed on the semiconductor substrate 11. Then, the first interlayer insulating film 12 is deposited on the entire surface of the semiconductor substrate 11 including the gate line, and the first interlayer insulating film 12 in the region where the landing plug is to be formed is removed to make the landing plug contact hole. To form. Next, the landing plug 13 is formed by embedding the polysilicon film in the landing plug contact hole.

이어서, 랜딩 플러그(13) 및 제1층간절연막(12) 상에 제2층간절연막(14)을 증착하고, 제2층간절연막(14)을 선택적으로 식각하여 어느 하나의 랜딩 플러그(13) 상부를 오픈한 후, 비트라인콘택(15)을 형성한다. 이어서, 비트라인콘택(15) 상에 비트라인(16)을 형성하고, 비트라인(17)을 포함한 제2층간절연막(14) 상에 제3층간절연막(17)을 증착한다.Subsequently, a second interlayer insulating film 14 is deposited on the landing plug 13 and the first interlayer insulating film 12, and the second interlayer insulating film 14 is selectively etched to remove an upper portion of the landing plug 13. After opening, the bit line contact 15 is formed. Next, the bit line 16 is formed on the bit line contact 15, and the third interlayer insulating film 17 is deposited on the second interlayer insulating film 14 including the bit line 17.

계속해서, 제3층간절연막(17)과 제2층간절연막(14)을 선택적으로 식각하여 나머지 랜딩 플러그(13) 상부를 오픈하는 스토리지노드콘택홀(18)을 형성한다. 이후, 식각부산물 제거를 위한 습식세정을 진행한다.Subsequently, the third interlayer insulating layer 17 and the second interlayer insulating layer 14 are selectively etched to form a storage node contact hole 18 for opening the remaining landing plugs 13. Thereafter, wet cleaning is performed to remove the etch byproducts.

도 1b에 도시된 바와 같이, 스토리지노드콘택홀(18)에 폴리실리콘막을 매립하여 스토리지노드콘택플러그(19)를 형성한다. As shown in FIG. 1B, a polysilicon layer is embedded in the storage node contact hole 18 to form the storage node contact plug 19.

상술한 바와 같이 종래의 반도체소자에서는 이웃하는 랜딩플러그(Landing Plug, 13)를 분리하기 위한 랜딩플러그분리막인 제1층간절연막(12)을 실리콘산화막(SiO2)으로 형성한다.As described above, in the semiconductor device of the related art, the first interlayer insulating layer 12, which is a landing plug separation layer for separating neighboring landing plugs 13, is formed of a silicon oxide film SiO 2 .

그러나, 반도체소자가 점점 미세해짐에 따라 레이아웃 상에서 비트라인(16)이 랜딩플러그(13)를 충분히 감싸지 못하는 문제가 발생하게 되고, 이러한 경우 후속 스토리지노드콘택홀(18) 형성 공정에서 정렬 불량 등의 이유로 제1층간절연막(12)을 식각하는 경우가 발생한다.However, as semiconductor devices become more and more fine, a problem arises in that the bit line 16 does not sufficiently cover the landing plug 13 on the layout. In this case, a misalignment may occur in a subsequent process of forming the storage node contact hole 18. For this reason, the first interlayer insulating film 12 is etched.

이와 같이, 정렬 불량에 의해 제1층간절연막(12)이 식각되는 경우에는, 후속 식각부산물 제거를 위한 습식세정 과정에서 습식 케미컬(Wet Chemical)에 의해 제1층간절연막(12)이 용해되는 문제가 발생한다. 이는 이웃하는 랜딩플러그(13)간의 절연물질이 식각되는 것이므로, 도 1b의 'B'와 같이 서로 연결되지 않아야 할 랜딩플러그(13)와 스토리지노드콘택플러그(19)간의 원하지 않는 브릿지(Bridge) 현상을 초래한다.As such, when the first interlayer dielectric layer 12 is etched due to misalignment, the first interlayer dielectric layer 12 may be dissolved by wet chemical during a wet cleaning process to remove subsequent etching byproducts. Occurs. Since the insulating material between neighboring landing plugs 13 is etched, an unwanted bridge phenomenon between the landing plugs 13 and the storage node contact plugs 19, which should not be connected to each other as shown in FIG. Brings about.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 케미컬어택으로 인한 이웃하는 랜딩 플러그와 스토리지노드콘택플러그 간의 브릿지를 방지하는데 적합한 반도체 소자 및 그의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a manufacturing method thereof suitable for preventing bridges between neighboring landing plugs and storage node contact plugs due to chemical attack.

상기 목적을 달성하기 위한 본 발명의 반도체소자는 반도체기판; 상기 반도체기판 상에 형성되며 복수의 콘택홀이 구비된 절연막; 상기 콘택홀의 측벽에 형성된 어택방지막; 상기 콘택홀의 내부에 매립된 복수의 랜딩플러그; 및 상기 복수의 랜딩플러그 중 적어도 어느 하나의 랜딩플러그 위에 형성된 스토리지노드콘택플러그를 포함하는 것을 특징으로 하고, 상기 어택방지막은 실리콘질화막이고, 상기 절연막은 실리콘산화막인 것을 특징으로 한다.The semiconductor device of the present invention for achieving the above object is a semiconductor substrate; An insulating film formed on the semiconductor substrate and having a plurality of contact holes; An attack prevention film formed on sidewalls of the contact hole; A plurality of landing plugs embedded in the contact hole; And a storage node contact plug formed on at least one of the landing plugs, wherein the attack prevention film is a silicon nitride film, and the insulating film is a silicon oxide film.

또한, 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상에 제1콘택홀을 갖는 제1절연막을 형성하는 단계; 상기 제1콘택홀의 양측벽에 어택방지막을 형성하는 단계; 상기 제1콘택홀에 도전 물질을 매립하여 제1콘택플러그를 형성하는 단계; 상기 제1콘택플러그가 형성된 상기 제1절연막 상부에 제2절연막을 형성하는 단계; 상기 제2절연막의 소정 영역을 식각하여 상기 제1콘택플러그를 오픈시키는 제2콘택홀을 형성하는 단계, 및 상기 제2콘택홀에 상기 제1콘택플러그와 연결되는 제2콘택플러그를 매립하는 단계를 포함하는 것을 특징으로 하며, 상기 제1,2절연막과 상기 어택방지막은 식각률이 서로 다른 절연막인 것을 특징으로 하며, 상기 제1 및 제2절연막은 산화막이고, 상기 어택방지막은 질화막인 것을 특징으로 한다.In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of forming a first insulating film having a first contact hole on a semiconductor substrate; Forming an anti-attack film on both sidewalls of the first contact hole; Forming a first contact plug by filling a conductive material in the first contact hole; Forming a second insulating layer on the first insulating layer on which the first contact plug is formed; Etching a predetermined region of the second insulating layer to form a second contact hole for opening the first contact plug, and filling a second contact plug connected to the first contact plug in the second contact hole Wherein the first and second insulating layers and the attack prevention layer are insulating layers having different etching rates, wherein the first and second insulating layers are oxide layers, and the attack prevention layer is a nitride layer. do.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2는 본 발명의 실시예에 따른 반도체소자의 구조를 도시한 도면이다.2 is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention.

도 2를 참조하면, 반도체기판(21) 상에 복수의 콘택홀(23)이 구비된 제1층간절연막(22)이 형성되고, 콘택홀(23)의 양측벽에는 어택방지막(24)이 형성된다. 여기서, 어택방지막(24)은 질화막이고, 바람직하게는 실리콘질화막이다. Referring to FIG. 2, a first interlayer insulating film 22 having a plurality of contact holes 23 is formed on a semiconductor substrate 21, and an attack prevention film 24 is formed on both side walls of the contact hole 23. do. Here, the attack prevention film 24 is a nitride film, preferably a silicon nitride film.

그리고, 어택방지막(24)이 형성된 콘택홀(23) 내부에 랜딩플러그(25A, 25)가 매립되어 있다. 여기서, 랜딩플러그(25A, 25B)는 폴리실리콘이다.The landing plugs 25A and 25 are embedded in the contact hole 23 in which the attack prevention film 24 is formed. Here, the landing plugs 25A and 25B are polysilicon.

그리고, 랜딩플러그(25A, 25B) 및 제1층간절연막(22) 상에 제2층간절연막(26)이 형성되고, 제2층간절연막(25)을 관통하여 어느 하나의 랜딩플러그(25A)에 비트라인콘택(27)이 연결되며, 비트라인콘택(27) 위에는 비트라인(28)이 형성된다.Then, a second interlayer insulating film 26 is formed on the landing plugs 25A and 25B and the first interlayer insulating film 22, and passes through the second interlayer insulating film 25 to form a bit in one of the landing plugs 25A. The line contact 27 is connected, and the bit line 28 is formed on the bit line contact 27.

그리고, 비트라인(28) 상부에 제3층간절연막(29)이 형성되고, 제3층간절연막(29) 내에는 다른 랜딩플러그(25A)의 표면을 개방시키는 스토리지노드콘택홀(30)이 구비된다.A third interlayer dielectric layer 29 is formed on the bit line 28, and a storage node contact hole 30 is formed in the third interlayer dielectric layer 29 to open the surface of another landing plug 25A. .

그리고, 스토리지노드콘택홀(30) 내에는 스토리지노드콘택플러그(31)가 매립되어 있다. 여기서, 스토리지노드콘택플러그(31)는 폴리실리콘이다.The storage node contact plug 31 is embedded in the storage node contact hole 30. Here, the storage node contact plug 31 is polysilicon.

도 2에서 제1,2 및 제3층간절연막(22, 26, 29)은 모두 실리콘산화막이다.In FIG. 2, the first, second and third interlayer insulating films 22, 26, and 29 are all silicon oxide films.

도 2에 따르면, 랜딩플러그(25A, 25B)가 매립되는 콘택홀(23)의 양측벽에 어택방지막(24)이 구비되며, 이 어택방지막(24)은 이웃하는 랜딩플러그(25A, 25B)간 분리막의 역할을 한다. 즉, 이웃하는 랜딩플러그(25A, 25B) 사이의 분리막은 어택방지막(24), 제1층간절연막(22), 어택방지막(24)의 3중 구조가 된다. 예컨대, 어택방지막(24)이 실리콘질화막이고, 제1층간절연막(22)이 실리콘산화막이므로, 이웃한 랜딩플러그(25A, 25B) 사이의 분리막은 실리콘질화막, 실리콘산화막, 실리콘질화막의 3중 구조가 된다.According to FIG. 2, an attack prevention film 24 is provided on both side walls of the contact hole 23 in which the landing plugs 25A and 25B are embedded, and the attack prevention film 24 is disposed between neighboring landing plugs 25A and 25B. It acts as a separator. That is, the separation film between the adjacent landing plugs 25A and 25B has a triple structure of the attack prevention film 24, the first interlayer insulating film 22, and the attack prevention film 24. For example, since the attack prevention film 24 is a silicon nitride film and the first interlayer insulating film 22 is a silicon oxide film, the triplet structure of the silicon nitride film, the silicon oxide film, and the silicon nitride film is divided between the adjacent landing plugs 25A and 25B. do.

특히, 어택방지막(24)은 후술하겠지만, 스토리지노드콘택홀(30) 형성후 습식세정 과정에서 제1층간절연막(22)이 용해되더라도 연결되지 않아야 될 랜딩플러그(25A)와 스토리지노드콘택플러그(31)이 접촉하여 발생하는 브릿지를 방지하는 역할을 한다. 이를 위해 어택방지막(24)은 실리콘산화막인 제1 내지 제3층간절연막(22, 26, 29)의 습식세정시 용해되지 않는 불용성, 즉 습식식각 선택비가 큰 물질, 바람직하게는 실리콘질화막으로 형성한다.In particular, the attack prevention film 24 will be described later, but the landing plug 25A and the storage node contact plug 31 which should not be connected even if the first interlayer insulating film 22 is dissolved in the wet cleaning process after the storage node contact hole 30 is formed. ) Prevents bridges from contact. To this end, the attack prevention film 24 is formed of a material having a high wet etching selectivity, preferably a silicon nitride film, which does not dissolve during wet cleaning of the first to third interlayer insulating films 22, 26, and 29, which are silicon oxide films. .

도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도이다. 3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 반도체 기판(21)의 소정 영역에 소자분리막 등의 소정 공정을 진행한다. 이때, 소정 공정이라 함은 소자분리막, 소스/드레인 및 게이트전극을 구비한 트랜지스터 공정이다.As shown in FIG. 3A, a predetermined process such as an isolation layer is performed on a predetermined region of the semiconductor substrate 21. In this case, the predetermined process is a transistor process including an isolation layer, a source / drain, and a gate electrode.

계속해서, 반도체 기판(21) 상에 다수의 게이트 라인(도시하지 않음)을 형성하고, 게이트 라인을 포함하는 반도체 기판(21)의 전면에 제1층간절연막(22)을 증착한다. 이어서, 사진 및 식각 공정을 수행하여 제1층간절연막(22)을 식각하므로써복수의 콘택홀(23)을 형성한다. 여기서, 콘택홀(23)은 랜딩플러그와 반도체기판의 일부를 연결하기 위한 콘택홀이며, 이에 따라 제1층간절연막(22)은 '랜딩플러그분리막'이 된다. 그리고, 제1층간절연막(22)은 BPSG와 같은 산화막, 바람직하게는 실리콘산화막(Silicon oxide)으로 형성한다.Subsequently, a plurality of gate lines (not shown) are formed on the semiconductor substrate 21, and the first interlayer insulating film 22 is deposited on the entire surface of the semiconductor substrate 21 including the gate lines. Subsequently, a plurality of contact holes 23 are formed by etching the first interlayer insulating layer 22 by performing a photo and etching process. Here, the contact hole 23 is a contact hole for connecting a part of the landing plug and the semiconductor substrate, and thus the first interlayer insulating layer 22 becomes a 'landing plug separation layer'. The first interlayer insulating film 22 is formed of an oxide film such as BPSG, preferably silicon oxide.

도 3b에 도시된 바와 같이, 콘택홀(23)의 측벽에 어택방지막(24)을 형성한다.As shown in FIG. 3B, an attack prevention film 24 is formed on the sidewall of the contact hole 23.

상기 어택방지막(24)은 콘택홀(23)이 형성된 제1층간절연막(22)의 표면을 따라 절연막을 증착한 후, 절연막을 에치백 등의 건식식각으로 식각하여 콘택홀(23)의 측벽에만 잔류시키므로써 형성된 것이다. 바람직하게, 어택방지막(24)은 후속 습식세정과정에서 제1층간절연막(22)이 용해되더라도 스토리지노드콘택플러그와 이웃하는 랜딩플러그가 브릿지되는 것을 방지하기 위한 것으로서, 산화막의 습식세정시 용해되지 않는 불용성 물질로 형성한다. 바람직하게 어택방지막(24)은 질화막, 특히 실리콘질화막(Silicon nitride)을 100∼300Å 두께로 형성한다. 이러한 어택방지막(24)은 제1층간절연막(22)과 서로 다른 물질이면서 식각률도 다르다. 또한, 후속 제2층간절연막과도 서로 다른 물질이면서 식각률도 다르다.The attack prevention film 24 deposits an insulating film along the surface of the first interlayer insulating film 22 on which the contact hole 23 is formed, and then the insulating film is etched by dry etching such as etch back to only the sidewalls of the contact hole 23. It is formed by remaining. Preferably, the attack prevention film 24 is to prevent the storage node contact plug and the neighboring landing plug from being bridged even when the first interlayer insulating film 22 is dissolved in a subsequent wet cleaning process, and does not dissolve during wet cleaning of the oxide film. Form insoluble material. Preferably, the attack prevention film 24 forms a nitride film, in particular, a silicon nitride film having a thickness of 100 to 300 Å. The attack prevention film 24 is different from the first interlayer insulating film 22 and has a different etching rate. In addition, the etching rate is different from that of the subsequent second interlayer insulating film.

도 3c에 도시된 바와 같이, 전체 결과물의 전면에 콘택홀(23)을 매립하도록 도전층을 증착한 후, 전면 식각 혹은 평탄화 공정을 수행하여 콘택홀(23) 내부에 매립되는 랜딩플러그(25A, 25B)을 형성한다. 여기서, 랜딩플러그(25A, 25B) 형성을 위한 도전층으로는 폴리실리콘막을 이용하는 것이 바람직하다.As shown in FIG. 3C, after the conductive layer is deposited to fill the contact hole 23 on the entire surface of the entire resultant product, the landing plug 25A, which is embedded in the contact hole 23 by performing an entire surface etching or planarization process, 25B). Here, it is preferable to use a polysilicon film as the conductive layer for forming the landing plugs 25A and 25B.

그리고, 랜딩플러그콘택(25A, 25B)은 비트라인이 콘택될 랜딩플러그(25A)와 스토리지노드가 콘택될 랜딩플러그(25B)으로 구분된다.The landing plug contacts 25A and 25B are divided into a landing plug 25A to which a bit line is to be contacted and a landing plug 25B to which a storage node is to be contacted.

특히, 본 발명의 실시예에서는 이웃하는 랜딩플러그(25A, 25B)간의 분리막 구조가 어택방지막(24), 제1층간절연막(22), 어택방지막(24)의 3중 구조가 된다. 즉, 어택방지막(24)이 실리콘질화막이고, 제1층간절연막(22)이 실리콘산화막이므로, 이웃한 랜딩플러그(25A, 25B) 사이의 분리막은 실리콘질화막, 실리콘산화막, 실리콘질화막의 3중 구조가 된다.In particular, in the embodiment of the present invention, the separation membrane structure between neighboring landing plugs 25A and 25B is a triple structure of the attack prevention film 24, the first interlayer insulating film 22, and the attack prevention film 24. That is, since the attack prevention film 24 is a silicon nitride film and the first interlayer insulating film 22 is a silicon oxide film, the separation structure between adjacent landing plugs 25A and 25B has a triple structure of silicon nitride film, silicon oxide film and silicon nitride film. do.

도 3d에 도시된 바와 같이, 랜딩플러그(25A, 25B) 및 제1층간절연막(22) 상에 제2층간절연막(26)을 증착한다. 이때, 제2층간절연막(26)은 BPSG와 같은 산화막, 바람직하게는 실리콘산화막으로 형성한다.As shown in FIG. 3D, a second interlayer insulating film 26 is deposited on the landing plugs 25A and 25B and the first interlayer insulating film 22. At this time, the second interlayer insulating film 26 is formed of an oxide film such as BPSG, preferably a silicon oxide film.

이어서, 제2층간절연막(26)을 선택적으로 식각하여 비트라인콘택 예정 영역을 오픈한 다음, 비트라인콘택 예정 영역에 도전층을 매립하여 랜딩 플러그(25A)와 콘택되는 비트라인콘택(27)을 형성한다. Subsequently, the bit line contact predetermined region is opened by selectively etching the second interlayer insulating layer 26, and then the bit line contact 27 contacting the landing plug 25A is formed by filling a conductive layer in the bit line contact predetermined region. Form.

계속해서, 비트라인콘택(27) 상에 비트라인(28)을 형성한다. Subsequently, the bit line 28 is formed on the bit line contact 27.

도 3e에 도시된 바와 같이, 비트라인(28) 및 제2층간절연막(26)의 전면 상부에 제3층간절연막(29)을 증착한다. 이때, 제3층간절연막(29)은 BPSG와 같은 산화막, 바람직하게는 실리콘산화막으로 형성한다.As shown in FIG. 3E, a third interlayer insulating film 29 is deposited on the entire surface of the bit line 28 and the second interlayer insulating film 26. At this time, the third interlayer insulating film 29 is formed of an oxide film such as BPSG, preferably a silicon oxide film.

다음으로, 제3층간절연막(29)과 제2층간절연막(26)의 소정 영역을 오픈하도록 사진 및 식각 공정을 수행하여 랜딩 플러그(25B) 상부를 오픈하는 스토리지노드콘택홀(30)을 형성한다.Next, a storage node contact hole 30 for opening the upper portion of the landing plug 25B is formed by performing a photo and etching process so as to open predetermined regions of the third interlayer dielectric layer 29 and the second interlayer dielectric layer 26. .

바람직하게는, 제3층간절연막(29) 상부에 하드마스크를 형성하고, 이를 식각마스크로 이용하여 제3층간절연막(29) 및 제2층간절연막(26)을 선택적으로 건식식 각한다.Preferably, a hard mask is formed on the third interlayer insulating film 29, and the third interlayer insulating film 29 and the second interlayer insulating film 26 are selectively dry-etched using the hard mask as an etching mask.

위와 같은 스토리지노드콘택홀(30) 형성 공정에서 정렬 불량 등의 이유로 제1층간절연막(22)을 식각하는 경우가 발생한다.In the process of forming the storage node contact hole 30, the first interlayer insulating layer 22 may be etched due to misalignment.

이어서, 식각부산물 제거를 위한 습식세정을 진행한다. 이때, 습식세정은 습식 케미컬을 이용한 습식 식각을 이용하는데, 바람직하게는 불산(HF) 또는 BOE(Buffered Oxide Etchant) 용액을 사용한다. Subsequently, wet cleaning is performed to remove the etch byproducts. In this case, wet cleaning uses wet etching using wet chemical, and preferably, hydrofluoric acid (HF) or BOE (Buffered Oxide Etchant) solution is used.

상기한 습식세정시 제1층간절연막(22)이 용해되어서, 즉 일부가 식각되는 현상('A' 참조)이 발생할 수 있다.During the wet cleaning, the first interlayer insulating layer 22 may be dissolved, that is, a portion may be etched (see 'A').

하지만, 본 발명은 습식 케미컬 사용시 제1층간절연막(22)이 식각된다고 하더라도 어택방지막(24)은 식각이 발생하지 않는다. 부연 설명하면, 어택방지막(24)이 질화막이므로, 불산 또는 BOE 용액에 대해 질화막은 용해되지 않아 식각되지 않는다. 이로써 어택방지막(24)에 의해 이웃하는 랜딩플러그(25A)들의 측벽이 노출되지 않는다.However, in the present invention, even when the first interlayer dielectric layer 22 is etched when the wet chemical is used, the attack prevention layer 24 does not etch. In other words, since the attack prevention film 24 is a nitride film, the nitride film is not dissolved in the hydrofluoric acid or BOE solution and is not etched. As a result, the sidewalls of the neighboring landing plugs 25A are not exposed by the attack prevention film 24.

도 3f에 도시된 바와 같이, 스토리지노드콘택홀(30)을 매립하도록 도전층을 형성한 후, 전면 식각 혹은 평탄화 공정을 이용하여 스토리지노드콘택플러그(31)를 형성한다. 여기서, 스토리지노드콘택플러그(31)를 형성하기 위한 도전층으로 폴리실리콘막을 이용하는 것이 바람직하다.As shown in FIG. 3F, after the conductive layer is formed to fill the storage node contact hole 30, the storage node contact plug 31 is formed by using an entire surface etching or planarization process. Here, it is preferable to use a polysilicon film as the conductive layer for forming the storage node contact plug 31.

위와 같이 스토리지노드콘택플러그(31)를 형성할 때, 제1층간절연막(22)의 용해된 부분에 스토리지노드콘택플러그(31)가 형성될 수는 있으나(도면부호 'B' 참조), 어택방지막(24)이 각 랜딩플러그(25A, 25B)의 측벽에 존재하므로, 어택방지 막(24)에 의해 스토리지노드콘택플러그(31)와 이웃하는 랜딩플러그(25A)가 브릿지되는 것을 방지할 수 있다.When forming the storage node contact plug 31 as described above, although the storage node contact plug 31 may be formed in the dissolved portion of the first interlayer insulating layer 22 (see reference numeral 'B'), an attack prevention film Since 24 is present on the sidewalls of the landing plugs 25A and 25B, it is possible to prevent the landing node contact plug 31 and the neighboring landing plug 25A from being bridged by the attack prevention film 24.

상술한 바에 따르면, 본 발명은 이웃하는 랜딩플러그를 분리하기 위한 제1층간절연막(22)에 형성된 콘택홀(23)의 양측벽에 제1층간절연막(22)이 용해되더라도 용해되지 않는 물질인 질화막 계열의 어택방지막(24)을 형성하므로써, 오정렬에 의해 습식 케미컬 사용시 제1층간절연막(22)이 용해되더라도 스토리지노드콘택플러그(31)와 이웃하는 랜딩 플러그(25A) 간의 브릿지를 방지하여 소자의 동작 특성을 개선할 수 있다.As described above, in the present invention, a nitride film which is a material that does not dissolve even when the first interlayer insulating film 22 is dissolved on both side walls of the contact hole 23 formed in the first interlayer insulating film 22 for separating the neighboring landing plugs. By forming a series of attack prevention films 24, even when the first interlayer insulating film 22 is dissolved during wet chemical use due to misalignment, the bridge between the storage node contact plug 31 and the neighboring landing plug 25A is prevented to operate the device. Properties can be improved.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 이웃하는 랜딩 플러그와 스토리지노드콘택플러그의 브릿지 현상을 방지하여 수율 향상을 기대할 수 있는 효과가 있다.The present invention as described above has an effect that can be expected to improve the yield by preventing the bridge phenomenon of the neighboring landing plug and the storage node contact plug.

Claims (15)

반도체 기판 상에 제1콘택홀을 갖는 제1절연막을 형성하는 단계;Forming a first insulating film having a first contact hole on the semiconductor substrate; 상기 제1콘택홀의 양측벽에 어택방지막을 형성하는 단계; 및Forming an anti-attack film on both sidewalls of the first contact hole; And 상기 제1콘택홀에 도전 물질을 매립하여 제1콘택플러그를 형성하는 단계;Forming a first contact plug by filling a conductive material in the first contact hole; 상기 제1콘택플러그가 형성된 상기 제1절연막 상부에 제2절연막을 형성하는 단계;Forming a second insulating layer on the first insulating layer on which the first contact plug is formed; 상기 제2절연막의 소정 영역을 식각하여 상기 제1콘택플러그를 오픈시키는 제2콘택홀을 형성하는 단계; 및Etching a predetermined region of the second insulating layer to form a second contact hole for opening the first contact plug; And 상기 제2콘택홀에 상기 제1콘택플러그와 연결되는 제2콘택플러그를 매립하는 단계Embedding a second contact plug connected to the first contact plug in the second contact hole 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1,2절연막과 상기 어택방지막은 서로 다른 절연막인 반도체소자의 제조 방The first and second insulating films and the attack prevention film may be different insulating films. 제2항에 있어서,The method of claim 2, 상기 제1,2절연막과 상기 어택방지막은 식각률이 서로 다른 절연막인 반도체소자의 제조 방법.And the first and second insulating films and the attack prevention film are insulating films having different etching rates. 제3항에 있어서,The method of claim 3, 상기 제1 및 제2절연막은 산화막인 반도체소자의 제조 방법.And the first and second insulating films are oxide films. 제4항에 있어서,The method of claim 4, wherein 상기 어택방지막은 질화막인 반도체소자의 제조 방법.The attack prevention film is a nitride film manufacturing method of a semiconductor device. 제5항에 있어서,The method of claim 5, 상기 어택방지막은 실리콘질화막인 반도체소자의 제조 방법.The attack prevention film is a silicon nitride film manufacturing method of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 제2콘택홀을 형성하는 단계는,Forming the second contact hole, 상기 제2절연막을 건식식각하는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device for dry etching the second insulating film. 제1항 내지 제7항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 7, 상기 제2콘택홀을 형성한 후에,After forming the second contact hole, 습식케미컬을 이용한 세정 단계를 더 포함하는 반도체소자의 제조 방법.The method of manufacturing a semiconductor device further comprising a cleaning step using a wet chemical. 제8항에 있어서,The method of claim 8, 상기 습식 케미컬은,The wet chemical is, 불산(HF) 또는 BOE(Buffered Oxide Etchant) 용액을 사용하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device using hydrofluoric acid (HF) or BOE (Buffered Oxide Etchant) solution. 제1항에 있어서,The method of claim 1, 상기 제2콘택플러그는,The second contact plug, 상기 제2콘택홀을 매립하도록 도전층을 형성한 후에 전면식각 또는 평탄화공정을 진행하여 형성하는 반도체 소자의 제조 방법.And forming a conductive layer to fill the second contact hole, and then performing a full surface etching or planarization process. 제1항에 있어서,The method of claim 1, 상기 제2콘택플러그는, 폴리실리콘으로 형성하는 반도체소자의 제조 방법.The second contact plug is formed of polysilicon. 제11항에 있어서,The method of claim 11, 상기 제1콘택플러그는 랜딩플러그이고, 상기 제2콘택콘택플러그는 스토리지노드콘택플러그인 반도체소자의 제조 방법.The first contact plug is a landing plug, and the second contact contact plug is a storage node contact plug. 반도체기판;Semiconductor substrates; 상기 반도체기판 상에 형성되며 복수의 콘택홀이 구비된 절연막;An insulating film formed on the semiconductor substrate and having a plurality of contact holes; 상기 콘택홀의 측벽에 형성된 어택방지막;An attack prevention film formed on sidewalls of the contact hole; 상기 콘택홀의 내부에 매립된 복수의 랜딩플러그; 및A plurality of landing plugs embedded in the contact hole; And 상기 복수의 랜딩플러그 중 적어도 어느 하나의 랜딩플러그 위에 형성된 스토리지노드콘택플러그A storage node contact plug formed on at least one of the landing plugs; 를 포함하는 반도체소자.Semiconductor device comprising a. 제13항에 있어서,The method of claim 13, 상기 어택방지막은 질화막이고, 상기 절연막은 산화막인 반도체소자.The attack prevention film is a nitride film, and the insulating film is an oxide film. 제14항에 있어서,The method of claim 14, 상기 어택방지막은 실리콘질화막이고, 상기 절연막은 실리콘산화막인 반도체 소자.The attack prevention film is a silicon nitride film, and the insulating film is a silicon oxide film.
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KR20000008175A (en) * 1998-07-10 2000-02-07 윤종용 Method of forming contact in semiconductor device and structure of contact
KR20050028753A (en) * 2003-09-19 2005-03-23 삼성전자주식회사 Semiconductor device having a cylinder shaped storage electrode and method of fabricating the same
KR20060019359A (en) * 2004-08-27 2006-03-03 주식회사 하이닉스반도체 Method for fabrication of semiconductor device capable of preventing chemical attack
KR20060067746A (en) * 2004-12-15 2006-06-20 동부일렉트로닉스 주식회사 Method for forming the copper interconnection of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000008175A (en) * 1998-07-10 2000-02-07 윤종용 Method of forming contact in semiconductor device and structure of contact
KR20050028753A (en) * 2003-09-19 2005-03-23 삼성전자주식회사 Semiconductor device having a cylinder shaped storage electrode and method of fabricating the same
KR20060019359A (en) * 2004-08-27 2006-03-03 주식회사 하이닉스반도체 Method for fabrication of semiconductor device capable of preventing chemical attack
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