KR100440471B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
- Publication number
- KR100440471B1 KR100440471B1 KR10-2002-0060305A KR20020060305A KR100440471B1 KR 100440471 B1 KR100440471 B1 KR 100440471B1 KR 20020060305 A KR20020060305 A KR 20020060305A KR 100440471 B1 KR100440471 B1 KR 100440471B1
- Authority
- KR
- South Korea
- Prior art keywords
- copper
- layer
- film
- plating
- interlayer insulating
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 구리배선 형성 시 디슁 현상 없이 구리의 평탄화를 확보하고 비아 주변에 결함이 발생되지 않도록 하는 것이다. 이를 위해 본 발명에서는 비아를 충진시키도록 구리도금층을 형성하기 전에, 층간절연막의 상부에 위치하는 구리씨드층 상에 도금방지막을 형성하여 구리도금층이 층간절연막의 상부에는 형성되지 않고 비아의 상부에만 형성되도록 하며, 이로써, 층간절연막 상부에 위치하는 구리 제거를 위해 과도연마를 수행할 필요가 없으므로 구리의 디슁 현상을 방지하는 효과가 있다.The present invention relates to a method for manufacturing a semiconductor device, the purpose of which is to ensure the flattening of copper without deducting when forming the copper wiring and to prevent defects around the vias. To this end, in the present invention, before forming the copper plating layer to fill the vias, a plating prevention film is formed on the copper seed layer positioned on the interlayer insulating film so that the copper plating layer is not formed on the upper portion of the interlayer insulating film but formed only on the top of the via. As a result, there is no need to perform overpolishing to remove copper located above the interlayer insulating film, thereby preventing the copper from dripping.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 구리배선을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a copper wiring.
일반적으로 금속 배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성이 우수한 금속 배선 재료이므로, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.In general, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, since copper (Cu) is a metal wiring material having a low specific resistance and excellent reliability compared to tungsten and aluminum, studies are being actively conducted to replace metal wiring of semiconductor devices with copper.
그런데, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(Reactive Ion Etching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 건식 식각 공정을 거치지 않으면서 배선을 형성할 수 있는 방법에 관하여 활발히 연구되고 있는바, 이러한 공정을 다마신(damascene) 공정이라 한다.However, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by dry etching. Therefore, in the case of copper, active research on a method for forming a wiring without undergoing a dry etching process, such a process is called a damascene process.
기존의 구리를 이용한 다마신 공정에 의하면 구리를 웨이퍼에 전면(blanket) 증착한 후에 불필요한 웨이퍼 표면의 구리층을 화학기계적 연마 공정으로 제거함으로써 최종적인 구리배선을 형성한다.According to the damascene process using copper, final copper wiring is formed by depositing copper on a wafer and removing unnecessary copper layers by chemical mechanical polishing.
그러면, 첨부된 도 1a 내지 도 1e를 참조하여 종래의 구리 배선 형성 방법을 설명한다.Next, a conventional copper wiring forming method will be described with reference to FIGS. 1A to 1E.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판의 상부에 통상의 반도체 소자 공정을 진행하여 개별 소자가 형성된 반도체 기판의 구조물(1)을 형성하고, 반도체 기판의 구조물(1) 상에 하부절연막(2)을 형성한 다음, 하부절연막(2)을 선택적으로 식각하여 배선구(100)를 형성하고 구리를 전면증착한 후, 하부절연막(2)이 노출될 때까지 화학기계적 연마하여 하부구리배선(3)을 형성한다.First, as shown in FIG. 1A, a semiconductor device process is performed on an upper portion of a semiconductor substrate to form a structure 1 of a semiconductor substrate on which individual elements are formed, and then a lower insulating layer on the structure 1 of the semiconductor substrate is formed. 2) and then selectively etch the lower insulating film 2 to form the wiring holes 100, deposit copper on the entire surface, and chemically polish until the lower insulating film 2 is exposed to the lower copper wiring ( 3) form.
이어서, 하부절연막(2) 및 하부구리배선(3)의 상부 전면에 SiC 베리어막(4)을 300Å 두께로 증착한 후 SiC 베리어막(4) 상에 SiOC막(5)을 6000Å 두께로 증착하여 층간절연막을 형성한다.Subsequently, the SiC barrier film 4 is deposited on the entire upper surface of the lower insulating film 2 and the lower copper wiring 3 to 300 mW, and the SiOC film 5 is deposited on the SiC barrier film 4 to 6000 mW. An interlayer insulating film is formed.
다음, 도 1b에 도시된 바와 같이, SiOC막(5)을 선택적으로 식각하여 하부구리배선(3)을 노출시키는 비아(101)를 형성한다.Next, as shown in FIG. 1B, the SiOC film 5 is selectively etched to form the vias 101 exposing the lower copper wiring 3.
다음, 도 1c에 도시된 바와 같이, 비아(101)를 포함한 SiOC막(5)의 상부 전면에 구리의 확산 방지를 위해 TaN으로 이루어진 확산방지막(6)을 300Å 두께로 증착한다.Next, as shown in FIG. 1C, a diffusion barrier film 6 made of TaN is deposited on the entire upper surface of the SiOC film 5 including the vias 101 to have a thickness of 300 μs.
다음, 도 1d에 도시된 바와 같이, 확산방지막(6) 상에 구리층(7)을 형성하는데, 구리층(7)을 형성할 때에는 플라즈마 화학기상증착 방법으로 구리씨드층을1000Å의 두께로 형성한 다음, 구리씨드층 상에 전기도금방법으로 비아를 충분히 매립하도록 3500Å 두께의 구리도금층을 형성한다.Next, as shown in FIG. 1D, a copper layer 7 is formed on the diffusion barrier 6, and when the copper layer 7 is formed, a copper seed layer is formed to a thickness of 1000 kPa by plasma chemical vapor deposition. Then, a 3500 mm thick copper plated layer is formed on the copper seed layer to sufficiently fill the via by electroplating.
다음, 도 1e에 도시된 바와 같이, SiOC막(5)이 노출될 때까지 구리층(7)을 화학기계적 연마하여 상면을 평탄화한다.Next, as shown in FIG. 1E, the upper surface is planarized by chemical mechanical polishing of the copper layer 7 until the SiOC film 5 is exposed.
그러나, 구리층의 화학기계적 연마시 SiOC막(5) 상부에 위치하는 구리를 제거하기 위해서는 약간의 과도연마를 수행해야 하는데, 이로 인하여 비아에 형성된 구리가 과도하게 식각되어 움푹 패이는 디슁(dishing) 현상이 발생하는 문제점이 있었다.However, during the chemical mechanical polishing of the copper layer, some overpolishing should be performed to remove the copper located on the SiOC film 5, which causes the copper formed in the via to be excessively etched and pitted. There was a problem that the phenomenon occurs.
디슁 현상이 발생하면 상면의 평탄화가 순조롭게 진행되지 못하여 후속 포토리소그래피 공정시 오정렬 등의 문제를 야기시키는 문제점이 있었다.When the dimming phenomenon occurs, the flattening of the top surface does not proceed smoothly, causing problems such as misalignment during the subsequent photolithography process.
이를 방지하기 위해 과도연마를 하지 않을 경우 구리의 화학기계적 연마가 덜 이루어져 비아 주변에 결함이 발생하는 문제점이 있었다.In order to prevent this, if the overpolishing is not performed, the chemical mechanical polishing of copper is less likely to cause defects around the vias.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 구리배선 형성시 디슁 현상 없이 구리의 평탄화를 확보하고 비아 주변에 결함이 발생되지 않도록 하는 것이다.The present invention is to solve the problems as described above, the object is to ensure the flattening of the copper without the deducting phenomenon when forming the copper wiring and to prevent defects around the vias.
도 1a 내지 도 1e는 종래 반도체 소자 제조 방법을 도시한 단면도이고,1A to 1E are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
도 2a 내지 도 2g는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 비아를 충진시키도록 구리도금층을 형성하기 전에, 층간절연막의 상부에 위치하는 구리씨드층 상에 도금방지막을 형성하여 구리도금층이 층간절연막의 상부에는 형성되지 않고 비아의상부에만 형성되도록 한다.In order to achieve the above object, in the present invention, before forming the copper plating layer to fill the vias, a plating prevention film is formed on the copper seed layer positioned on the interlayer insulating film so that the copper plating layer is formed on the top of the interlayer insulating film. It is not to be formed but only to be formed on top of the via.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 형성된 하부 금속배선을 포함한 상부 전면에 층간절연막을 증착하고 층간절연막을 선택적으로 식각하여 비아를 형성하는 단계; 비아의 내부를 포함하여 층간절연막의 상부 전면에 비아의 내면을 따라서 구리씨드층을 형성하는 단계; 구리씨드층 상에 도금방지막을 형성하는 단계; 도금방지막을 선택적으로 식각하여 비아의 내부 및 상부에 형성된 구리씨드층을 노출시키는 단계; 비아를 충진시키도록 노출된 구리씨드층 상에 도금법으로 구리도금층을 형성하는 단계; 층간절연막이 노출될 때까지 구리도금층, 도금방지막 및 구리씨드층을 화학기계적 연마하는 단계를 포함하여 이루어진다.That is, the semiconductor device manufacturing method according to the present invention comprises the steps of depositing an interlayer insulating film on the upper surface including the lower metal wiring formed on the structure of the semiconductor substrate and selectively etching the interlayer insulating film to form a via; Forming a copper seed layer along an inner surface of the via on the entire upper surface of the interlayer insulating layer including the inside of the via; Forming an anti-plating film on the copper seed layer; Selectively etching the anti-plating film to expose the copper seed layer formed on and in the via; Forming a copper plating layer by plating on the exposed copper seed layer to fill the vias; Chemical mechanical polishing the copper plating layer, the anti-plating film and the copper seed layer until the interlayer insulating film is exposed.
이 때, 층간절연막으로는 SiOC막을 형성하고, 층간절연막의 하부에는 SiC 베리어막을 더 형성하는 것이 바람직하다.At this time, it is preferable that a SiOC film is formed as an interlayer insulating film, and a SiC barrier film is further formed below the interlayer insulating film.
비아를 형성할 때에는 비아로 예정된 영역의 상부에 위치하는 층간절연막을 노출시키는 감광막 패턴을 형성한 후, 감광막 패턴을 마스크로 하여 노출된 층간절연막을 식각하여 비아를 형성하는 것이 바람직하다.When the via is formed, it is preferable to form a photoresist pattern that exposes the interlayer insulating film positioned over the region defined as the via, and then to form the via by etching the exposed interlayer insulating film using the photoresist pattern as a mask.
구리씨드층의 하부에는 비아의 내부를 포함하여 층간절연막의 상부 전면에 TaN으로 이루어진 확산방지막을 100 내지 500Å 두께로 형성하는 것이 바람직하며, 구리씨드층은 플라즈마 화학기상증착 방법으로 500~1500Å의 두께로 형성하는 것이 바람직하다.Under the copper seed layer, it is preferable to form a diffusion barrier layer consisting of TaN on the entire upper surface of the interlayer insulating film including the inside of the via to have a thickness of 100 to 500 mW, and the copper seed layer is 500 to 1500 mW by the plasma chemical vapor deposition method. It is preferable to form.
도금방지막으로는 SiN, SiC, SiOC, 티이오에스(TEOS : tetra ethyl orthosilicate), 또는 SiO2등을 100 내지 500Å 두께로 형성하며, 도금방지막을 선택적으로 식각할 때에는, 도금방지막 상에 비아의 상부에 위치하는 도금방지막을 노출시키는 감광막 패턴을 형성한 후, 감광막 패턴을 마스크로 하여 노출된 도금방지막을 식각하여 비아의 내부 및 상부에 형성된 구리씨드층을 노출시키는 것이 바람직하다.As the anti-plating film, SiN, SiC, SiOC, tetra ethyl orthosilicate (TEOS), or SiO 2 is formed to have a thickness of 100 to 500Å, and when the anti-plating film is selectively etched, After forming a photoresist pattern exposing the anti-plating layer to be located, it is preferable to expose the copper seed layers formed on and in the via by etching the exposed anti-plating layer using the photoresist pattern as a mask.
이하, 본 발명의 일 실시예에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 2a 내지 도 2g는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail. 2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 상부에 통상의 반도체 소자 공정을 진행하여 개별 소자가 형성된 반도체 기판의 구조물(11)을 형성하고, 반도체 기판의 구조물(11) 상에 하부절연막(12)을 형성한 다음, 하부절연막(12)을 선택적으로 식각하여 배선구(200)를 형성하고 구리를 전면증착한 후, 하부절연막(12)이 노출될 때까지 화학기계적 연마하여 하부배선(13)을 형성한다.First, as shown in FIG. 2A, a semiconductor device process is performed on an upper portion of a semiconductor substrate to form a structure 11 of a semiconductor substrate on which individual elements are formed, and then a lower insulating layer on the structure 11 of the semiconductor substrate is formed. 12) and then selectively etch the lower insulating film 12 to form the wiring holes 200, depositing copper on the entire surface, and chemically polishing the lower insulating film 12 until the lower insulating film 12 is exposed. ).
이 때, 하부배선(13)을 반드시 구리로 형성할 필요는 없으며, 텅스텐과 같은 금속막을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 하부 배선(13)을 형성할 수도 있다.In this case, the lower interconnection 13 is not necessarily formed of copper, and a lower interconnection 13 for forming a circuit of a semiconductor device may be formed by forming and patterning a metal film such as tungsten.
이어서, 하부절연막(12) 및 하부배선(13)의 상부 전면에 유전상수가 낮은 저유전물질인 SiC를 증착하여 SiC 베리어막(14)을 100 내지 500Å 정도의 두께로 증착하고, SiC 베리어막(4) 상에는 저유전물질로 이루어진 SiOC막(15)을 대략 5000내지 7000Å 정도의 두께로 증착하여 층간절연막을 형성한다. 바람직하게는 SiC 베리어막(14)은 300Å의 두께로, SiOC막(15)은 6000Å의 두께로 형성한다.Subsequently, SiC, which is a low dielectric material having a low dielectric constant, is deposited on the entire upper surface of the lower insulating film 12 and the lower wiring 13 to deposit the SiC barrier film 14 to a thickness of about 100 to 500 kV, and the SiC barrier film ( 4) On the SiOC film 15 made of a low dielectric material is deposited to a thickness of approximately 5000 to 7000 Å to form an interlayer insulating film. Preferably, the SiC barrier film 14 is formed to a thickness of 300 GPa, and the SiOC film 15 is formed to a thickness of 6000 GPa.
이와 같이 저유전물질을 이용하여 층간절연막을 형성하면 구리 배선층 간의 커패시턴스 값이 낮아져 전류의 흐름에 대한 방해가 적고 신호의 전달이 빨라지며, 따라서 소자의 동작속도가 빨라진다.When the interlayer insulating film is formed using the low dielectric material as described above, the capacitance value between the copper wiring layers is lowered, thereby reducing the interruption of the current flow and speeding up the signal transmission, thereby increasing the operation speed of the device.
다음, 도 2b에 도시된 바와 같이, SiOC막(15) 상에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 영역의 상부에 위치하는 SiOC막(15)을 노출시키는 제1감광막 패턴(미도시)을 형성한 후, 제1감광막 패턴을 마스크로 하여 노출된 SiOC막(15)을 식각하여 비아(201)를 형성한 다음, 제1감광막 패턴을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2B, a first photoresist pattern (not shown) is applied to the SiOC film 15 to expose the SiOC film 15 positioned on the region intended as a via by exposing and developing the photoresist film. After forming the via, the exposed SiOC film 15 is etched using the first photoresist pattern as a mask to form a via 201, and then the first photoresist pattern is removed and a cleaning process is performed.
다음, 도 2c에 도시된 바와 같이, 비아(201)를 포함한 SiOC막(15)의 상부 전면에 구리의 확산 방지를 위해 TaN으로 이루어진 확산방지막(16)을 100 내지 500Å 정도의 두께로 증착하며, 바람직하게는 300Å의 두께로 증착한다.Next, as shown in Figure 2c, to prevent the diffusion of copper on the upper surface of the SiOC film 15 including the via 201, a diffusion barrier 16 made of TaN is deposited to a thickness of about 100 ~ 500Å, Preferably, the deposition is performed at a thickness of 300 mm 3.
다음, 도 2d에 도시된 바와 같이, 확산방지막(16) 상에 플라즈마 화학기상증착 방법으로 구리씨드층(17)을 500 내지 1500Å 정도의 두께로 형성한 다음, 구리씨드층(17) 상에 도금방지막(18)을 100 내지 500Å 정도의 두께로 전면 증착한다. 바람직하게는 구리씨드층(17)을 1000Å 두께로 도금방지막(18)을 300Å 두께로 증착한다.Next, as shown in FIG. 2D, the copper seed layer 17 is formed on the diffusion barrier layer 16 by a plasma chemical vapor deposition method to a thickness of about 500 to 1500 kPa, and then plated on the copper seed layer 17. The prevention film 18 is deposited all over with a thickness of about 100 to 500 mW. Preferably, the copper seed layer 17 is deposited to a thickness of 1000 kPa, and the anti-plating film 18 is deposited to a thickness of 300 kPa.
도금방지막(18)으로는 SiN, SiC, SiOC, 티이오에스(TEOS), 또는 SiO2등을형성할 수 있으며, 이 때 SiO2는 SiH4를 소스물질로 사용하여 화학기상증착으로 형성한 것 등을 사용할 수 있다.As the anti-plating film 18, SiN, SiC, SiOC, TEOS, or SiO 2 may be formed, wherein SiO 2 is formed by chemical vapor deposition using SiH 4 as a source material. Can be used.
다음, 도 2e에 도시된 바와 같이, 도금방지막(18) 상에 감광막을 도포하고 노광 및 현상하여 비아 상부에 위치하는 도금방지막(18)을 노출시키는 제2감광막 패턴(마스크)을 형성한 후, 제2감광막 패턴을 마스크로 하여 노출된 도금방지막(18)을 식각하여 그 하부의 구리씨드층(17)을 노출시킨 다음, 제2감광막 패턴을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2E, after forming a second photoresist pattern (mask) exposing the plating prevention layer 18 positioned on the via by applying a photoresist film and exposing and developing the plating prevention film 18, The exposed plating prevention film 18 is etched using the second photoresist pattern as a mask to expose the lower copper seed layer 17, and then the second photoresist pattern is removed and a cleaning process is performed.
다음, 도 2f에 도시된 바와 같이, 노출된 구리씨드층(17) 상에 전기도금방법으로 비아를 충분히 매립하도록 대략 3500Å 정도 두께의 구리도금층(17')을 형성한다.Next, as shown in FIG. 2F, a copper plating layer 17 ′ having a thickness of approximately 3500 kPa is formed on the exposed copper seed layer 17 so as to sufficiently fill the via by an electroplating method.
다음, 도 2g에 도시된 바와 같이, SiOC막(15)이 노출될 때까지 구리도금층(17'), 도금방지막(18) 및 구리씨드층(17)을 화학기계적 연마하여 상면을 평탄화한다.Next, as shown in FIG. 2G, the upper surface of the copper plating layer 17 ′, the anti-plating film 18 and the copper seed layer 17 is chemically polished until the SiOC film 15 is exposed.
이 때 SiOC막(15) 상부에는 구리도금층(17') 없이 구리씨드층(17)만이 형성되어 있어서 화학기계적 연마할 구리의 두께가 얇기 때문에 종래와 비교하여 과도연마할 필요가 없다.At this time, since only the copper seed layer 17 is formed on the SiOC film 15 without the copper plating layer 17 ', the thickness of copper to be chemically mechanically polished is not necessary.
상술한 바와 같이, 본 발명에서는 구리층의 화학기계적 연마시 SiOC막 상부에 위치하는 구리를 제거하기 위해서 과도연마를 수행할 필요가 없기 때문에, 과도연마에 의한 구리의 디슁 현상을 방지하는 효과가 있다.As described above, in the present invention, it is not necessary to perform overpolishing in order to remove copper located on the SiOC film during the chemical mechanical polishing of the copper layer, and thus, there is an effect of preventing the phenomenon of copper dipping due to overpolishing. .
또한, 디슁 현상이 방지되므로 충분히 화학기계적 연마할 수 있어서 비아 주변의 결함 발생을 방지하는 효과가 있다.In addition, since the dishing phenomenon is prevented, the chemical mechanical polishing can be sufficiently performed, thereby preventing the occurrence of defects around the vias.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0060305A KR100440471B1 (en) | 2002-10-02 | 2002-10-02 | Fabrication method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0060305A KR100440471B1 (en) | 2002-10-02 | 2002-10-02 | Fabrication method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040029867A KR20040029867A (en) | 2004-04-08 |
| KR100440471B1 true KR100440471B1 (en) | 2004-07-14 |
Family
ID=37331213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2002-0060305A KR100440471B1 (en) | 2002-10-02 | 2002-10-02 | Fabrication method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100440471B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0930647A1 (en) * | 1998-01-20 | 1999-07-21 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
| JP2000323568A (en) * | 1999-05-11 | 2000-11-24 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| KR20000076081A (en) * | 1997-03-10 | 2000-12-26 | 야마모토 카즈모토 | Wiring Forming Method for Semiconductor Device and Semiconductor Device |
| KR20020040091A (en) * | 2000-11-23 | 2002-05-30 | 윤종용 | Slurry for chemical mechanical polishing and manufacturing method of copper metal interconnection layer using the same |
-
2002
- 2002-10-02 KR KR10-2002-0060305A patent/KR100440471B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000076081A (en) * | 1997-03-10 | 2000-12-26 | 야마모토 카즈모토 | Wiring Forming Method for Semiconductor Device and Semiconductor Device |
| EP0930647A1 (en) * | 1998-01-20 | 1999-07-21 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
| JP2000323568A (en) * | 1999-05-11 | 2000-11-24 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| KR20020040091A (en) * | 2000-11-23 | 2002-05-30 | 윤종용 | Slurry for chemical mechanical polishing and manufacturing method of copper metal interconnection layer using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040029867A (en) | 2004-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6071809A (en) | Methods for forming high-performing dual-damascene interconnect structures | |
| US7545045B2 (en) | Dummy via for reducing proximity effect and method of using the same | |
| US6080656A (en) | Method for forming a self-aligned copper structure with improved planarity | |
| JP2000188293A (en) | Method for optimizing chemical-mechanical polishing of copper in copper interconnecting process for integrated circuit | |
| US6133143A (en) | Method of manufacturing interconnect | |
| US7960839B2 (en) | Semiconductor interconnection line and method of forming the same | |
| US6674170B1 (en) | Barrier metal oxide interconnect cap in integrated circuits | |
| US20090170305A1 (en) | Method for improving electromigration lifetime for cu interconnect systems | |
| KR101107746B1 (en) | method of forming a metal line in semiconductor device | |
| KR100440471B1 (en) | Fabrication method of semiconductor device | |
| US20020127849A1 (en) | Method of manufacturing dual damascene structure | |
| KR100458594B1 (en) | Fabrication method of semiconductor device | |
| KR20090024854A (en) | Metal line and method for fabricating metal line of semiconductor device | |
| KR20010009036A (en) | A method of forming conductive lines and interconnection thereof | |
| KR20040057517A (en) | Method of forming a dual damascene pattern | |
| KR100497776B1 (en) | Multi-layer fabrication technique for semiconductor device | |
| KR100418920B1 (en) | Method for forming interconnection of semiconductor device | |
| KR101036159B1 (en) | Method for forming metal line used dual damascene | |
| KR20000056852A (en) | Method of fabricating a metal-interconnect structure in integrated circuit | |
| KR100198653B1 (en) | Semiconductor device metallisation method | |
| KR100815944B1 (en) | Method for forming copper wiring layers in semiconductor devices | |
| KR20040010355A (en) | Method for forming metal line of semiconductor device | |
| KR100393968B1 (en) | method for forming dual damascene of semiconductor device | |
| KR100458589B1 (en) | Fabrication method of semiconductor device | |
| KR20070026962A (en) | Method for forming a metal line in semiconductordevice |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120619 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |