KR20000056852A - Method of fabricating a metal-interconnect structure in integrated circuit - Google Patents

Abstract

PURPOSE: A method for manufacturing a metal interconnection structure in an integrated circuit is provided to eliminate a defect that an upper surface of a dual damascene structure is formed as a shape of a dish, and to avoid a short circuit or a bridging defect caused by a remaining material of a barrier layer on an insulation layer. CONSTITUTION: A method for manufacturing a metal interconnection structure in an integrated circuit comprises the steps of: forming an insulation layer on the entire surface of a semiconductor substrate; forming a trench in the insulation layer; forming a first barrier layer on an exposed entire surface of the insulation layer, not filling up the trench completely; forming a second barrier layer on an exposed entire surface of the first barrier layer, not filling up the trench completely; eliminating the first and second barrier layer covering the entire insulation layer excluding the trench; evaporating a metal on the entire surface of the insulation layer to form a metalization layer for filling up the trench completely; and performing a selective removal process for eliminating the metalization layer covering the insulation layer.

Description

METHOD OF FABRICATING A METAL-INTERCONNECT STRUCTURE IN INTEGRATED CIRCUIT}

TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor, and more particularly, to a method of manufacturing a metal-interconnect structure in an integrated circuit. Even more specifically, the process of the present invention is useful for the production of copper-based dual damascene structures and is generally copper-chemical mechanical polish (Cu-CMP). It is a chemical mechanical polishing technique required to polish a copper-based metallization layer to form a double damascene structure called.

High density integrated circuits, such as Very Large Scale Integration ICs (VLSI ICs), typically include two or more metal interconnect structures provided as wiring lines for electrically connecting various components within the integrated circuit. It is formed of a multi-level interconnect structure. The multilayer interconnect structure includes a first layer (base layer) of a metal interconnect structure electrically connected to a source / drain region of a MOS transistor formed in an integrated circuit, wherein the base of the metal interconnect structure is formed by an insulating film. At least one second membrane of the metal interconnect structure separate from the membrane. The second film of the metal interconnect structure is electrically connected to the base film of the metal interconnect structure via a metal plug (or via) formed in the insulating film. Another film of the metal interconnect structure may be formed on the front surface of the second film of the metal interconnect structure that constitutes the multilayer interconnect structure.

However, one drawback of the conventional multilayer interconnection structure is that it increases the capacitive effect between neighboring metal lines when the integrated circuit device is further scaled down, and thus resistance-capacitance (RC) This increases the delay and cross talk in the metal plug. As a result, the transmission of data through the metal lines in the metal interconnect structure becomes slow, thus degrading the performance of the integrated circuit device.

To increase the conductivity of data transmission lines in integrated circuits, copper is currently being experimented to form metal interconnect structures in integrated circuits. To simplify the process, the metal interconnect structures can be formed together in conjunction with a metal plug or a plug by a so-called dual damascene process. A dual damascene process for producing metal interconnect structures in addition to conventional metal plugs is described next with reference to FIGS. 1A-1D.

Referring to FIG. 1A, in an initial step, the semiconductor substrate 10 is prepared. Next, an insulating film 12 such as a silicon dioxide film is deposited on the entire upper surface of the substrate 10.

In FIG. 1B, in a subsequent step, a photolithography process and an isotropic etch process in order to form the trench 14a in the predefined location in the insulating film 12, that is, where the metal interconnect structure is formed. Is performed. The trench 14a is formed in the insulating film 12 to a predetermined depth without exposing the surface of the substrate 10.

Referring to FIG. 1C, the photolithography process and the isotropic etching process are again performed to further remove the narrowed portion of the insulating layer 12 disposed under the trench 14a until the upper surface of the substrate 10 is exposed. Is performed. The void portion left behind is provided as a contact opening (or via opening), which is indicated by reference numeral 14b. As shown in FIG. 1C, the contact opening 14b is narrower than the trench 14a. The barrier film 16 is deposited on the surface of all exposed substrates 10 and the insulating film 12 with a heat resistant metal such as tantalum (Ta) or tantalum nitride (TaN) in a substantially uniform thickness. This barrier film 16 may increase the bonding strength between the insulating film 12 and subsequent trench metals such as copper in the trench 14a and the contact opening 14b, and may also increase the trench 14a and contact. Metal deposited in the opening 14b can be prevented from diffusing into neighboring components.

Next, referring to FIG. 1D, a metal, such as copper, is used to form the metal plug 18b in the contact opening 14b and the metal interconnect structure in the trench 14a. It is deposited into trench 14a. The combination of the metal interconnect structure 18a and the metal plug 18b represents a dual damascene structure. Since the metal is deposited above the top level of the trench 14a and the portion of the barrier film 16 lying on the top surface of the insulating film 12 is not desired, the metal interconnect structure 18a may be of interest. A chemical mechanical polishing (CMP) process is performed to polish the excess upper part and unwanted portions of the barrier film 16 on the top surface of the insulating film 12. This completes the fabrication of the dual damascene structure in the integrated circuit device. In the dual damascene structure, the metal interconnect structure 18a acts as one level of the metal interconnect structure in the integrated circuit device and via the metal plug 18b a transistor device (not shown in the figure). Or a lower level of a subsequent metal interconnect structure (not shown in the figure) formed in the semiconductor substrate 10.

However, one drawback of the method described above is that the metal interconnect structure causes the top surface of the metal interconnect structure 18a to be made entirely in a dish-like shape, as shown in FIG. 1D. A chemical mechanical polishing process for 18a. This undesired dishing effect is due to the following fact: during the chemical mechanical polishing process, the polishing rate at which the polishing rate acting on the metal interconnect structure 18a acts on the barrier film 16. Due to being very different. For example, when the metal interconnect structure 18a is formed of copper (Cu) and the barrier layer 16 is formed of tantalum nitride (TaN), the selectivity ratio of Cu and TaN in a chemical mechanical polishing process selectivity is 8 to 16. When the barrier film 16 is formed of tantalum (Ta), the selectivity between Cu and Ta is 12 to 20. This high selectivity causes the chemical mechanical polishing process to act on the copper-based metal interconnect structure 18a faster than the barrier film 16 and, consequently, the metal interconnect structure 18a. Undesired dish shapes 19 are formed on the top surface.

This dish shape 19 makes the entire upper surface of the wafer very uneven, thus making the subsequently deposited insulating oxide poor in planarization. This causes the erosion of the oxide film and consequently increases the resistance of the metal interconnect structure 18a, thus degrading the performance of the resulting integrated circuit device.

Moreover, unwanted portions of the barrier film 16 lying on the top surface of the insulating film 12 are not always completely polished by a chemical mechanical polishing process. After the chemical mechanical polishing process, a residue still remains on the insulating film 12, which causes unwanted short-circuit and bridging effects.

Conventional solutions to the above-mentioned problems provide an undesirably high chemical mechanical polishing selectivity between the copper-based metal interconnect structure 18a and the tantalum (Ta) or tantalum nitride (TaN) based barrier film 16. To reduce, it is to use multiple polish steps with various kinds of slurries and other polishing pads. However, this embodiment greatly increases the number of rework of the chemical mechanical polishing process, which greatly complicates the overall process, and therefore is expensive to implement.

The present invention has been proposed to solve the above-mentioned problems, and in order to make the copper-based double damascene structure high in resistance and planarization, a copper-based metallization film and tantalum or tantalum Within integrated circuits that can be used to fabricate copper-based double damascene structures to prevent unwanted dishing of copper-based double damascene structures by high chemical mechanical polishing selectivity between nitride-based barrier films. Its purpose is to provide a method of manufacturing a metal interconnect structure.

Another object of the present invention is a metal in an integrated circuit that can be used in a method of manufacturing a copper-based double damascene structure to prevent short circuits and bridges due to the presence of residues of the barrier film remaining on the front surface of the insulating film after a chemical mechanical polishing process. It is to provide a method for manufacturing the interconnect structure.

1A-1D are views used to describe the processes involved in a conventional dual damascene process for producing a dual damascene structure comprising a metal interconnect structure and a metal plug;

2A-2F and 3 are used to illustrate the steps involved in a semiconductor fabrication process using the method of the invention to fabricate a copper-based dual damascene structure; And

4A-4F are diagrams used to illustrate the steps involved in a semiconductor fabrication process using the method of the present invention to fabricate a copper-based dual damascene structure.

* Explanation of symbols for the main parts of the drawings

10, 20, 40: semiconductor substrate 12, 22, 42: insulating film

14a, 26, 46: trench 14b, 24, 44: contact opening

16, 48: barrier film 18a, 34a, 50a: metal interconnect structure

18b, 34b, 50b: metal plug 19: dish shape

28: first barrier film 30: second barrier film

32: photoresist film 34, 50: metallization film

According to the present invention for achieving the above object, a method for manufacturing a metal interconnect structure in an integrated circuit is provided. The process of the invention is particularly useful for the production of copper-based dual damascene structures comprising two integrated metallized parts, namely metal interconnect structures and metal plugs. Generally speaking, however, the present invention is limited to methods of fabricating metal interconnect structures in integrated circuits.

The method of the present invention, when broadly defined as a method of manufacturing a metal interconnect structure, includes the following steps. That is, forming an insulating film on the entire surface of the semiconductor substrate; Forming a trench in the insulating film; Forming a first barrier film over all of the exposed surfaces of the substrate and insulating film without completely filling the trench; Forming a second barrier film over all of the exposed surface of the first barrier film without completely filling the trench; Removing the first and second barrier layers directly covered on the insulating layer over the trench; Depositing a metal on the entire surface of the insulating film to form a metallization film completely filling the trench; And removing a portion of the metallization film covered on the surface of the insulating film so that the metallization film deposited in the remaining portion of the trench is provided in a desired metal interconnect structure.

As mentioned above, the present invention is broadly defined as a method of manufacturing metal interconnect structures in integrated circuits. In practice, however, the method of the present invention aims at eliminating the drawbacks of the prior art mentioned in the background of the present invention, in particular copper- comprising two integrated metallized parts, namely metal interconnect structures and metal plugs. It is useful in the process for producing a based double damascene structure.

(Example 1)

2A-2F and 3 are diagrams used to illustrate the steps involved in a semiconductor fabrication process using the method of the present invention to fabricate a copper-based dual damascene structure in an integrated circuit.

First, referring to FIG. 2A, in an initial step, the semiconductor substrate 20 is prepared. The substrate 20 is already formed with a transistor element (not shown) or a lower level (not shown) of a metal interconnect structure. The metal interconnect structure by the manufacturing method according to the invention is used as the base level of the metal interconnect structure in the former case and at the subsequent higher level of the metal interconnect structure in the latter case. Generally speaking, the method of the present invention can be used to form any level of metal interconnect structure for a multilayer interconnect structure.

Next, an insulating material such as silicon dioxide (SiO 2), borophophosilicate glass (BPSG), or phosphosilicate glass (PSG) is used through chemical vapor deposition (CVD) on the entire upper surface of the substrate 20. Thus, the insulating film 22 is formed to have a thickness of 7000 kPa to 10000 kPa. This insulating film 22 is then planarized, for example, by an etch-back process or chemical mechanical polishing.

Subsequently, a trench 26 and a contact opening (or via opening) 24 are sequentially formed in the insulating film 22. In this case, the contact opening 24 is formed to have a smaller width than the trench 26. For example, the trench 26 is first subjected to a photolithography process for masking all insulating films except where the trench 26 is formed, and then an isotropic etching process is performed on the unmasked portions of the insulating film. It is performed until a predetermined end point in the insulating film 22 is reached, or for a predetermined time period to reach a predetermined depth in the insulating film 22. The contact opening 24 is subjected to the same photolithography process until the underlying region of the transistor device (not shown) or the subsequent lower level of the metal interconnect structure (not shown) is exposed in the substrate 20. And isotropic etching processes.

Referring to FIG. 2B, in a subsequent step, tantalum (Ta) or tantalum nitride (TaN) in a substantially uniform thickness of 300 kPa to 500 kPa through a CVD process on the surface of all exposed substrates 20 and the insulating film 22. The first barrier layer 28 is deposited using a heat resistant metal such as). Next, a second barrier film 30 is formed over the entire exposed surface of the first barrier film 28 in a similar manner, wherein nitride of the heat resistant metal used to form the first barrier film 28 is formed. It is formed using a metal except for. For example, when the first barrier layer 28 is formed of tantalum (Ta), the second barrier layer 30 is formed of tantalum nitride (TaN). On the other hand, when the first barrier layer 28 is formed of titanium (Ti), the second barrier layer 30 is formed of titanium nitride (TiN). The combination film of Ta / TaN as a barrier film can increase the adhesion between the insulating film 22 and the copper deposited in the contact opening 24 and the trench 26 in a subsequent process, and the deposited copper is a component adjacent thereto. Can be prevented from spreading.

2C or 3, the first and second barrier films 26 and 28 directly covered on the insulating film except for the trench are removed. As shown in FIG. 2C, the photoresist layer 32 is formed where the trench 26 is formed such that the second barrier layer 30 covered over the entire top surface of the insulating layer 22 except for the trench 26 is exposed. It is applied selectively. Next, an etching process, preferably an isotropic etching process, is performed on the wafer using the photoresist film 32 as a mask, wherein the second except the trench 26 is exposed until the upper surface of the insulating film 22 is exposed. The unmasked portions of the barrier layer 30 and the first barrier layer 28 are both etched. Alternatively, as shown in FIG. 3, a chemical mechanical polishing process is performed on the first and second barrier films 28 and 30 covered on the entire top surface of the insulating film 22 except for the trench 26.

Removal of the unmasked portions of the first and second barrier films 28, 30 covered on the top surface of the insulating film 22 except for the trench 26 is a dishing defect of copper deposited in the subsequent trench 26. It is a feature of the invention that it can be removed. This is because the subsequent chemical mechanical polishing process only acts on the copper in the trench 26 but not on the portions of the first and second barrier films 28 and 30 that are currently removed, as in the prior art.

Referring to FIG. 2D, the first barrier film 28 remaining in the trench 26 and the contact opening 24 is indicated here by reference numeral 28a, while the remaining portion of the second barrier film 30 is It is indicated by reference numeral 30a. As a subsequent step, the photoresist film 32 is completely removed through, for example, an oxygen plasma process.

In FIG. 2E, the entire upper surface of the wafer until a predetermined thickness is formed on the top surface of the insulating film 22 to form a metallization film 34 which completely fills the contact opening 24 and the trench 26. On metal is preferably copper deposited. The metallization layer 34 may be formed through, for example, a CVD process, a physical vapor deposition (PVD) process, or an electro-chemical deposition (ECD) process. If ECD is used, it is required to first form a PVD seed film (not shown) on the entire surface of the wafer.

Referring to FIG. 2F, a selective removal process, such as a chemical mechanical polishing process, is performed on the metallization film 34 until the upper surface of the insulating film 22 is exposed. Residues of metallization film 34 in contact opening 24 are provided as metal plugs 34b, while residues of metallization film 34 in trenches 26 are provided as metal interconnect structures 34a. do. The combination of the metal interconnect structure 34a and the metal plug 34b constitutes a dual damascene structure, and the metal interconnect structure 34a passes through the metal plug 34b to the lower transistor element (not shown in the figure). Or lower level of a subsequent metal interconnect structure (not shown in the figure) formed in the semiconductor substrate.

(Example 2)

4A-4F are diagrams used to illustrate the steps involved in a semiconductor fabrication process using the method of the present invention to fabricate a copper-based dual damascene structure in an integrated circuit.

Referring to FIG. 4A, in an initial step, the semiconductor substrate 40 is prepared. The substrate 40 is already formed with a transistor element (not shown) or a lower level (not shown) of a metal interconnect structure. The metal interconnect structure by the manufacturing method according to the invention acts as the base level of the metal interconnect structure in the former case and at the subsequent higher level of the metal interconnect structure in the latter case. Generally speaking, the method of the present invention can be used to form any level of metal interconnect structure for a multilayer interconnect structure.

Next, silicon dioxide (SiO 2), borophophosilicate glass (BPSG), or phosphosilicate glass (PSG) through chemical vapor deposition (CVD) to have a thickness of 7000 kPa to 10000 kPa on the entire upper surface of the substrate 40. An insulating film 42 using an insulating material such as) is formed. Next, this insulating film 42 is planarized, for example, by an etch-back process or chemical mechanical polishing.

Subsequently, a trench 46 and a contact opening (or via opening) 44 are sequentially formed in the insulating film 42. In this case, the contact opening 44 is formed to have a smaller width than the trench 46. The trench 46 may be, for example, first subjected to a photolithography process for masking all the insulating films 42 except where the trench 46 is formed, and then an isotropic etching process on the unmasked portion of the insulating film. This is performed until it reaches a predetermined end point in the insulating film 42 or for a predetermined time period to reach a predetermined depth in the insulating film 42.

The contact opening 44 is the same photolithography until the contact region of the underlying transistor element (not shown) or the subsequent lower level of the metal interconnect structure (not shown) in the substrate 40 is exposed. It can be formed by performing a process and an isotropic etching process.

Referring to FIG. 4B, in a subsequent step, tantalum (Ta) or tantalum nitride (TaN) has a substantially uniform thickness of 300 kPa to 500 kPa through a CVD process on the surfaces of all exposed substrates 40 and the insulating film 42. The barrier film 48 is deposited using a heat resistant metal such as). The combination film of Ta / TaN as a barrier film can increase the adhesion between the insulating film 42 and the copper deposited in the contact opening 44 and the trench 46 in a subsequent process, and the deposited copper is a component adjacent thereto. Can be prevented from spreading.

In FIG. 4C, the entire upper surface of the wafer is formed to a predetermined thickness on the top surface of the insulating film 42 to form a metallization film 34 that completely fills the contact opening 44 and the trench 46. Metal is preferably copper deposited. The metallization layer 50 may be formed through, for example, a physical vapor deposition (PVD) process such as a CVD process or sputtering, or an electro-chemical deposition (ECD) process. If ECD is used, it is required to first form a PVD seed film (not shown) on the entire surface of the wafer.

Referring to FIG. 4D, a selective removal process, such as a chemical mechanical polishing process, is performed on the metallization film 50 until the upper surface of the insulating film 42 is exposed. Residue of metallization 50 in contact opening 44 is provided as metal plug 34b, while residue of metallization 50 in trench 46 is provided as metal interconnect structure 50a. do. The combination of the metal interconnect structure 50a and the metal plug 50b constitutes a dual damascene structure, and the metal interconnect structure 50a passes through the metal plug 50b to the lower transistor element (not shown in the figure). Or lower level of a subsequent metal interconnect structure (not shown in the figure) formed in the semiconductor substrate 40.

In FIG. 4E, the barrier film 48 directly covered on the insulating film except for the trench is removed. First, a photoresist film 52 is selectively applied where the trench 46 is formed so that the barrier film 48 covered over the entire top surface of the insulating film 42 except for the trench 46 is exposed.

Referring to FIG. 4F, using the photoresist film 52 as a mask, an etching process, preferably an isotropic etching process, is performed on a wafer, and the trench 46 is exposed until the upper surface of the insulating film 42 is exposed. Is performed to etch all the unmasked portions of the barrier layer 48 except for. The unmasked portion of the barrier film 48 except for the trench 46 may be subjected to other processes, such as an electric beam (EB) process, a strip process or a clean process (CLN). Can be removed using. Residues of barrier film 48 in trench 46 and contact opening 44 are indicated here by reference numeral 48a. In a subsequent step, the photoresist film 52 is completely removed by, for example, an oxygen plasma process.

It is seen that removing the unmasked portion of the barrier film 48 covered on the top surface of the insulating film 42 except for the trench 46 can eliminate dishing defects of copper deposited in the subsequent trench 46. It is a feature of the invention. This is because the subsequent chemical mechanical polishing process only acts on the copper in the trench 46 but not on the barrier film 48 currently removed, as in the prior art.

First, the method of the present invention can (1) eliminate defects in which the upper surface of the dual damascene structure, which has been generated in the prior art dual damascene structure, is formed in a dish shape.

(2) The method of the present invention can eliminate short circuit and bridging defects due to the residue of the barrier film remaining on the insulating film which has been generated in the dual damascene structure manufactured by the prior art.

(3) The method of the present invention can further simplify the complexity of the process by not performing repeated reworking of the chemical mechanical polishing process as compared to the prior art, and therefore easier and more cost effective to implement than the prior art. Can be.

Although the present invention has been described as a preferred embodiment, the present invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements, procedures, and the scope of the appended claims should be accorded the widest interpretation so as to encompass all such modifications, similar arrangements and procedures.

Claims (34)

Forming an insulating film on the entire surface of the semiconductor substrate; Forming a trench in the insulating film; Forming a first barrier film over the entire exposed surface of the insulating film without completely filling the trench; Forming a second barrier film over the entire exposed surface of the first barrier film without completely filling the trench; Removing the first and second barrier films covered over the entire insulating film except for the trench; Depositing a metal on the entire surface of the insulating film to form a metallization film completely filling the trench; And And performing a selective removal process to remove the metallization film covered on the surface of the insulating film, wherein the remaining portion deposited in the trench serves as a desired metal interconnect structure. The method of claim 1, And the insulating film is a silicon dioxide film. The method of claim 1, And the insulating film is a BPSG film. The method of claim 1, And the insulating film is a PSG film. The method of claim 1, The forming of the trench may include performing a photolithographic process for masking all of the insulating layers except where the trench is formed; And Performing an isotropic etching process on the unmasked portion of the insulating film until a predetermined end point in the insulating film is reached. The method of claim 1, The forming of the trench may include performing a photolithography process to mask all of the insulating layers except where the trench is formed; And Performing an isotropic etching process for a predetermined time period such that etching to reach a predetermined depth in the insulating film is performed on the unmasked portion of the insulating film. The method of claim 1, Forming a contact opening under the trench; This step includes performing a photolithography process to mask all portions of the insulating film except where the trench is formed; And And performing an isotropic etch process on the unmasked portion of the insulating film until the surface of the semiconductor substrate is exposed. The method of claim 1, And the first barrier film is formed of a heat resistant metal. The method of claim 1, And the first barrier film is formed of tantalum (Ta). The method of claim 1, And the first barrier film is formed of titanium (Ti). The method of claim 1, And the second barrier film is formed of a heat resistant metal. The method of claim 1, And the second barrier film is formed of tantalum nitride (TaN). The method of claim 1, And wherein said second barrier film is formed of titanium nitride (TiN). The method of claim 1, And the metal deposited in the trench is copper (Cu). The method of claim 1, And wherein if the metal deposited in the trench is copper (Cu) and the first barrier film is formed of tantalum (Ta), the second barrier film is formed of tantalum nitride (TaN). The method of claim 1, Wherein said selective removal process is a chemical mechanical polishing (CMP) process. Forming an insulating film on the entire surface of the semiconductor substrate; Forming a trench in the insulating film; Forming a contact opening in the lower portion of the trench to expose a selected area of the substrate below the insulating layer; Forming a first barrier film over the exposed surfaces of the substrate and the insulating film without completely filling the contact openings and the trenches; Forming a second barrier film over the entire exposed surface of the first barrier film without completely filling the contact openings and trenches; Removing the first and second barrier films covered over the entire insulating film except for the trench; Depositing copper over the entire surface of the insulating film to form a copper-based metallization film that completely fills the contact openings and trenches; And Performing a selective removal process to remove the copper-based metallization film covered on the surface of the insulating film, whereby the remaining portions deposited in the contact opening act as metal plugs and are deposited in the trenches. To produce a copper-based metal interconnect structure in an integrated circuit such that the remaining portion acts as a desired metal interconnect structure. The method of claim 17, And wherein the insulating film is a silicon dioxide film and fabricates a copper-based metal interconnect structure in an integrated circuit. The method of claim 17, Wherein the insulating film is a BPSG film and fabricates a copper-based metal interconnect structure in an integrated circuit. The method of claim 17, Wherein the insulating film is a PSG film and fabricates a copper-based metal interconnect structure. The method of claim 17, The forming of the trench may include performing a photolithographic process for masking all of the insulating layer except where the trench is formed; And Performing an isotropic etch process on the unmasked portion of the insulating film until a predetermined depth in the insulating film is reached. The method of claim 17, And the first barrier film is formed of a heat resistant metal. The method of claim 17, And wherein said first barrier film is formed of tantalum (Ta). The method of claim 17, And the second barrier film is formed of a heat resistant metal. The method of claim 17, And wherein said second barrier film is formed of tantalum nitride (TaN). The method of claim 17, Wherein said selective removal process is a chemical mechanical polishing (CMP) process. Forming an insulating film on the entire surface of the semiconductor substrate; Forming a trench in the insulating film; Forming a barrier film over the entire exposed surface of the insulating film without completely filling the trench; Depositing a metal over the insulating film and the barrier film to form a metallization film completely filling the trench; Performing a selective removal process to remove the metallization layer covered on the surface of the barrier layer such that the remaining portions deposited in the trench serve as a desired metal interconnect structure; And Removing the barrier film covered over the entire insulating film. The method of claim 27, And wherein said optional removal process is a CMP process. The method of claim 27, And the barrier film is formed of Ta / TaN. The method of claim 27, And the barrier film is formed of Ti / TiN. The method of claim 27, The method for removing the barrier film covered on the entire surface of the insulating film, Selectively applying a photoresist film where the trench is formed while exposing the entire barrier film covered on the top surface of the insulating film except for the trench; Removing the barrier film covering the entire surface of the insulating film by using the photoresist film as a mask; And Removing the photoresist film. The method of claim 31, wherein The removal process may comprise an etching process, a strip process or a clean process. The method of claim 31, wherein Wherein said removing process comprises an electric beam process. The method of claim 31, wherein Wherein said removing process comprises a stripping process and a cleaning process or cleaning process.