KR20030056391A - Method for forming copper line in semiconductor device - Google Patents
Method for forming copper line in semiconductor device Download PDFInfo
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- KR20030056391A KR20030056391A KR1020010086595A KR20010086595A KR20030056391A KR 20030056391 A KR20030056391 A KR 20030056391A KR 1020010086595 A KR1020010086595 A KR 1020010086595A KR 20010086595 A KR20010086595 A KR 20010086595A KR 20030056391 A KR20030056391 A KR 20030056391A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 보다 상세하게는 구리 전해도금 공정의 효율성 및 안정성을 높일 수 있는 반도체 소자의 구리배선 형성방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly to a method for forming a copper wiring of a semiconductor device that can improve the efficiency and stability of the copper electroplating process.
일반적으로, 반도체 소자의 구리배선 형성방법으로는 전기적 특성이 우수한 듀얼 다마신(dual damascene) 공정을 주로 사용한다. 이러한 듀얼 다마신 공정에의한 반도체 소자의 구리배선은 다음과 같은 일련의 단계를 거쳐 형성한다.In general, a dual damascene process having excellent electrical characteristics is mainly used as a method of forming a copper wiring of a semiconductor device. The copper wiring of the semiconductor device by the dual damascene process is formed through a series of steps as follows.
종래 기술에 따른 반도체 소자의 구리배선 형성방법은, 먼저 하부 구리배선을 형성한 다음, 상기 하부 구리배선 상부에 층간절연층을 증착한다. 그 다음, 상기 층간절연층을 선택적으로 제거하여 비아홀과 트렌치를 형성한 다음 그 내표면에 배리어 금속층(barrier metal layer)을 증착한다. 이어서, 상기 비아홀과 트렌치를 구리로 매립하고 평탄화 및 세정공정을 거친 다음, 캡핑층(capping layer)을 증착하여 반도체 소자의 구리배선을 완성한다.In the method of forming a copper wiring of a semiconductor device according to the related art, first, a lower copper wiring is formed, and then an interlayer insulating layer is deposited on the lower copper wiring. Next, the interlayer insulating layer is selectively removed to form via holes and trenches, and then a barrier metal layer is deposited on the inner surface thereof. Subsequently, the via hole and the trench are filled with copper, planarized and cleaned, and then a capping layer is deposited to complete copper wiring of the semiconductor device.
그러나, 종래 기술에 따른 반도체 소자의 구리배선 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the copper wiring forming method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서 구리매립 공정은 크게 두 단계로 나뉘는바, 구리 결정핵(seed)층 증착 및 구리 전해도금 공정이 그것이다. 특히, 구리 결정핵층의 증착 상태가 불량한 경우에는 후속 전해도금 단계에 악영향을 미쳐 소자의 불량률이 높아진다는 문제점이 있다.In the prior art, the copper embedding process is largely divided into two stages: copper seed layer deposition and copper electroplating. In particular, when the deposition state of the copper crystal nucleus layer is poor, there is a problem that the defect rate of the device is increased by adversely affecting the subsequent electroplating step.
또한, 하부 구리배선과 구리 플러그의 경계에 배리어 금속층이 존재하는데, 이러한 배리어 금속층의 존재로 말미암아 하부 구리배선과 구리 플러그간의 상호 접착력과 매립특성이 열악해져서 구리 플러그 내부에 보이드(void)가 발생하게 되어 소자의 불량률이 높아진다는 문제점이 있다.In addition, a barrier metal layer exists at the boundary between the lower copper wiring and the copper plug, and the presence of the barrier metal layer causes poor adhesion between the lower copper wiring and the copper plug and embedding characteristics, thereby causing voids to occur inside the copper plug. There is a problem that the defective rate of the device is increased.
이에, 본 발명은 상기 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 구리 결정핵층 층착후에 은(Ag)의 치환도금 방법으로 구리결정핵층을 보강하여 구리 전해도금 공정의 효율성 및 안정성을 높이는 반도체 소자의 구리배선 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the problems of the prior art, the object of the present invention is to reinforce the copper crystal core layer by a substitution plating method of silver (Ag) after the copper crystal core layer deposition and copper electroplating process efficiency and It is to provide a method for forming copper wiring of a semiconductor device to increase the stability.
도 1 내지 도 6은 본 발명에 따른 반도체 소자의 구리배선 형성방법을 도시한 공정별 단면도.1 to 6 are cross-sectional views for each process illustrating a method for forming copper wirings of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10: 하부 구리배선20: 층간절연층10: lower copper wiring 20: interlayer insulating layer
30: 비아홀40: 트렌치30: via hole 40: trench
50: 배리어 금속층60: 구리 결정핵(seed)층50: barrier metal layer 60: copper seed layer
70: 구리배선80: 캡핑막70: copper wiring 80: capping film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리배선 형성방법은, 반도체 기판상에 하부 구리배선과 층간절연층을 형성한 다음, 상기 층간절연층에 비아홀과 트렌치를 형성하는 단계; 상기 비아홀 및 트렌치 내표면을 포함한 상기 층간절연층 전면상에 배리어 금속층을 형성하는 단계; 상기 배리어 금속층 전면상에 구리 결정핵층을 증착한 다음, 상기 구리 결정핵층을 은(Ag) 치환 도금하는 단계; 상기 비아홀 및 트렌치를 매립하는 구리층을 형성하는 단계; 상기 구리층을 일부제거하여 구리배선을 형성하는 단계; 및 상기 구리배선을 포함한 층간절연층상에 캡핑층을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: forming a lower copper wiring and an interlayer insulating layer on a semiconductor substrate, and then forming via holes and trenches in the interlayer insulating layer; Forming a barrier metal layer on an entire surface of the interlayer insulating layer including the via hole and an inner surface of the trench; Depositing a copper seed layer on the entire barrier metal layer, and then plating silver (Ag) substitution on the copper seed layer; Forming a copper layer filling the via hole and the trench; Removing a portion of the copper layer to form a copper wiring; And forming a capping layer on the interlayer insulating layer including the copper wiring.
이하, 본 발명에 따른 반도체 소자의 구리배선 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming copper wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도6은 본 발명에 따른 반도체 소자의 구리배선 형성방법을 도시한 공정별 단면도이다.1 to 6 are cross-sectional views illustrating processes of forming copper wirings of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 구리배선 형성방법은, 도 1에 도시된 바와 같이, 반도체 기판(미도시) 상에 하부 구리배선(10)을 형성하고, 상기 하부 구리배선(10) 상부에 층간절연층(20)을 증착한다. 상기 층간절연층(20)으로는 실리콘산화물 또는 저유전상수 절연막 등이 있다. 이어서, 상기 층간절연층(20)을 선택적으로 제거하여 트렌치(40) 및 비아홀(30)을 형성한다.In the method of forming a copper wiring of a semiconductor device according to the present invention, as shown in FIG. 1, a lower copper wiring 10 is formed on a semiconductor substrate (not shown), and interlayer insulation is formed on the lower copper wiring 10. Deposit layer 20. The interlayer insulating layer 20 may be a silicon oxide or a low dielectric constant insulating film. Subsequently, the interlayer insulating layer 20 is selectively removed to form the trench 40 and the via hole 30.
이어서, 도 2에 도시된 바와 같이, 고주파 스퍼터링 세정 또는 수소환원 세정공정으로 상기 하부 구리배선(10) 표면을 세정한 다음, 상기 트렌치(40) 및 비아홀(30) 내표면을 비롯한 상기 층간절연막(20) 전면상에 배리어 금속층(50)을 이온화 물리기상증착법(ionized PVD)으로 약 100 내지 700Å 두께로 형성한다. 이때, 상기 배리어 금속층(50)으로는 탄탈륨(Ta)이나 탄탈륨질화물(TaN) 등을 사용하여 형성한다.Next, as shown in FIG. 2, the surface of the lower copper wiring 10 is cleaned by a high frequency sputtering cleaning or a hydrogen reduction cleaning process, and then the interlayer insulating film including the inner surface of the trench 40 and the via hole 30 is formed. 20) The barrier metal layer 50 is formed on the entire surface to about 100 to 700 Å thickness by ionized physical vapor deposition (ionized PVD). In this case, the barrier metal layer 50 is formed using tantalum (Ta), tantalum nitride (TaN), or the like.
그다음, 도 3에 도시된 바와 같이, 상기 배리어 금속층(50) 전면상에 이온화 물리기상증착법(ionized PVD)으로 구리 결정핵층(60:Cu seed layer)을 약 500 내지 1,500Å 정도의 두께로 증착한다. 그런다음, 상기 구리 결정핵층(60) 상에 은(Ag)을 치환 도금한다. 상기 은(Ag) 치환 도금은 상기 반도체 기판(미도시)을 질산은(AgNO3) 용액에 넣으면, 상기 구리 결정핵층(60)에 은(Ag)이 자발적으로 치환도금된다. 이에 대한 반응식은 다음과 같다.Next, as shown in FIG. 3, a copper seed layer 60 is deposited to a thickness of about 500 to 1,500 Å on an entire surface of the barrier metal layer 50 by ionized PVD. . Thereafter, silver (Ag) is plated on the copper crystal nucleus layer 60. In the silver (Ag) substitution plating, silver (Ag) is spontaneously substituted and plated on the copper crystal core layer 60 when the semiconductor substrate (not shown) is placed in a silver nitrate (AgNO 3 ) solution. The reaction scheme is as follows.
2Ag++ Cu -> 2Ag + Cu2+ 2Ag + + Cu-> 2Ag + Cu 2+
상기 반응이 기전력은 약 0.462 볼트(V)로서 자발적으로 진행된다. 상기 은 도금층의 두께를 약 100 내지 700Å 정도로 유지한 후, 초순수(deionized water)로써 세정한다. 상기 세정공정에 의하여 상기 구리 결정핵층(60)의 표면결합이 감소되며, 결정핵층의 두께가 균일해진다. 또한, 후술하는 구리 전해도금층(70)과 배리어 금속층(50)과의 접착력이 향상된다.The reaction proceeds spontaneously with an electromotive force of about 0.462 volts (V). The thickness of the silver plating layer is maintained at about 100 to 700 kPa, followed by washing with deionized water. The cleaning process reduces the surface bonding of the copper crystal nucleus layer 60 and makes the thickness of the crystal nucleus layer uniform. In addition, the adhesion between the copper electroplating layer 70 and the barrier metal layer 50 described later is improved.
이어서, 도 4에 도시된 바와 같이, 상기 트렌치(40) 및 비아홀(30)을 충분히매립하도록 상기 층간절연층(20)을 구리로써 매립한 다음, 후속 열처리 공정을 진행한다. 이때, 구리 매립방법으로는 매립 특성 및 물성이 우수한 전해 도금방법이 바람직하다. 한편, 후속 열처리 공정은 상기 구리층(70)의 결정립 크기를 증가시키고 안정화하기 위함이다. 상기 열처리 공정을 급속열처리 방식(RTP)을 이용하는 경우에는 약 150 내지 400℃에서 약 2분 이내에 진행한다.Subsequently, as shown in FIG. 4, the interlayer insulating layer 20 is filled with copper to sufficiently fill the trench 40 and the via hole 30, and then a subsequent heat treatment process is performed. In this case, as the copper embedding method, an electrolytic plating method excellent in embedding characteristics and physical properties is preferable. On the other hand, the subsequent heat treatment process is to increase and stabilize the grain size of the copper layer 70. In the case of using the rapid heat treatment method (RTP), the heat treatment process is performed at about 150 to 400 ° C. within about 2 minutes.
그다음, 도 5에 도시된 바와 같이, CMP 공정으로 상기 구리층(70)을 연마하여 구리 플러그 및 구리 배선을 제외한 나머지 표면부분을 제거한다. 상기 CMP 공정 이후에는 표면 세정공정을 진행하여 CMP 공정에 의하여 유발된 표면결함 및 불순물 입자 등을 제거한다.Next, as shown in FIG. 5, the copper layer 70 is polished by a CMP process to remove the remaining surface portions except for the copper plug and the copper wiring. After the CMP process, a surface cleaning process is performed to remove surface defects and impurity particles caused by the CMP process.
이어서, 도 6에 도시된 바와 같이, 상기 구리배선(70a) 표면에 생성된 자연산화막을 환원시킨 후, 공기중에 노출시키지 않은 채로 상기 구리배선(70a)을 비롯한 상기 층간절연층(20) 전면상에 구리층 캡핑층(80)을 실리콘질화물 등으로 플라즈마 화학기상증착법(PECVD)으로 형성한다. 상기 캡핑층(80)은 상기 구리배선(70a) 내의 구리원자가 상부의 층간절연층(미도시)으로 확산하는 것을 억제하는 역할을 담당한다. 구리원자의 확산을 억제함으로써 배선간의 누설전류 발생을 방지할 수 있는 것이다.Subsequently, as shown in FIG. 6, after the natural oxide film formed on the surface of the copper wiring 70a is reduced, the entire surface of the interlayer insulating layer 20 including the copper wiring 70a is exposed without being exposed to air. The copper layer capping layer 80 is formed of silicon nitride or the like by plasma chemical vapor deposition (PECVD). The capping layer 80 plays a role of suppressing diffusion of copper atoms in the copper wiring 70a into an upper interlayer insulating layer (not shown). By suppressing diffusion of copper atoms, leakage current between wirings can be prevented.
이후에, 예정된 후속 공정을 진행하여 듀얼 다마신 공정에 의한 최종적인 반도체 소자의 구리배선을 완성한다.Thereafter, a predetermined subsequent process is performed to complete the final copper wiring of the semiconductor device by the dual damascene process.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as obvious to those skilled in the art without departing from the spirit and principles of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 구리배선 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the copper wiring forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 은(Ag)의 치환 도금방법에 의하여 구리 결정핵층을 보강함으로써 구리 결정핵층의 표면 결함 감소, 두께의 균일성 증가, 구리 전해도금층의 매립특성의 향상, 구리 전해도금층과 배리어 금속층과의 접착력 향상 등의 효과가 있다.In the present invention, by reinforcing the copper crystal core layer by a substitutional plating method of silver (Ag), the surface defect of the copper crystal core layer is reduced, the thickness uniformity is increased, the embedding characteristics of the copper electroplating layer are improved, the copper electroplating layer and the barrier metal layer It has the effect of improving the adhesive strength with.
또한, 스텝커버리지가 양호해지므로 하이 테크놀로지(high technology)의 비아홀 매립에 유리하며, 구리배선의 신뢰성 및 전해도금 공정의 효율성 및 안정성을 높일 수 있는 효과가 있다.In addition, since the step coverage is good, it is advantageous to fill the via hole of high technology, and there is an effect of increasing the reliability and efficiency of the electroplating process and the reliability of the copper wiring.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030095005A (en) * | 2002-06-11 | 2003-12-18 | 김재정 | Fabricating Method of Matal Film for Semiconductor Interconnection |
| KR100713328B1 (en) * | 2005-12-23 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device using dual damascene process |
| US8927433B2 (en) | 2009-12-18 | 2015-01-06 | Electronics And Telecommunications Research Institute | Conductive via hole and method for forming conductive via hole |
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| CA2239838C (en) * | 1998-06-08 | 2001-08-07 | Yuan Mei Corp. | A water amount controlling switch structure of water injection gun |
| JP3187011B2 (en) * | 1998-08-31 | 2001-07-11 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP2000156406A (en) * | 1998-11-19 | 2000-06-06 | Sony Corp | Semiconductor device and its manufacture |
| US6440849B1 (en) * | 1999-10-18 | 2002-08-27 | Agere Systems Guardian Corp. | Microstructure control of copper interconnects |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030095005A (en) * | 2002-06-11 | 2003-12-18 | 김재정 | Fabricating Method of Matal Film for Semiconductor Interconnection |
| KR100713328B1 (en) * | 2005-12-23 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device using dual damascene process |
| US8927433B2 (en) | 2009-12-18 | 2015-01-06 | Electronics And Telecommunications Research Institute | Conductive via hole and method for forming conductive via hole |
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