KR19990049050A - Wiring Formation Method of Semiconductor Device - Google Patents
Wiring Formation Method of Semiconductor Device Download PDFInfo
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- KR19990049050A KR19990049050A KR1019970067887A KR19970067887A KR19990049050A KR 19990049050 A KR19990049050 A KR 19990049050A KR 1019970067887 A KR1019970067887 A KR 1019970067887A KR 19970067887 A KR19970067887 A KR 19970067887A KR 19990049050 A KR19990049050 A KR 19990049050A
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- silicide layer
- wiring
- semiconductor device
- copper film
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
본 발명은 실리사이드층상에 무전해 도금 구리막을 형성하기 이전에 상기 실리사이드층상에 형성되는 산화물을 제거하여 실리사이드층과 무전해 도금 구리막과의 접착특성을 개선시키는데 적당한 반도체소자의 배선형성방법에 관한 것으로써, 실리사이드층상에 무전해 도금 구리막을 배선으로 사용하는 반도체소자 배선형성방법에 있어서, 상기 실리사이드층을 형성한 후, Pd-HF혼합 용액을 사용하여 실리사이드층상의 산화물을 제거함과 동시에 Pd버퍼층을 형성하는 기판 전처리를 실시한 후, 상기 무전해 도금 구리막을 형성하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device suitable for improving adhesion characteristics of a silicide layer and an electroless plating copper film by removing an oxide formed on the silicide layer before forming an electroless plating copper film on the silicide layer. In the method for forming a semiconductor device wiring using an electroless plated copper film on a silicide layer as a wiring, after the silicide layer is formed, an oxide on the silicide layer is removed using a Pd-HF mixed solution and a Pd buffer layer is formed at the same time. After the substrate pretreatment is performed, the electroless plating copper film is formed.
Description
본 발명은 반도체소자의 배선에 관한 것으로 특히, 상부배선 재료로 사용하는 무전해 Cu막과, 그 하부막의 부착특성을 개선시키는데 적당한 반도체소자의 배선형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring of semiconductor devices, and in particular, to an electroless Cu film used as an upper wiring material and a wiring forming method of a semiconductor device suitable for improving adhesion characteristics of the lower film.
일반적으로 상부배선의 재료로 알루미늄보다는 구리를 주로 사용하고 있다. 이는 향후, 1Giga, 4Giga급 디램(DRAM) 또는 스피드를 중요시하는 기타 LOGIC, ASIC회로에서도 마찬가지로 사용되리라 생각된다.In general, copper is mainly used as an upper wiring material rather than aluminum. It is expected that this will be used in 1Giga, 4Gigabit DRAM or other LOGIC and ASIC circuits where speed is important.
이와같이 알루미늄보다 구리를 더 선호하는 이유는 구리가 전기전도도가 매우 낮고, 일렉트로 마이그레이션(Electromigration:전기적 전자이동)에 대한 저항성이 강하기 때문이다.Copper is preferred over aluminum because copper has very low electrical conductivity and strong resistance to electromigration.
이러한 구리(Cu)의 증착방법으로는 CVD(Chemical Vapor Deposition), 스퍼터링(Sputtering)방법, 그리고 무전해 도금법의 여러 가지 방법등이 있다.The copper (Cu) deposition method includes a chemical vapor deposition (CVD), a sputtering method, and an electroless plating method.
이중에서 무전해 도금법은 높은 증착속도, 낮은 실험비용, 증착의 편리성 등의 잇점을 가지고 있으므로 차세대 고밀도 집적회로의 상부배선 재료의 증착방법으로 널리 사용될 것으로 예상된다.Among these, electroless plating has advantages such as high deposition rate, low experiment cost, and convenience of deposition, and is expected to be widely used as a method for depositing the top wiring material of next generation high density integrated circuit.
하지만, 실제 집적회로에서는 구리의 무전해 도금을 실시할 경우, 소오스, 드레인영역에서 하부기판인 베리어 메탈(Barrier metal), 단일 실리사이드층, 또는 이중 실리사이드층과 접하게 된다.In actual integrated circuits, however, when electroless plating of copper is performed, the lower substrate is in contact with a barrier metal, a single silicide layer, or a double silicide layer.
여기서, 이중 실리사이드층은 실리콘기판위에 내열금속과 준귀금속을 나란히 도포한 후 열처리를 통하여 생기는 막의 역전현상을 이용한 실리사이드층을 말한다.Here, the double silicide layer refers to a silicide layer using the inversion phenomenon of the film formed by heat-treating the heat-resistant metal and the quasi-noble metal on the silicon substrate side by side.
상기 이중 실리사이드층은 내열금속에 의한 실리콘 표면의 자연산화막의 환원 제거가 가능하고, 질소분위기에서 열처리할 때 생기는 금속질화물(nitride)이 구리에 대한 확산장벽으로 사용될 수 있다는 잇점을 가지고 있다.The double silicide layer is capable of reducing and removing the native oxide film on the silicon surface by the heat-resistant metal, and has the advantage that metal nitride (nitride) generated during heat treatment in a nitrogen atmosphere can be used as a diffusion barrier for copper.
이하, 종래기술에 따른 반도체소자의 배선형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a wiring forming method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1d는 종래기술에 따른 반도체소자의 배선형성방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method for forming a wiring of a semiconductor device according to the prior art.
도 1a에 도시한 바와같이 활성영역과 필드영역으로 정의된 반도체기판(11)의 필드영역에 필드산화막(12)을 형성한다.As shown in FIG. 1A, the field oxide film 12 is formed in the field region of the semiconductor substrate 11 defined as the active region and the field region.
이후, 활성영역의 반도체기판(11)상의 소정영역에 게이트전극(13)을 형성한 후, 상기 게이트전극(13)을 마스크로 이용한 불순물 이온주입으로 LDD영역(14)을 형성한다.Thereafter, the gate electrode 13 is formed in a predetermined region on the semiconductor substrate 11 in the active region, and then the LDD region 14 is formed by implanting impurity ions using the gate electrode 13 as a mask.
이후, 상기 게이트전극(13)양측면에 절연측벽(15)을 형성하고, 상기 절연측벽(15) 및 게이트전극(13)을 마스크로 이용한 불순물 이온주입으로 상기 게이트전극(13)양측의 반도체기판(11)표면내에 소오스 및 드레인 불순물영역(16,16a)을 형성한다.Thereafter, insulating side walls 15 are formed on both sides of the gate electrode 13, and impurity ions are implanted using the insulating side wall 15 and the gate electrode 13 as a mask to form semiconductor substrates on both sides of the gate electrode 13. 11) Source and drain impurity regions 16 and 16a are formed in the surface.
이후, 도 1b에 도시한 바와같이 상기 게이트전극(13)을 포함한 반도체기판(11)전면에 실리사이드 형성용 금속을 증착한 후 열처리하여 상기 게이트전극(13)의 상부면과, 상기 소오스 및 드레인 불순물영역(16,16a)에 상응하는 반도체기판(11)의 표면에 실리사이드층(17)을 형성한다.Subsequently, as illustrated in FIG. 1B, a silicide forming metal is deposited on the entire surface of the semiconductor substrate 11 including the gate electrode 13, and then heat-treated to form an upper surface of the gate electrode 13, the source and drain impurities. The silicide layer 17 is formed on the surface of the semiconductor substrate 11 corresponding to the regions 16 and 16a.
여기서, 상기 실리사이드층(17)은 단일층 또는 이중층으로 형성할 수 있다.Here, the silicide layer 17 may be formed as a single layer or a double layer.
이후, 도 1c에 도시한 바와같이 미반응된 금속을 제거한 후, 상기 게이트전극(13)을 포함한 반도체기판(11)전면에 절연층(18)을 형성한다.Thereafter, as shown in FIG. 1C, after the unreacted metal is removed, the insulating layer 18 is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 13.
그리고, 상기 소오스 및 드레인 불순물영역(16,16a)의 실리사이드층(17)이 노출되도록 상기 절연층(18)을 선택적으로 제거하여 콘택홀(19)을 형성한다.The insulating layer 18 is selectively removed to expose the silicide layers 17 of the source and drain impurity regions 16 and 16a to form contact holes 19.
이후, 도 1d에 도시한 바와같이 상기 콘택홀(19)을 포함한 반도체기판(11)전면에 무전해 도금 구리(CU)막(20)을 증착한 후, 패터닝한다.Thereafter, as shown in FIG. 1D, an electroless plating copper (CU) film 20 is deposited on the entire surface of the semiconductor substrate 11 including the contact hole 19, and then patterned.
이후의 공정은 통상의 반도체소자 형성공정과 동일하다.The subsequent process is the same as the conventional semiconductor element formation process.
그러나 상기와 같은 종래 반도체소자의 배선형성방법은 다음과 같은 문제점이 있었다.However, the wiring forming method of the conventional semiconductor device as described above has the following problems.
즉, 상기 이중 실리사이드층이나 단일 실리사이드층은 모두 열처리를 거쳐야 되는데 상기 열처리시 실리사이드층의 표면에 산화물이 성장된다.That is, the double silicide layer or the single silicide layer must be subjected to heat treatment, but oxide is grown on the surface of the silicide layer during the heat treatment.
통상, 무전해 도금 Cu막을 단일 또는 이중 실리사이드층상에 도포할 때, Cu막은 하부층(실리사이드층)과 부착특성이 좋지 않은 특성을 가지고 있는데 특히, 하부층이 단일 실리사이드층, 이중 실리사이드층과 같이 열처리를 행하여 이루어질 경우, 산화물에 의해 무전해 도금 구리막과 실리사이드층과의 부착특성이 급격하게 나빠진다.In general, when an electroless plated Cu film is applied on a single or double silicide layer, the Cu film has a poor adhesion property with a lower layer (silicide layer). In particular, the lower layer is heat treated like a single silicide layer or a double silicide layer. In this case, the adhesion between the electroless plated copper film and the silicide layer is sharply degraded by the oxide.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로써, 구리막을 무전해 도금하기 전에 하부층으로 사용되는 실리사이드층 및 베리어 메탈 등을 전처리하고, 구리의 핵생성을 촉진시켜줌으로써, 구리막과 하부층과의 부착특성을 향상시켜 소자의 신뢰성을 개선시키는데 적당한 반도체소자의 배선형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, pretreat the silicide layer and barrier metal used as the lower layer before electroless plating the copper film, by promoting the nucleation of copper, SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring forming method of a semiconductor device suitable for improving the reliability of the device by improving the adhesion characteristics of the device.
도 1a 내지 1d는 종래 반도체소자의 배선형성방법을 설명하기 위한 공정단면도1A to 1D are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.
도 2a 내지 2d는 본 발명의 반도체소자 배선형성방법을 설명하기 위한 공정단면도2A through 2D are cross-sectional views illustrating a method of forming a semiconductor device wiring of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11,21 : 반도체기판 12,22 : 필드산화막11,21: semiconductor substrate 12,22: field oxide film
13,23 : 게이트전극 14,24 : LDD영역13,23 gate electrode 14,24 LDD region
15,25 : 절연측벽 16,26 : 소오스 불순물영역15,25 Insulation side wall 16,26 Source impurity region
16a,26a : 드레인 불순물영역 17,27 : 실리사이드층16a, 26a: drain impurity region 17, 27: silicide layer
18,28 : 절연층 19,29 : 콘택홀18,28 Insulation layer 19,29 Contact hole
30 : Pd버퍼층 20,31 : 무전해 도금 구리막30 Pd buffer layer 20,31 electroless plating copper film
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 배선형성방법은 실리사이드층상에 무전해 도금 구리막을 배선으로 사용하는 반도체소자 배선형성방법에 있어서, 상기 실리사이드층을 형성한 후, Pd-HF혼합 용액을 사용하여 실리사이드층상의 산화물을 제거함과 동시에 Pd버퍼층을 형성하는 기판 전처리를 실시한 후, 상기 무전해 도금 구리막을 형성하는 것을 특징으로 한다.In the semiconductor device wiring formation method of the present invention for achieving the above object, in the semiconductor device wiring formation method using an electroless plated copper film on the silicide layer as the wiring, after forming the silicide layer, Pd-HF mixed solution After performing the substrate pretreatment which removes the oxide on the silicide layer and forms the Pd buffer layer using the above, the electroless plating copper film is formed.
이하, 본 발명에 따른 반도체소자의 배선형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a wiring forming method of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명에 따른 반도체소자의 배선형성방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.
도 2a에 도시한 바와같이, 활성영역과 필드영역으로 정의된 반도체기판(21)의 필드영역에 필드산화막(22)을 형성한다.As shown in FIG. 2A, the field oxide film 22 is formed in the field region of the semiconductor substrate 21 defined by the active region and the field region.
이후, 활성영역의 반도체기판(21)상의 소정영역에 게이트전극(23)을 형성한 후, 상기 게이트전극(23)을 마스크로 이용한 불순물 이온주입으로 LDD영역(24)을 형성한다.Thereafter, the gate electrode 23 is formed in a predetermined region on the semiconductor substrate 21 of the active region, and then the LDD region 24 is formed by implanting impurity ions using the gate electrode 23 as a mask.
이후, 상기 게이트전극(23)양측면에 절연측벽(25)을 형성하고, 상기 절연측벽(24) 및 게이트전극(23)을 마스크로 이용한 불순물 이온주입으로 상기 게이트전극(23)양측의 반도체기판(21)표면내에 소오스 및 드레인 불순물영역(26,26a)을 형성한다.Thereafter, insulating side walls 25 are formed on both sides of the gate electrode 23, and impurity ions are implanted using the insulating side wall 24 and the gate electrode 23 as a mask to form semiconductor substrates on both sides of the gate electrode 23. 21) Source and drain impurity regions 26 and 26a are formed in the surface.
이후, 도 2b에 도시한 바와같이 상기 게이트전극(23)을 포함한 반도체기판(21)전면에 실리사이드 형성용 금속을 증착한 후 열처리하여 상기 게이트전극(23)의 상부면과, 상기 소오스 및 드레인 불순물영역(26,26a)에 상응하는 반도체기판(21)의 표면에 실리사이드층(27)을 형성한다.Thereafter, as illustrated in FIG. 2B, a silicide forming metal is deposited on the entire surface of the semiconductor substrate 21 including the gate electrode 23, and then heat-treated to form an upper surface of the gate electrode 23, the source and drain impurities. The silicide layer 27 is formed on the surface of the semiconductor substrate 21 corresponding to the regions 26 and 26a.
여기서, 상기 실리사이드층(27)은 단일층 또는 이중층으로 형성할 수 있으며 베리어 메탈(barrier metal)로 대신할 수 있다.The silicide layer 27 may be formed as a single layer or a double layer, and may be replaced with a barrier metal.
이후, 도 2c에 도시한 바와같이 미반응된 금속을 제거한 후, 상기 게이트전극(23)을 포함한 반도체기판(21)전면에 절연층(28)을 형성한다.Thereafter, as shown in FIG. 2C, after the unreacted metal is removed, the insulating layer 28 is formed on the entire surface of the semiconductor substrate 21 including the gate electrode 23.
그리고, 상기 소오스 및 드레인 불순물영역(26,25a)의 실리사이드층(26)이 노출되도록 상기 절연층(28)을 선택적으로 제거하여 콘택홀(29)을 형성한다.In addition, the insulating layer 28 is selectively removed to expose the silicide layers 26 of the source and drain impurity regions 26 and 25a to form the contact holes 29.
이어, 상기 Cu막의 무전해 도금을 실시하기 전에 상기 실리사이드층(27)형성을 위한 열처리시 형성되는 산화물을 제거하기 위해 기판 전처리를 실시한다.Subsequently, a substrate pretreatment is performed to remove oxides formed during heat treatment for forming the silicide layer 27 prior to electroless plating of the Cu film.
즉, 도 2d에 도시한 바와같이 Pd-HF혼합 용액을 사용하여 상기 실리사이드층(27)상에 존재하는 산화물을 제거하고, Pd버퍼층(30)을 형성한다.That is, as shown in FIG. 2D, the oxide present on the silicide layer 27 is removed using a Pd-HF mixed solution to form the Pd buffer layer 30.
이때, 상기 Pd버퍼층(30)은 후에 형성될 Cu막의 핵생성을 촉진시키는 매개체 역할을 한다.At this time, the Pd buffer layer 30 serves as a medium for promoting nucleation of the Cu film to be formed later.
여기서, 상기 Pd-HF혼합 용액의 조성비는 다음과 같다.Here, the composition ratio of the Pd-HF mixture solution is as follows.
PdCl2가 0.02g, HCl이 0.1ml, 글레이셜 어세티트 에시드(Glacial acetid acid :빙초산)가 50ml, 그리고 DI 워터(순수한 물)가 25ml, HF가 4ml의 비율로 구성된다.It consists of 0.02g of PdCl 2 , 0.1ml of HCl, 50ml of glacial acetid acid (glacial acetic acid), 25ml of DI water (pure water) and 4ml of HF.
상기 실리사이드층(27)상의 산화물을 제거하기 위한 또다른 방법으로서는 N2플라즈마 처리를 이용할 수 있다.As another method for removing the oxide on the silicide layer 27, an N 2 plasma treatment may be used.
즉, N2플라즈마 처리를 통해 상기 실리사이드층(27)상의 산화물을 제거한다.That is, the oxide on the silicide layer 27 is removed by N 2 plasma treatment.
그리고, Pd-HF혼합 용액을 사용하여 기판 전처리를 실시한다.Subsequently, substrate pretreatment is performed using a Pd-HF mixed solution.
여기서, N2플라즈마 공정시 조건은 다음과 같다.Here, the conditions during the N 2 plasma process are as follows.
RF파워가 100W이고 초기진공상태의 압력이 5×10-6Torr, 수소유량은 50sccm이고, 플라즈마 공정시 압력은 620mTorr, 그리고 플라즈마 처리시간은 60분이다.The RF power is 100W, the initial vacuum pressure is 5 × 10 -6 Torr, the hydrogen flow rate is 50sccm, the pressure during the plasma process is 620mTorr, and the plasma treatment time is 60 minutes.
이상과 같이 기판 전처리를 실시한 후, 상기 콘택홀(29)을 포함한 반도체기판 전면에 무전해 도금 구리(Cu)막(31)을 증착한 후 패터닝하면, 본 발명에 따른 반도체소자의 배선형성 공정이 완료된다.After the substrate pretreatment as described above, after depositing and patterning the electroless plated copper (Cu) film 31 on the entire surface of the semiconductor substrate including the contact hole 29, the wiring forming process of the semiconductor device according to the present invention Is done.
여기서, 상기 무전해 도금 구리막의 조성은 다음과 같다.Here, the composition of the electroless plating copper film is as follows.
CuSo25H2O-10g, HCHO(37%)-60ml, CH3OH-300ml을 NaOH-40g, K Na2H2O8 4H2O-28g과 혼합하여 60℃온도에서 20분간 무전해 도금을 실시한다.CuSo 2 5H 2 O-10g, HCHO (37%)-60ml, CH 3 OH-300ml were mixed with NaOH-40g, K Na 2 H 2 O8 4H 2 O-28g and electroless plating for 20 minutes at 60 ℃. Conduct.
이상 상술한 바와같이 본 발명의 반도체소자의 배선형성방법은 다음과 같은 효과가 있다.As described above, the wiring forming method of the semiconductor device of the present invention has the following effects.
첫째, 베리어 메탈 및 실리사이드층상에 형성된 산화물을 Pd-HF혼합 용액 및 N2플라즈마 처리를 실시하여 제거한 후 무전해 도금 구리막을 형성하기 때문에 상기 구리막과 그 하부의 베리어 메탈 및 실리사이드층과의 접착특성을 향상시킨다.First, since the oxide formed on the barrier metal and the silicide layer is removed by Pd-HF mixed solution and N 2 plasma treatment, an electroless plating copper film is formed, and thus the adhesion property between the copper film and the barrier metal and silicide layer thereunder is formed. To improve.
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| KR1019970067887A KR100252886B1 (en) | 1997-12-11 | 1997-12-11 | Method for forming metal-line of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040007098A (en) * | 2002-07-16 | 2004-01-24 | 주식회사 하이닉스반도체 | Semiconductor device for including copper wiring and method for the same |
| KR100476702B1 (en) * | 2000-12-28 | 2005-03-16 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100476702B1 (en) * | 2000-12-28 | 2005-03-16 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR20040007098A (en) * | 2002-07-16 | 2004-01-24 | 주식회사 하이닉스반도체 | Semiconductor device for including copper wiring and method for the same |
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