KR100429177B1 - Line manufacturing method of semiconductor device - Google Patents
Line manufacturing method of semiconductor device Download PDFInfo
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- KR100429177B1 KR100429177B1 KR1019970029730A KR19970029730A KR100429177B1 KR 100429177 B1 KR100429177 B1 KR 100429177B1 KR 1019970029730 A KR1019970029730 A KR 1019970029730A KR 19970029730 A KR19970029730 A KR 19970029730A KR 100429177 B1 KR100429177 B1 KR 100429177B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000010409 thin film Substances 0.000 claims abstract description 36
- 230000008569 process Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 17
- 238000005240 physical vapour deposition Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 52
- 238000000151 deposition Methods 0.000 description 19
- 230000008021 deposition Effects 0.000 description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000004913 activation Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 238000011534 incubation Methods 0.000 description 3
- 230000009257 reactivity Effects 0.000 description 3
- 239000003054 catalyst Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Computer Hardware Design (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
Description
본 발명은 반도체소자의 금속배선에 관한 것으로 특히, 씨드(seeding)층의 활성화 정도에 따라 일반의 CVD(Chemical Vapor Deposition)공정보다 증착속도를높이고 열처리에 따른 결정립간의 연결상태를 향상시켜 보다 낮은 비저항을 얻는데 적당하도록 한 반도체소자의 배선 형성방법에 관한 것이다.The present invention relates to the metallization of semiconductor devices. In particular, the deposition rate is higher than that of a conventional chemical vapor deposition (CVD) process and the connection state between grains due to heat treatment is improved according to the degree of activation of the seeding layer. A method for forming a wiring of a semiconductor device, which is suitable for obtaining the semiconductor device.
일반적으로 차세대 반도체 금속공정의 요구조건을 만족시키기 위한 대체물질로서는 알루미늄(Al)보다 비저항이 낮고 RC딜레이 시간을 감소시켜 빠른 응답속도를 가능하게 하는 구리(Cu)에 대한 연구가 널리 진행되고 있다.In general, as a substitute material for satisfying the requirements of the next-generation semiconductor metal process, research on copper (Cu), which has a lower specific resistance than aluminum (Al) and reduces the RC delay time, enables fast response speed.
이러한 구리를 사용함에 따라 컨포멀(conformal)한 스텝 커버리지를 얻을 수 있는 CVD공정이 PVD(physical vapor deposition)공정에 비해 선호되고 있다.As a result of using copper, a CVD process that achieves conformal step coverage is preferred to a physical vapor deposition (PVD) process.
실제 공정상에서 요구되는 단위시간당의 증착속도는 분당 1000Å이상의 큰 값을 필요로하고 있으며, 이러한 증착속도의 향상을 위해 기존의 CVD공정을 수정한 여러 가지 공정들이 제시되고 있다.The deposition rate per unit time required in the actual process requires a large value of more than 1000 microseconds per minute, and various processes are proposed to modify the existing CVD process to improve the deposition rate.
이중 실제 CVD공정 이전에 활성화층으로서 씨드(seeding)층에 의한 증착속도 향상을 위해 주로 사용되는 씨드층의 물질로서는 Pt, W, Ta, Cr 등의 금속이 있다.Among the materials of the seed layer mainly used for improving the deposition rate by the seed layer as the active layer before the actual CVD process, there are metals such as Pt, W, Ta and Cr.
이중에서도 반응성이 큰 Pt가 특히 널리 사용되고 있다.Among them, Pt, which is highly reactive, is particularly widely used.
일반적으로 씨드층을 형성시키는 경우, 씨드층의 반응성을 최대한 활용하기 위하여 촉매 활성화도를 최대로 할 수 있도록 될수있는대로 얇은 두께의 씨드층을 증착시키는 연구가 진행되고 있다.In general, in the case of forming the seed layer, research is being conducted to deposit a seed layer having a thin thickness as much as possible to maximize the catalyst activation degree in order to maximize the reactivity of the seed layer.
이러한 씨드층의 형성방법으로서는 증착층의 두께 제어를 정확히 하기 위해 팬단트 드롭(pendant drop)이라는 방법을 사용하고 있다.As a method of forming the seed layer, a method called a pendant drop is used to precisely control the thickness of the deposition layer.
구리를 MOCVD(metal organic CVD)방법으로 증착할 경우, 구리의 증착속도는 CVD반응초기에 핵생성을 하기위해 기판위로 아무런 반응이 없이 지속되는 인큐베이션(incubation)타임이 존재한다.When copper is deposited by metal organic CVD (MOCVD), there is an incubation time in which the deposition rate of copper continues without reaction on the substrate to nucleate early in the CVD reaction.
이러한 인큐베이션 타임의 유무는 동일 시간동안 증착을 실시하는 경우, 최종의 박막에 있어서 두께의 차이를 유발하며 박막의 최종두께를 증착시간으로 나누어 환산하는 증착속도에서도 차이를 일으키게 된다.The presence or absence of such incubation time causes a difference in thickness in the final thin film when the deposition is performed for the same time, and also in a deposition rate in which the final thickness of the thin film is divided by the deposition time.
따라서 CVD반응 이전에 미리 핵을 생성시켜 핵 생성을 위해 요구되는 인큐베이션 타임을 상쇄시킴으로서 최종의 박막두께를 증가시키고자 하는 연구가 진행되고 있고 그중에서 CVD공정 이전에 씨드층을 형성시키는 방법들이 연구되고 있다.Therefore, studies have been made to increase the final thin film thickness by counteracting the incubation time required for nucleation by generating nuclei before the CVD reaction, and among them, methods for forming a seed layer before the CVD process are studied. have.
이러한 구리의 CVD공정 이전에 씨드층을 형성하는 연구는 특히 PVD공정을 통하여 씨드층을 형성하는 방법들이 제기되고 있다.The research on forming the seed layer prior to the CVD process of copper has been proposed to form the seed layer through the PVD process.
특히, 써말 에바포레이션(Thermal evaporation)에 의한 씨드층의 형성이 여러 연구를 통해 보고 되고 있다.In particular, the formation of seed layers by thermal evaporation has been reported through various studies.
일반적으로 씨드층의 두께는 반응성의 향상 측면에서 되도록 얇게 증착하고 특히, 씨드층의 두께가 모노레이어(monolayer)정도로 매우 얇은 경우에는 활성화정도의 증가로 인하여 큰 증착속도을 얻을 수 있다.In general, the thickness of the seed layer is deposited as thin as possible in terms of improving the reactivity. In particular, when the thickness of the seed layer is very thin, such as a monolayer, a large deposition rate can be obtained due to an increase in the activation degree.
도 1은 종래 반도체소자의 배선 형성방법을 설명하기 위한 개념도이다.1 is a conceptual diagram illustrating a wiring forming method of a conventional semiconductor device.
전술한 바와같이 실제 CVD공정 이전에 활성화층으로서 씨드(seeding)층에 의한 증착속도 향상을 위해 주로 사용되는 씨드층의 물질로서는 Pt, W, Ta, Cr 등의 금속이 있다.As described above, metals such as Pt, W, Ta, and Cr are used as a material of the seed layer mainly used for improving the deposition rate by the seed layer as an activation layer before the actual CVD process.
이중에서도 반응성이 큰 Pt가 특히 널리 사용되고 있다.Among them, Pt, which is highly reactive, is particularly widely used.
도 1에 도시한 바와같이 소정깊이로 트랜치(12)를 갖는 반도체 기판(11)의상기 트랜치(12)의 표면에 백금(Pt), 텅스텐(W) 등을 이용하여 스퍼터링(Sputtering)법으로 씨드층(13)을 형성한다.As shown in FIG. 1, the surface of the
이때 상기 씨드층(13)의 반응성을 최대한 활용하기 위하여 촉매 활성화도를 최대로 할 수 있도록 될수있는대로 얇은 두께의 씨드층(13)을 증착시키는 연구가 진행되고 있다.At this time, in order to maximize the reactivity of the
이어, 상기 씨드층(13)을 형성한 후, 상기 씨드층(13)상에 구리를 CVD법을 이용하여 증착하여 박막(14)을 형성한다.Subsequently, after the
이와같이 씨드층(13)을 통한 박막(14)의 증착속도를 향상시키고자 하였다.As described above, the deposition rate of the
그러나 상기와 같은 종래 반도체소자의 배선 형성방법은 다음과 같은 문제점이 있었다.However, the wiring forming method of the conventional semiconductor device as described above has the following problems.
첫째, 씨드층을 이용하여 구리의 증착속도를 향상시킬 수 있다는 측면에서 증착하는 물질과 씨드층의 레티스 미스메치(lattice mismatch)를 고려하지 않고 있으므로 최종박막의 특성에 영향을 미치게 된다.First, in view of improving the deposition rate of copper by using the seed layer, the lattice mismatch of the material and the seed layer to be deposited is not taken into consideration, thus affecting the properties of the final thin film.
둘째, 구리박막을 형성하기 이전에 백금이나 텅스텐 등을 씨드층으로 사용한 경우, 구리박막과 씨드층과의 접착력이 불량해진다.Second, when platinum or tungsten is used as the seed layer before forming the copper thin film, the adhesion between the copper thin film and the seed layer is poor.
셋째, 씨드층의 프리페어드 오리엔테이션(preferred orientation)이 최종의 박막에 영향을 줄 수 있다.Third, the prepared orientation of the seed layer can affect the final thin film.
넷째, 씨드층과 구리박막형성에 따른 두 가지 공정의 병합으로 인한 결정립간의 연결 등의 문제점을 해결하기에는 부족하다.Fourth, it is insufficient to solve problems such as the connection between grains due to the merging of two processes due to the formation of the seed layer and the copper thin film.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서 씨드층의 물질과 그 위에 증착되는 물질이 동일한 구리로 사용하여 증착되는 원자를 가속하여 기판으로의 쉘로우(shallow)이온주입하므로서 높은 접착력을 갖는 반도체소자의 배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems, the semiconductor material having a high adhesion by the shallow ion implantation to the substrate by accelerating the atoms deposited using the same copper material of the seed layer and the material deposited thereon It is an object of the present invention to provide a method for forming wiring of an element.
도 1은 종래 반도체소자의 배선 형성방법을 설명하기 위한 개념도1 is a conceptual diagram illustrating a wiring forming method of a conventional semiconductor device.
도 2는 본 발명에 의한 반도체소자의 배선 형성방법을 설명하기 위한 개념도2 is a conceptual diagram illustrating a method for forming a wiring of a semiconductor device according to the present invention.
도 3은 본 발명의 씨드층에 의한 박막의 증착속도를 나타낸 개략도Figure 3 is a schematic diagram showing the deposition rate of the thin film by the seed layer of the present invention
도 4는 본 발명에 대한 ICB 씨드층의 접착력 향상 및 비저항 감소를 나타낸 그래프Figure 4 is a graph showing the adhesion improvement and resistivity reduction of the ICB seed layer for the present invention
도 5는 본 발명에 의한 박막 형성후 열처리에 다른 면저항 감소를 나타낸 그래프5 is a graph showing a reduction in sheet resistance to heat treatment after forming a thin film according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판22 : 트랜치21
23 : 씨드층24 : 박막23
상기의 목적을 달성하기 위한 본 발명의 반도체소자 배선 형성방법은 기판의 표면에 PVD 공정을 이용하여 씨드층을 형성하는 단계와, 상기 씨드층의 표면에 CVD 공정을 이용하여 상기 씨드층과 동일한 물질로 박막을 형성하는 단계와, 그리고 상기 박막의 비저항을 감소시키기 위해 진공하에서 열처리를 실시하는 단계를 포함하여 형성함을 특징으로 한다.The semiconductor device wiring forming method of the present invention for achieving the above object is a step of forming a seed layer on the surface of the substrate using a PVD process, the same material as the seed layer using a CVD process on the surface of the seed layer Forming a thin film, and performing heat treatment under vacuum to reduce the resistivity of the thin film.
이하, 본 발명의 반도체소자의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a wiring forming method of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명에 의한 반도체소자의 배선 형성방법을 설명하기 위한 개념도이다.2 is a conceptual diagram for explaining a method for forming a wiring of a semiconductor device according to the present invention.
도 2에 도시한 바와같이 소정깊이로 트랜치(22)를 갖는 반도체 기판(21)의 상기 트랜치(22)의 표면에 PVD 공정인 ICB(ionized cluster beam) 공정을 이용하여 쉐도우 이온주입을 실시하여 후공정에서 상기 반도체 기판(21)과 박막의 접착력을 증가시키도록 씨드층(23)을 형성한다.As shown in FIG. 2, shadow ion implantation is performed on the surface of the
이때 상기 씨드층(23)은 구리로 형성하며, 상기 씨드층(23)의 두께에 의한 영향을 고려하기 위해 씨드층(23)의 두께를 변화시켜 증착한다.In this case, the
이어, 상기 씨드층(23)을 형성한 후, 상기 씨드층(23)상에 구리를 CVD법을 이용하여 증착함으로써 박막(24)을 형성한다.Subsequently, after the
그리고 상기 씨드층(23)과 박막(24)을 형성하기 위한 공정이 서로 다른 공정즉, PVD와 CVD 공정을 사용하였기 때문에 상기 박막(24)의 비저항을 줄이기 위해 3×10-5Torr의 진공하에서 각각 400℃, 500℃, 600℃의 열처리 온도로 30분간 열처리를 실시한다.In addition, since the processes for forming the
도 3은 본 발명의 씨드층에 의한 박막의 증착속도를 나타낸 개략도이고, 도 4는 본 발명의 의한 ICB 씨드층의 접착력 향상 및 비저항 감소를 나타낸 그래프이며, 도 5는 본 발명에 의한 박막형성 후 열처리에 다른 면저항 감소를 나타낸 그래프이다.Figure 3 is a schematic diagram showing the deposition rate of the thin film by the seed layer of the present invention, Figure 4 is a graph showing the adhesion and reduction of the specific resistance of the ICB seed layer of the present invention, Figure 5 is after forming a thin film according to the present invention It is a graph showing other sheet resistance reduction in heat treatment.
도 3에 도시한 바와같이 증착온도를 130℃로부터 170℃로 변화시켜 가면서 증착한 박막의 경우 최종의 증착속도는 씨드층을 5Å으로 갖는 경우가 가장 큰 값을 나타냈으며, 전체적으로는 씨드층을 갖는 경우가 ICB 씨드층을 갖지 않는 경우에 비해 높은 증착속도를 나타낸다.As shown in FIG. 3, the final deposition rate of the thin film deposited by varying the deposition temperature from 130 ° C. to 170 ° C. showed the highest value when the seed layer had 5 μs. The case shows a higher deposition rate compared to the case without the ICB seed layer.
이어, 도 4에 도시한 바와같이 ICB 씨드층위에 증착된 박막의 경우 접착력이 21 N에서 27 N으로 증가하였으며, 200℃에서 증착한 경우 박막의 비저항 값은 40Å씨드층의 경우 2.42μΩ·cm로서 씨드층을 갖지 않는 2.81μΩ·cm의 경우에 비해 낮은 값을 가짐을 나타낸다.As shown in FIG. 4, the adhesion strength of the thin film deposited on the ICB seed layer was increased from 21 N to 27 N, and when deposited at 200 ° C., the specific resistance of the thin film was 2.42 μΩ · cm for the 40 Å seed layer. It is shown to have a lower value as compared with the case of 2.81 μΩ · cm without the seed layer.
그리고 도 5에 도시한 바와같이 박막의 열처리 온도를 증가시켜감에 따른 최종 박막의 면저항이 감소함을 확인할 수 있으며, 이러한 면저항의 감소는 열처리에 따른 결정립간의 콘택의 향상으로 인함을 나타낸다.As shown in FIG. 5, it can be seen that the sheet resistance of the final thin film decreases as the heat treatment temperature of the thin film is increased, and the decrease in the sheet resistance is due to the improvement of contact between grains due to the heat treatment.
이상에서 설명한 반도체소자의 배선 형성방법에 있어서 다음과 같은 효과가 있다.The wiring forming method of the semiconductor element described above has the following effects.
첫째, 씨드층을 ICB공정으로 형성시 원자가 가속되어 기판으로 쉐도우 인플런트되어 기판과 박막간의 접착력을 향상시킬 수 있다.First, when the seed layer is formed by the ICB process, atoms are accelerated and shadow inflected onto the substrate, thereby improving adhesion between the substrate and the thin film.
둘째, 씨드층과 최종 박막의 형성물질을 동일한 물질로 형성함으로써 결정립간의 콘택이 우수하며, 박막의 비저항을 감소시킬 수 있다.Second, by forming the seed material and the final thin film forming material of the same material, the contact between the grains is excellent, and the specific resistance of the thin film can be reduced.
셋째, CVD와 PVD 공정의 병합으로 인한 불안정을 막기위해 진공하에서 열처리함으로서 최종적으로 낮은 비저항을 갖는 박막을 형성할 수 있다.Third, in order to prevent instability due to the incorporation of CVD and PVD processes, heat treatment under vacuum can finally form a thin film having a low resistivity.
Claims (4)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778869A (en) * | 1993-06-30 | 1995-03-20 | Kawasaki Steel Corp | Semiconductor device and manufacture thereof |
| KR0129201B1 (en) * | 1994-09-29 | 1998-04-06 | 문정환 | Manufacturing method for metal line film of semiconductor device |
| KR100187686B1 (en) * | 1996-03-16 | 1999-06-01 | 김영환 | Metal layer forming method of semiconductor device |
| KR100253561B1 (en) * | 1992-08-28 | 2000-05-01 | 김영환 | Method of depositing w on oxide of semiconductor device without adhesion layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100253561B1 (en) * | 1992-08-28 | 2000-05-01 | 김영환 | Method of depositing w on oxide of semiconductor device without adhesion layer |
| JPH0778869A (en) * | 1993-06-30 | 1995-03-20 | Kawasaki Steel Corp | Semiconductor device and manufacture thereof |
| KR0129201B1 (en) * | 1994-09-29 | 1998-04-06 | 문정환 | Manufacturing method for metal line film of semiconductor device |
| KR100187686B1 (en) * | 1996-03-16 | 1999-06-01 | 김영환 | Metal layer forming method of semiconductor device |
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