KR100477813B1 - Tungsten Metal Wiring Formation Method of Semiconductor Device - Google Patents

Tungsten Metal Wiring Formation Method of Semiconductor Device Download PDF

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KR100477813B1
KR100477813B1 KR1019970075071A KR19970075071A KR100477813B1 KR 100477813 B1 KR100477813 B1 KR 100477813B1 KR 1019970075071 A KR1019970075071 A KR 1019970075071A KR 19970075071 A KR19970075071 A KR 19970075071A KR 100477813 B1 KR100477813 B1 KR 100477813B1
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gas
tungsten
semiconductor device
film
metal wiring
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KR1019970075071A
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KR19990055159A (en
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채무성
김정태
이상협
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

본 발명은 반도체 제조 분야에 관한 것으로, 특히 금속배선(metallization) 공정에 관한 것이며, 특히 차세대 반도체 장치의 금속배선으로 사용될 수 있는 저저항 텅스텐(low-resistivity W) 공정에 관한 것이며, 저항 특성 및 불순물 확산 특성을 개선하는 반도체 장치의 금속배선 형성방법을 제공하는데 그 목적이 있다. 본 발명은 종래의 저저항 텅스텐 증착 공정을 개선한 것으로. 텅스텐 증착을 2단계로 나누어 진행하고자 하며, 그 첫 단계에서는 통상적인 SiH4 가스 및 H2 가스의 혼합가스를 사용하여 되도록 얇은 제1 텅스텐막을 형성하여 결정입자 크기가 작아 비저항이 높아지지만 후속 공정시 확산 방지막과 더불어 붕소의 확산 방지 특성을 확보하고, 두번째 단계에서는 B2H6 가스를 사용하여 텅스텐 결정입자를 크게 형성함으로써 낮은 비저항 특성을 가지는 제2 텅스텐막을 증착하는 기술이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a metallization process, and more particularly to a low-resistance tungsten (low-resistivity W) process that can be used as a metallization of next-generation semiconductor devices. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wirings in a semiconductor device to improve diffusion characteristics. The present invention is an improvement on the conventional low resistance tungsten deposition process. Tungsten deposition is carried out in two stages. In the first stage, a thin first tungsten film is formed by using a mixed gas of a conventional SiH 4 gas and H 2 gas so that the crystal grain size is small and the specific resistance is increased. It is a technique of depositing a second tungsten film having low resistivity by securing a diffusion preventing property of boron together with a diffusion preventing film and forming tungsten crystal grains largely using B 2 H 6 gas.

Description

반도체 장치의 텅스텐 금속배선 형성방법Method of forming tungsten metal wiring in semiconductor device

본 발명은 반도체 제조 분야에 관한 것으로, 특히 금속배선(metallization) 공정에 관한 것이며, 특히 차세대 반도체 장치의 금속배선으로 사용될 수 있는 저저항 텅스텐(low-resistivity W) 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly to a metallization process, and more particularly to a low-resistance tungsten (low-resistivity W) process that can be used as metallization in next-generation semiconductor devices.

종래의 반도체 장치 제조 공정시 금속배선 재료로서 텅스텐(w)을 사용하였으나, 텅스텐막은 그 자체의 비저항이 높아 지연 시간이 큰 문제점이 있었다. 반도체 장치의 신호처리 속도 향상을 위하여 비저항이 낮은 알루미늄(Al) 또는 구리(Cu)를 사용한 금속배선 공정을 개발하기 위한 노력이 진행되고 있다. 그러나, 한편 알루미늄은 취약한 단차 피복성과 전자이주/스트레스이주 현상으로 인하여 차세대 고집적 소자에 적용하기 어려운 문제점이 있으며, 구리의 경우 다른 층과의 계면 특성 및 확산 특성이 열악하여 이를 보완해야하는 과제를 안고 있다.In the conventional semiconductor device manufacturing process, tungsten (w) is used as the metal wiring material, but the tungsten film has a problem in that a delay time is high because of its high specific resistance. Efforts have been made to develop a metallization process using aluminum (Al) or copper (Cu) with low specific resistance to improve signal processing speed of semiconductor devices. However, aluminum has a problem that it is difficult to apply to next-generation high-density devices because of weak step coverage and electron migration / stress migration phenomenon, and copper has a problem of compensating for poor interface and diffusion characteristics with other layers. .

최근에는 화학기상증착(CVD) 방식으로 증착된 텅스텐막의 장점을 이용하기 위하여 텅스텐 자체의 비저항을 낮추는 저저항 텅스텐 증착 공정이 개발되고 있다. 저저항 텅스텐 증착 공정은 반응 가스로써 종래의 수소(H2)를 대신하여 다이보레인(B2H6)을 사용함으로써 텅스텐 결정입자의 크기를 더 크게 성장시켜 비저항을 종전보다 30% 이상 낮추는 기술이다.Recently, in order to take advantage of the tungsten film deposited by chemical vapor deposition (CVD), a low-resistance tungsten deposition process for lowering the specific resistance of tungsten itself has been developed. The low-resistance tungsten deposition process uses a diborane (B 2 H 6 ) instead of hydrogen (H 2 ) as a reaction gas to grow tungsten crystal grains larger and lower the specific resistance by more than 30%. to be.

그러나, 저저항 텅스텐 증착 공정시 B2H6 가스 내의 붕소(B)가 불순물로 작용하여 금속 콘택의 소오스/드레인 접합영역의 도핑 농도를 변화시킬 수 있다. 붕소의 침투를 막기 위하여 텅스텐막의 하지층에 확산 방지막을 적용하기도 하지만 종래의 확산 방지막으로는 크기가 작은 붕소의 확산을 막을 수 없는 문제점이 있었다.However, in the low resistance tungsten deposition process, boron (B) in the B 2 H 6 gas may act as an impurity to change the doping concentration of the source / drain junction region of the metal contact. In order to prevent boron infiltration, a diffusion barrier layer may be applied to the underlayer of the tungsten layer, but there is a problem in that the diffusion barrier may not prevent the diffusion of small boron.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 저항 특성 및 불순물 확산 특성을 개선하는 반도체 장치의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for forming a metal wiring in a semiconductor device which improves resistance characteristics and impurity diffusion characteristics.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 반도체 기판 상에 형성된 층간 절연막을 선택 식각하여 금속 콘택홀을 형성하는 제1 단계; SiH4 가스를 포함하는 반응가스를 사용한 화학기상증착 방식으로 전체구조 상부에 제1 텅스텐막을 증착하는 제2 단계; 및 B2H6 가스를 포함하는 반응가스를 사용한 화학기상증착 방식으로 전체구조 상부에 제2 텅스텐막을 증착하는 제3 단계를 포함하는 반도체 장치의 금속배선 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, a first step of forming a metal contact hole by selectively etching the interlayer insulating film formed on the semiconductor substrate; Depositing a first tungsten film on the entire structure by chemical vapor deposition using a reaction gas containing SiH 4 gas; And a third step of depositing a second tungsten film on the entire structure in a chemical vapor deposition method using a reaction gas including a B 2 H 6 gas.

본 발명은 종래의 저저항 텅스텐 증착 공정을 개선한 것으로. 텅스텐 증착을 2단계로 나누어 진행하고자 하며, 그 첫 단계에서는 통상적인 SiH4 가스 및 H2 가스의 혼합가스를 사용하여 되도록 얇은 제1 텅스텐막을 형성하여 결정입자의 크기가 작아 비저항이 높아지지만 후속 공정시 확산 방지막과 더불어 붕소의 확산 방지 특성을 확보하고, 두번째 단계에서는 B2H6 가스를 사용하여 텅스텐 결정입자를 크게 형성함으로써 낮은 비저항 특성을 가지는 제2 텅스텐막을 증착하는 기술이다.The present invention is an improvement on the conventional low resistance tungsten deposition process. Tungsten deposition is carried out in two stages. In the first stage, a thin first tungsten film is formed by using a mixed gas of a conventional SiH 4 gas and H 2 gas to increase the specific resistance due to the small size of crystal grains. In addition to the diffusion diffusion film, the boron diffusion prevention property is secured, and in the second step, a second tungsten film having low specific resistance is deposited by forming large tungsten crystal grains using B 2 H 6 gas.

이하, 본 발명의 일실시예를 소개한다. Hereinafter, an embodiment of the present invention will be introduced.

본 발명의 일실시예에 따른 금속배선 형성 공정은 다음과 같다.The metallization forming process according to the embodiment of the present invention is as follows.

우선, 소정의 하부층 공정을 마친 실리콘 기판 전체구조 상부에 층간 절연막을 형성하고, 이를 선택 식각하여 금속 콘택홀을 형성한다.First, an interlayer insulating film is formed on the entire silicon substrate structure having a predetermined lower layer process, and then selectively etched to form a metal contact hole.

다음으로, 전체구조 상부에 접합층(glue layer)인 Ti막 및 장벽 금속(barrier metal)인 TiN막을 차례로 증착한다. 이때, Ti/TiN 구조를 대신하여 TiN막만을 사용할 수도 있다.Next, a Ti film, which is a glue layer, and a TiN film, which is a barrier metal, are sequentially deposited on the entire structure. In this case, only the TiN film may be used instead of the Ti / TiN structure.

계속하여, 소오스 가스로서 WF6 가스를 사용하며 반응 가스로서 SiH4 가스 또는 SiH4 가스, H2 가스의 혼합가스를 사용하는 화학기상증착 방식으로 10～3000Å 두께의 제1 텅스텐막을 전체구조 상부에 증착한다. 이때, SiH4 가스의 유량을 5～100sccm, 반응기 내의 서셉터(susceptor)의 온도를 300～750℃ 정도로 조절하며, 반응기 내의 압력을 1～20Torr 정도로 유지하여 1분 정도 증착을 진행한다.Subsequently, a first tungsten film having a thickness of 10 to 3000 mm 3 was deposited on the entire structure by chemical vapor deposition using WF 6 gas as the source gas and a mixed gas of SiH 4 gas or SiH 4 gas and H 2 gas as the reaction gas. Deposit. At this time, the flow rate of the SiH 4 gas is adjusted to 5 to 100 sccm, the temperature of the susceptor in the reactor is about 300 to 750 ° C., and the deposition is performed for about 1 minute while maintaining the pressure in the reactor at about 1 to 20 Torr.

이어서, 동일 챔버 내에서 소오스 가스로서 WF6 가스를 사용하며 반응 가스로서 B2H6 가스 또는 B2H6 가스, H2 가스의 혼합가스를 사용하여 10～6000Å 두께의 제2 텅스텐막을 전체구조 상부에 증착한다. 이때, B2H6 가스의 유량은 5～1000sccm 내에서 조절하며, 반응기 내의 압력을 1～100Torr로 유지한다.Subsequently, in the same chamber, a second tungsten film having a thickness of 10 to 6000 μs was formed by using a WF 6 gas as a source gas and using a mixed gas of B 2 H 6 gas or B 2 H 6 gas and H 2 gas as a reaction gas. Deposit on top. At this time, the flow rate of the B 2 H 6 gas is controlled within 5 ~ 1000sccm, the pressure in the reactor is maintained at 1 ~ 100 Torr.

상술한 일실시예에서 제1 텅스텐막은 금속배선의 저항 특성 및 확산 방지 특성을 고려하여 그 두께를 조절하는데 100Å 정도면 바람직하다고 할 수 있다.In the above-described embodiment, the first tungsten film is preferably about 100 kW in order to adjust the thickness in consideration of the resistance characteristics and the diffusion preventing properties of the metal wiring.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

이상에서와 같이 본 발명에 의하면 기존의 장비를 이용하여 텅스텐 금속배선의 저항 특성을 개선함으로써 소자의 신호처리 속도를 향상시킬 수 있으며, 확산 금속막의 확산 방지 특성을 향상시킬 수 있어 반도체 장치의 신뢰도를 개선할 수 있다.As described above, according to the present invention, the signal processing speed of the device can be improved by improving the resistance characteristics of the tungsten metal wiring by using existing equipment, and the diffusion preventing property of the diffusion metal film can be improved, thereby improving the reliability of the semiconductor device. It can be improved.

Claims (8)

반도체 기판 상에 형성된 층간 절연막을 선택 식각하여 금속 콘택홀을 형성하는 제1 단계; Forming a metal contact hole by selectively etching the interlayer insulating layer formed on the semiconductor substrate; SiH4 가스를 포함하는 반응가스를 사용한 화학기상증착 방식으로 전체구조 상부에 제1 텅스텐막을 증착하는 제2 단계; 및Depositing a first tungsten film on the entire structure by chemical vapor deposition using a reaction gas containing SiH 4 gas; And B2H6 가스를 포함하는 반응가스를 사용한 화학기상증착 방식으로 전체구조 상부에 제2 텅스텐막을 증착하는 제3 단계A third step of depositing a second tungsten film on the entire structure by chemical vapor deposition using a reaction gas containing a B 2 H 6 gas 를 포함하는 반도체 장치의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1 단계 수행후After performing the first step 전체구조 상부에 장벽 금속막을 형성하는 제4 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.And forming a barrier metal film over the entire structure. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제2 단계는,The second step, 300 내지 750℃의 서셉터 온도 및 1 내지 20Torr의 공정 압력 조건하에서 수행하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.A method for forming metal wiring in a semiconductor device, characterized in that it is carried out under a susceptor temperature of 300 to 750 ° C and a process pressure of 1 to 20 Torr. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제3 단계는,The third step, 300 내지 750℃의 서셉터 온도 및 1 내지 100Torr의 공정 압력 조건하에서 수행하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.A metal wiring forming method for a semiconductor device, characterized in that it is carried out under a susceptor temperature of 300 to 750 ℃ and a process pressure of 1 to 100 Torr. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제2 단계에서,In the second step, 상기 반응가스는 H2 가스를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.And the reaction gas further comprises H 2 gas. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제3 단계에서, In the third step, 상기 반응가스는 H2 가스를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.And the reaction gas further comprises H 2 gas. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제1 텅스텐막은 10 내지 3000Å 두께인 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.And the first tungsten film is 10 to 3000 kPa thick. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제2 텅스텐막은 10 내지 6000Å 두께인 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.And the second tungsten film is 10 to 6000 GPa thick.
KR1019970075071A 1997-12-27 1997-12-27 Tungsten Metal Wiring Formation Method of Semiconductor Device KR100477813B1 (en)

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