KR960035901A - Gate electrode formation method - Google Patents

Gate electrode formation method Download PDF

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Publication number
KR960035901A
KR960035901A KR1019950006076A KR19950006076A KR960035901A KR 960035901 A KR960035901 A KR 960035901A KR 1019950006076 A KR1019950006076 A KR 1019950006076A KR 19950006076 A KR19950006076 A KR 19950006076A KR 960035901 A KR960035901 A KR 960035901A
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KR
South Korea
Prior art keywords
layer
oxide layer
gate electrode
conductive layer
forming
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KR1019950006076A
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Korean (ko)
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KR100321760B1 (en
Inventor
김도우
이인찬
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김주용
현대전자산업 주식회사
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Priority to KR1019950006076A priority Critical patent/KR100321760B1/en
Publication of KR960035901A publication Critical patent/KR960035901A/en
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Publication of KR100321760B1 publication Critical patent/KR100321760B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자 제조공정중 게이트 전극 형성방법에 있어서, 반도체 기판(11) 상부에 게이트 절연층(12), 제1전도층(13), 제1산화층(14), 질화층(15), 제2산화층(16)을 차례로 형성한 후, 상기 제2산화층(16), 질화층(15)의 예정된 부위를 차례로 제거하는 제1단계; 상기 제1단계 수행후, 예정된 부위가 제거된 상기 제2산화층(16), 질화층(15)의 측벽에 스페이서(17)를 형성한 후, 상기 제2산화층(16) 및 노출된 제1산화층(14)을 제거하는 제2단계; 상기 제2단계 수행후, 노출된 상기 제1전도층(13)상에 제2전도층(18)을 형성하는 제3단계; 상기 스페이서(17), 질화층(15), 제1산화층(14)을 제거한후, 상기 제2전도층(18)을 식각벽으로 제1전도층(13), 게이트 절연층(12)을 차례로 제거하는 제4단계를 포함하는 것을 특징으로 하여, 게이트 전극의 임계치를 패턴가능한 마스크의 임계치보다 작게 디파인하고, 보다 정확하게 제어할 수 있어 소자의 수율 및 전기적 특성을 향상시킬 수 있는 특유의 효과가 있는 게이트 전극 형성방법에 관한 것이다.In the method of forming a gate electrode during the semiconductor device manufacturing process, the gate insulating layer 12, the first conductive layer 13, the first oxide layer 14, the nitride layer 15, A first step of sequentially forming the second oxide layer 16, and then sequentially removing predetermined portions of the second oxide layer 16 and the nitride layer 15; After performing the first step, the spacer 17 is formed on sidewalls of the second oxide layer 16 and the nitride layer 15 from which the predetermined portion is removed, and then the second oxide layer 16 and the exposed first oxide layer are formed. A second step of removing (14); A third step of forming a second conductive layer 18 on the exposed first conductive layer 13 after performing the second step; After removing the spacer 17, the nitride layer 15, and the first oxide layer 14, the first conductive layer 13 and the gate insulating layer 12 are sequentially formed by using the second conductive layer 18 as an etch wall. And removing the threshold value of the gate electrode smaller than the threshold value of the patternable mask and controlling the gate electrode more accurately, thereby improving the yield and electrical characteristics of the device. A method of forming a gate electrode is provided.

Description

게이트 전극 형성방법Gate electrode formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2G도는 본 발명에 따른 게이트 전극의 형성 공정도.2A to 2G are process charts for forming a gate electrode according to the present invention.

Claims (4)

반도체 소자 제조공정중 게이트 전극 형성방법에 있어서, 반도체 기판 상부에 게이트 절연층, 제1전도층, 제1산화층, 질화층, 제2산화층을 차례로 형성한 후, 상기 제2산화층, 질화층의 예정된 부위를 차례로 제거하는 제1단계; 상기 제1단계 수행후, 예정된 부위가 제거된 상기 제2산화층, 질화층의 측벽에 스페이서를 형성한 후, 상기 제2산화층 및 노출된 제1산화층을 제거하는 제2단계; 상기 제2단계 수행후, 노출된 상기 제1전도층 상에 제2전도층을 형성하는 제3단계; 상기 스페이서, 질화층, 제1산화층을 제거한 후, 상기 제2전도층을 식각벽으로 제1전도층, 게이트 절연층을 차례로 제거하는 제4단계를 포함하는 것을 특징으로 하는 게이트 전극 형성방법.In the method of forming a gate electrode during a semiconductor device manufacturing process, a gate insulating layer, a first conductive layer, a first oxide layer, a nitride layer, and a second oxide layer are sequentially formed on a semiconductor substrate, and then the second oxide layer and the nitride layer A first step of sequentially removing the sites; A second step of forming a spacer on sidewalls of the second oxide layer and nitride layer from which a predetermined site is removed after performing the first step, and then removing the second oxide layer and the exposed first oxide layer; A third step of forming a second conductive layer on the exposed first conductive layer after performing the second step; And removing the spacer, the nitride layer, and the first oxide layer, and then sequentially removing the first conductive layer and the gate insulating layer by using the second conductive layer as an etch wall. 제1항에 있어서, 상기 제3단계에서 제2전도층은, 선택성장법을 이용하여 형성하는 것을 특징으로 하는 게이트 전극 형성방법.The method of claim 1, wherein in the third step, the second conductive layer is formed using a selective growth method. 제1항 또는 제2항에 있어서, 상기 제2전도층은, 텅스텐층인 것을 특징으로 하는 게이트 전극 형성 방법.The gate electrode forming method according to claim 1 or 2, wherein the second conductive layer is a tungsten layer. 제1항에 있어서, 상기 스페이서는, 질화층 스페이서인 것을 특징으로 하는 게이트 전극 형성방법.The method of claim 1, wherein the spacer is a nitride layer spacer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006076A 1995-03-22 1995-03-22 A method for fabrication of semiconductor device KR100321760B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006076A KR100321760B1 (en) 1995-03-22 1995-03-22 A method for fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006076A KR100321760B1 (en) 1995-03-22 1995-03-22 A method for fabrication of semiconductor device

Publications (2)

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KR960035901A true KR960035901A (en) 1996-10-28
KR100321760B1 KR100321760B1 (en) 2002-05-13

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KR100321760B1 (en) 2002-05-13

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