KR960043155A - Method for manufacturing charge storage electrode of capacitor - Google Patents

Method for manufacturing charge storage electrode of capacitor Download PDF

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Publication number
KR960043155A
KR960043155A KR1019950010989A KR19950010989A KR960043155A KR 960043155 A KR960043155 A KR 960043155A KR 1019950010989 A KR1019950010989 A KR 1019950010989A KR 19950010989 A KR19950010989 A KR 19950010989A KR 960043155 A KR960043155 A KR 960043155A
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KR
South Korea
Prior art keywords
spacer
cylinder structure
charge storage
storage electrode
polysilicon layer
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Application number
KR1019950010989A
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Korean (ko)
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KR100223286B1 (en
Inventor
임찬
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950010989A priority Critical patent/KR100223286B1/en
Publication of KR960043155A publication Critical patent/KR960043155A/en
Application granted granted Critical
Publication of KR100223286B1 publication Critical patent/KR100223286B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 캐패시터의 전하저장전극 제조방법에 관하여 개시된다.The present invention relates to a method of manufacturing a charge storage electrode of a capacitor.

본 발명은 접합부 윗부분의 폴리실리콘층에 산화물(또는 질화물) 스페이서를 형성한 후, 이를 이용한 폴리실리콘 식각공정으로 내측 실린더 구조를 형성하고, 내측 실린더 구조 측벽에 다시 산화물(또는 질화물) 스페이서를 형성한 후, 이를 이용한 폴리실리콘 스페이서 형성공정으로 외측 실린더 구조를 형성하므로써, 제한된면적하에서 유효 표면적을 극대화 할 수 있다.In the present invention, after forming an oxide (or nitride) spacer on the polysilicon layer above the junction, an inner cylinder structure is formed by a polysilicon etching process using the same, and an oxide (or nitride) spacer is formed on the inner cylinder structure sidewall again. Then, by forming the outer cylinder structure by the polysilicon spacer forming process using the same, it is possible to maximize the effective surface area under a limited area.

Description

캐패시터의 전하저장전극 제조방법Method for manufacturing charge storage electrode of capacitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A 내지 1F도는 본 발명에 의한 캐패시터의 전하저장전극을 제조하는 단계를 도시한 소자의 단면도.1A to 1F are cross-sectional views of a device showing a step of manufacturing a charge storage electrode of a capacitor according to the present invention.

Claims (5)

캐패시터의 전하저장전극 제조방법에 있어서, 반도체 기판상에 충간 절연막 및 식각 장벽층을 순차적으로 형성한 후 접합부상에 콘택홀을 형성하고, 상기 콘택홀을 포함한 상기 식각 장벽충상에 폴리실리콘층을 두껍게 형성하는 단계와, 상기 접합부 윗부분의 상기 폴리실리콘층의 표면에 제1요홈을 형성하고, 상기 제1요홈의 내측벽에 제1스페이서를 형성하는 단계와, 상기 제1스페이서를 식각 마스크로 한 비둥방성 폴리실리콘 식각공정으로 상기 식각 장벽충상에 얇은 두께로 남는 시점까지 상기 폴리실리콘층을 식각하므로, 이로 인하여 상기 제1스페이서 내측의 상기 폴리실리콘층이 식각되어 제2요홈이 형성되고, 상기 제1스페이서 아래의 폴리실리콘층이 남아 전하저장전극의 내측 실린더 구조가 형성되는 단계와, 상기 내측 실린더 구조의 측벽에 제2스페이서를 형성한 후, 상기 제1 및 2스페이서를 식각 마스크로 하여 상기 폴리실리콘층의 노출된 부분을 식각하는 단계와, 상기 제2스페이서 측벽에 전하저장전극의 외측 실린더 구조로 폴리실리콘 스페이서를 형성하는 단계와, 상기 제1 및 2스페이서를 습식식각공정으로 제거하여 상기 내측 실린더 구조와 상기 외측 실린더 구조로된 이중 실린더형 전하저장전극을 제조하는 단계로 이루어지는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.In the method of manufacturing a charge storage electrode of a capacitor, the interlayer insulating film and the etch barrier layer are sequentially formed on the semiconductor substrate, and then contact holes are formed on the junction, and the polysilicon layer is thickened on the etch barrier including the contact hole. Forming a first groove on a surface of the polysilicon layer above the junction portion, forming a first spacer on an inner wall of the first groove, and using a first spacer as an etch mask. Since the polysilicon layer is etched until a thin thickness remains on the etch barrier by the polysilicon etching process, the polysilicon layer inside the first spacer is etched to form a second recess, and thus the first recess is formed. Remaining polysilicon layer under the spacer to form the inner cylinder structure of the charge storage electrode, and the side wall of the inner cylinder structure After forming the second spacer, etching the exposed portion of the polysilicon layer using the first and second spacers as an etch mask, and the polysilicon spacer in the outer cylinder structure of the charge storage electrode on the sidewall of the second spacer And forming a double-cylindrical charge storage electrode having the inner cylinder structure and the outer cylinder structure by removing the first and second spacers by a wet etching process. Electrode manufacturing method. 제1항에 있어서, 상기 식각 장벽층을 상기 제1 및 2스페이서의 습식식각공정 후에 습식식각방법으로 제거하여 언더 컷을 형성하는 것을 포함한 캐패시터의 전하저장전극 제조방법.The method of claim 1, wherein the etching barrier layer is removed by a wet etching method after the wet etching process of the first and second spacers to form an undercut. 제1항에 있어서, 상기 제1 및 2스페이서는 산화물로 형성하는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The method of claim 1, wherein the first and second spacers are formed of an oxide. 제1항에 있어서, 상기 제1 및 2스페이서는 질화물로 형성하는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The method of claim 1, wherein the first and second spacers are formed of nitride. 제1항에있어서, 상기 제1요험은 상기 콘택홀 크기로 형성되는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The method of claim 1, wherein the first experience is formed in the contact hole size. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950010989A 1995-05-04 1995-05-04 Method for manufacturing charge storage node of capacitor KR100223286B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950010989A KR100223286B1 (en) 1995-05-04 1995-05-04 Method for manufacturing charge storage node of capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950010989A KR100223286B1 (en) 1995-05-04 1995-05-04 Method for manufacturing charge storage node of capacitor

Publications (2)

Publication Number Publication Date
KR960043155A true KR960043155A (en) 1996-12-23
KR100223286B1 KR100223286B1 (en) 1999-10-15

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