KR101065352B1 - MOS Transistor for Fabricating the Same - Google Patents

Abstract

The present invention relates to a MOS transistor having a dummy poly layer to improve leakage characteristics of a junction region, and a method of manufacturing the same. The MOS transistor of the present invention has a device isolation region and an active region defined therein. A substrate, a gate formed at a predetermined portion on an active region of the substrate, a dummy poly layer formed on the device isolation region, sidewalls and dummy polysidewalls formed at sides of the gate and the dummy polylayer, and the gate And source / drain defined on a substrate corresponding to both sides of the sidewall, and contact electrodes contacting each of the source / drain, wherein the source / drain and the contact electrodes are formed by the dummy poly sidewall and the sidewall. Self-aligned.

Dummy poly, self-aligned contact, contact spiking, junction area, leakage current

Description

MOS transistor and its manufacturing method {MOS Transistor for Fabricating the Same}

1 is a structural cross-sectional view showing a conventional MOS transistor

2 is a structural cross-sectional view showing a MOS transistor of the present invention.

3 is a plan view illustrating a semiconductor device including the MOS transistor of FIG. 2.

4A to 4G are cross-sectional views illustrating a method of manufacturing the MOS transistor of the present invention.

Description of the Related Art [0002]

100 substrate 101 device isolation film

102 source / drain 103 LDD region

104: gate insulating film 105a: gate

105b: dummy poly layer 106a: sidewall spacer

106b: dummy poly sidewall spacer 107a: source / drain silicide

107b: gate silicide 107c: dummy poly silicide

108: contact electrode 109: contact hole

110: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a MOS transistor and a method of manufacturing the same, by forming a dummy poly layer to improve leakage characteristics of a junction region.

Metal-Oxide-Semiconductor Filed Effect Transistors (MOSFETs) are commonly referred to as MOSs, and are recently used in large-scale integrated circuits because of their ability to increase the density of semiconductor memory devices. Here, MOS stands for metal-oxide-semiconductor and indicates the configuration of the gate.

Generally, a MOS transistor is formed by defining a source / drain at a predetermined portion of a substrate and forming a gate electrode on the substrate. In addition, a contact electrode is in contact with each of the source / drain to apply a voltage to the source / drain formed on the substrate.

Hereinafter, a conventional MOS transistor will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view showing a conventional MOS transistor.

As shown in FIG. 1, the conventional MOS transistor includes a substrate 1, an isolation layer 2 for distinguishing it from other elements formed on the substrate 1, and a gate 8 formed at a predetermined portion on the substrate 1. ), A source / drain 3 defined in the substrate 1 on both sides of the gate 8, and a contact electrode 11 contacting each of the source / drain 3.

Here, the substrate 1 is defined by dividing the device isolation region for isolation between a plurality of devices formed on the substrate and the active region in which the device is formed. In the device isolation region, a device isolation film made of a trench insulating film is formed.

The gate 8 and the source / drain 3 are polysilicon layers of the same type and are heavily doped, and silicides 9 and 6 are formed on the surfaces thereof to reduce contact resistance with metals. have.

In addition, an LDD region 5 connected to the source / drain 3 is formed on a surface of the substrate 1 corresponding to both sides of the gate 8. The formation of the LDD region 5 is to reduce the electric field between the drain and the channel region, thereby reducing the injection into the gate insulating film 7, impact ionization and other thermo-electronic effects.

On the other hand, a gate insulating film 7 is formed between the gate 8 and the substrate 1 to maintain insulation between the gate 8 and the substrate 1.

Hereinafter, a method of manufacturing a conventional MOS transistor will be described with reference to FIG. 1.

First, a substrate 1 of silicon component is prepared. At this time, the silicon substrate is crystallized polysilicon.

Subsequently, a predetermined portion of the substrate 1 is removed in a trench shape having a predetermined thickness, and then an insulating film is filled in this portion to form the element isolation film 2. At this time, by forming the device isolation film 2, the substrate 1 is divided into an isolation region in which the device isolation film 2 is formed, and an active region in which the device isolation film 2 is not formed, and the device is formed in the active region. Will be formed.

Subsequently, the substrate 1 is sequentially deposited on the entire surface of the gate insulating film 7 and a heavily doped polysilicon layer.

Subsequently, the polysilicon layer and the gate insulating film 7 are selectively removed to leave the gate 8 and the gate insulating film 7 in the active region of the predetermined region.

Subsequently, a lightly doped drain (LDD) region 5 is formed by doping the substrate 1 with a low concentration of impurities using the gate 8 as a mask.

Subsequently, an insulating film for forming side wall spacers is deposited on the entire surface of the substrate 1 including the gate 8.

Subsequently, the sidewall spacer forming insulating layer is selectively removed to form the sidewall spacer 10 on the side of the gate 8.

Next, a source / drain 3 is defined in the substrate 1 by doping a high concentration of impurities using the gate 8 and the side wall spacer 10 as a mask.

Subsequently, the surfaces of the source / drain 3 and the gate 8 that are exposed and doped with high concentration impurities of the same type are reacted with a metal or a radical, and then heat-treated to form silicides 6 and 9, respectively.

Next, a contact electrode 11 for applying a voltage to the source / drain 3 is formed.                         

The impurities doped in the source / drain 3, the gate 8, and the LDD region 5 described above are impurity layers of the same type of n + or p +.

Although not shown, the contact electrode 11 may deposit an interlayer insulating film on the entire surface of the substrate 1 including the gate 8, remove the top of the source / drain, and contact the contact electrode at a portion where the interlayer insulating film is removed. (11) is formed by filling. At this time, when the interlayer insulating film is removed, this removed portion is called a contact hole.

Contact spiking between the substrate 1 and the device isolation film 2, such as part A, due to misalignment of the contact hole or variation of the critical dimension of the contact hole width. When spiking occurs, the drain 3 and the substrate 1 are short-circuited and current flows directly from the drain 3 to the substrate 1, thereby preventing the transistor from operating normally.

The conventional MOS transistor as described above has the following problems.

When the contact misalignment or the critical dimension variation of the contact electrode (contact hole) occurs, contact spiking occurs, so that the normal operation of the MOS transistor formed in the active region is not realized.

An object of the present invention is to provide a MOS transistor and a method for manufacturing the same, which have been devised to solve the above problems, and have improved a leakage characteristic of a junction region by forming a dummy poly layer.

In order to achieve the above object, a MOS transistor of the present invention includes a substrate in which a device isolation region and an active region are defined, a gate formed at a predetermined portion on an active region of the substrate, a dummy poly layer formed on the device isolation region, And sidewalls and dummy polysidewalls formed on sides of the gate and the dummy polylayer, respectively, and source / drain defined on substrates corresponding to both sides of the gate and the sidewall, and contact electrodes contacting each of the source / drain. And the source / drain and the contact electrodes are self-aligned by the dummy poly sidewalls and sidewalls.

The source / drain and the contact electrodes are self-aligned by the dummy poly sidewalls and sidewalls.

The gate and source / drain surfaces are silicided.

An LDD region is further formed on the surface of the substrate except for the lower portion of the gate.

In addition, the manufacturing method of the MOS transistor of the present invention for achieving the same object comprises the steps of preparing a substrate in which the active region and the device isolation region is defined, by depositing polysilicon on the entire surface of the substrate to gate the predetermined region of the active region Forming a dummy poly layer on the device isolation region, doping a low concentration impurity into the substrate using the gate as a mask to form an LDD region, and forming a sidewall on the side of the gate, Forming a dummy poly sidewall on a side of the dummy poly layer, doping an impurity into the substrate using the gate and the sidewall as a mask to form a source / drain, and a contact electrode in contact with each of the source / drain There is another feature in that it comprises a step of forming.                     

The forming of the contact electrode may include depositing an interlayer insulating film on the entire surface of the substrate including the gate, selectively removing the source / drain top to form a contact hole, and filling a contact electrode in the contact hole. Is done.

After forming the sidewalls and the dummy polysidewalls, silicides of exposed source / drain and gate surfaces.

Hereinafter, with reference to the accompanying drawings will be described in detail the MOS transistor of the present invention and a manufacturing method thereof.

2 is a plan view showing a MOS transistor of the present invention.

As shown in FIG. 2, the MOS transistor of the present invention includes a substrate 100 in which an element isolation region and an active region are defined, a gate 105a formed at a predetermined portion on an active region of the substrate 100, and an element isolation region. A dummy poly layer 105b formed on the sidewalls, side wall spacers 106a and dummy poly side wall spacers formed on sides of the gate 105a and the dummy polylayer 105b, respectively. 106b and a contact electrode contacting each of the source / drain 102 and the source / drain 102 defined on the substrate 100 corresponding to both sides of the gate 105a and the sidewall spacer 106a. 108).

Here, the substrate 100 is defined by dividing the device isolation region for isolation between the plurality of devices formed on the substrate 100 and the active region in which the device is formed. In the device isolation region, a device isolation film 101 made of a trench type insulating film is formed.

In addition, the source / drain 102 and the gate 105a are polysilicon layers of the same type and are heavily doped, and silicides 107a and 107b are formed on the surface to reduce contact resistance with metal. It is. In the same silicide formation process, the dummy poly silicide 107c is also formed on the upper surface of the dummy poly layer 105b.

In addition, an LDD region 103 connected to the source / drain 102 is formed on a surface of the substrate 100 corresponding to both sides of the gate 105a. The formation of the LDD region 103 is to reduce the electric field between the drain and the channel region, thereby reducing the injection into the gate insulating film 104, collision ionization and other thermoelectric effects. In both substrates 100 of the gate 105a and the sidewall spacers 106a at both sides thereof, the source / drain 102 including such LDD regions 103 is doped with a high concentration of impurities to a relatively deeper depth. Is formed.

Since the source / drain silicide 107a is defined in a region between the sidewall spacer 106a and the dummy poly sidewall spacer 106b, the source / drain 102 of the substrate 100 is formed before the contact electrode is formed. In the region, the source / drain silicide 107a and the dummy poly sidewall spacer 106b are exposed at the side of the source / drain silicide 107a. Accordingly, the contact electrode 108 corresponding to the source / drain 102 region of the substrate 100 is in contact with the source / drain silicide 107a and some dummy poly sidewall spacers 106b like the B region. Because of the self-aligned, spiking does not occur in the contact region, and no leakage current flows from the contact electrode 108 to the substrate 100.

That is, the sidewall spacers 106a and the dummy poly sidewall spacers 106b are used as an etch preventing layer when forming contact holes of an interlayer insulating layer (not shown) for forming the contact electrode 108, thereby preventing misalignment of contact holes or the like. Even if a critical dimension (CD) variation occurs, contact spiking occurs between the silicon substrate 100 and the device isolation layer 101 at the time of forming the contact hole. The contact design rule can be further tightened, and the area occupied by one MOS transistor can be further reduced.

Meanwhile, a gate insulating film 104 is formed between the gate 105a and the substrate 100 to maintain insulation between the gate 105a and the substrate 100.

3 is a plan view illustrating a semiconductor device including the MOS transistor of FIG. 2.

As shown in FIG. 3, each of the two MOS transistors is isolated from each other by an element isolation film (see 101 in FIG. 2 and positioned under the dummy poly layer 105b).

The gates 105a of the two MOS transistors are spaced apart from each other and formed in parallel to each other, and source / drain 102 is formed at both sides of each gate 105a, and each source / drain 102 has a contact electrode ( 108 is in contact with the surface.

In addition, a dummy poly layer 105b of polysilicon having the same component is formed on the device isolation layer 101 on the same layer as the gate 105a. As such, by designing to have a predetermined overlap with the dummy poly layer 105b and the device isolation film 101, contact spiking is performed between the silicon substrate 100 and the device isolation film 101. Even when misalignment occurs or critical dimensional variation of the contact hole occurs when forming the hole, the self-alignment of the contact hole is possible between the source / drain 102 of the substrate 100 and the side wall spacer and the dummy side wall spacer. Therefore, contact spikes can be prevented from occurring at the source and contact design rules can be tighter, thereby reducing the area occupied by one transistor.

Although not shown in the drawings, sidewall spacers and dummy polysidewall spacers are formed on both sides of each gate 105a and the dummy polylayer 105b.

Hereinafter, a manufacturing method of a MOS transistor of the present invention will be described with reference to the accompanying drawings.

4A to 4G are cross-sectional views illustrating a method of manufacturing the MOS transistor of the present invention.

As shown in FIG. 4A, a substrate 100 made of silicon is prepared. At this time, the silicon substrate is crystallized polysilicon.

Subsequently, the predetermined region of the substrate 100 is removed in a trench shape, and then an insulating film is filled in this portion to form the device isolation film 101. At this time, the formation of the device isolation layer 101 allows the substrate 100 to be divided into an isolation region in which the isolation layer 101 is formed and an active region in which the isolation layer 101 is not formed. Will be formed.

As shown in FIG. 4B, the substrate 100 sequentially deposits a gate insulating film 104 and a heavily doped polysilicon layer 105a and 105b on the entire surface.

Subsequently, the polysilicon layer and the gate insulating layer 104 are selectively removed to form the gate 105a and the dummy poly layer 105b in the device isolation region in the active region of the predetermined region, and the gate insulating layer 104 has the same width. ).

Here, a high concentration of impurities are doped into a predetermined type (n + or p +) of the gate 105a.

Subsequently, a lightly doped drain (LDD) region 103 is formed by doping the substrate 100 with a low concentration of impurities using the gate 105a as a mask. The impurity type doped in the LDD region 103 is a low concentration type impurity of the same type as the impurity of the gate 105a.

As shown in FIG. 4C, an insulating film 106 for forming side wall spacers is deposited on the entire surface of the substrate 100 including the gate 105a.

As shown in FIG. 4D, the sidewall spacer forming insulating layer 106 is selectively removed to form sidewall spacers 106a on the side of the gate 105a, and dummy polysides on the side of the dummy polylayer 105b. The wall spacer 106b is formed.

Subsequently, the source / drain 102 is defined on the exposed surface of the substrate 100 by doping a high concentration of impurities using the gate 105a, the sidewall spacer 106a, and the dummy poly sidewall spacer 106b as a mask. In this case, the type of the high concentration impurity is the same as the impurity of the gate 105a, and in the doping process is adjusted to be deeper than the doped depth compared to the LDD region 103 to implant the impurity.

As shown in FIG. 4E, the surfaces of the source / drain 102, the gate 105a, and the dummy polylayer 105b that are exposed and doped with high concentration impurities of the same type are reacted with a high melting point metal or a radical. After the heat treatment, the source / drain silicide 107a, the gate silicide 107b, and the dummy poly silicide 107c are formed.

As shown in FIG. 4F, an interlayer insulating layer 110 is deposited on the entire surface of the substrate 100 including the gate 105a and the dummy polylayer 105b on which silicides 107a, 107b, and 107c are formed. And selectively remove the source / drain 102 to expose the contact hole 109.

When the contact hole 109 is formed, an etching process of the interlayer insulating layer 110 is performed. At this time, the dummy poly sidewall spacer 106b formed at the side of the dummy poly layer 105b serves as an etch stop layer. And self-aligned to prevent exposure of the substrate 100.

As shown in FIG. 4G, an electrode material is filled in the contact hole 109 to form a contact electrode 108 in contact with the source / drain 102 of the substrate 100.

4F and 4G, the multilayer wiring in contact with the contact electrode 108 is formed. When the single MOS transistor is formed on the substrate 100, the interlayer insulating layer 110 is deposited. Instead, the gate silicide 107b may be directly exposed to the surface.                     

The impurities doped in the source / drain 102, the gate 105a, and the LDD region 103 described above are an impurity layer of the same type of n + or p +.

The MOS transistor of the present invention as described above and a manufacturing method thereof have the following effects.

First, contact spiking can be prevented from occurring between the silicon substrate and the STI, thereby improving junction leakage properties.

Second, self-aligned contacts can be formed, making the contact design rule tighter, further reducing the area occupied by one transistor.

Claims (7)

A substrate on which device isolation regions and active regions are defined; A gate formed at a predetermined portion on an active region of the substrate; A dummy poly layer formed on the device isolation region; Side walls and dummy poly side walls respectively formed on the gate and the dummy poly layer sides; Source / drain defined on substrates corresponding to both sides of the gate and the sidewall; And And contact electrodes in contact with the source / drain, respectively, wherein the source / drain and the contact electrodes are self-aligned by the dummy poly sidewall and the sidewall. delete The method of claim 1, And the gate and source / drain surfaces are silicided. The method of claim 1, And a LDD region is further formed on the surface of the substrate except for the lower portion of the gate. Preparing a substrate on which active regions and device isolation regions are defined; Depositing polysilicon on the entire surface of the substrate to form a gate at a predetermined portion of the active region and to form a dummy poly layer on the device isolation region; Forming an LDD region by doping a low concentration impurity into the substrate using the gate as a mask; Forming sidewalls on the side of the gate and forming dummy polysidewalls on the side of the dummy polylayer; Forming a source / drain by doping the substrate with the gate and the sidewall as a mask; And And forming a contact electrode in contact with each of the sources / drains. The method of claim 5, Forming the contact electrode Depositing an interlayer insulating film on the entire surface of the substrate including the gate and selectively removing an upper portion of the source / drain to form a contact hole; And And burying a contact electrode in the contact hole. The method of claim 5, And after forming the sidewalls and the dummy polysidewalls, silicidating the exposed source / drain and gate surfaces.

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