KR100469149B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100469149B1
KR100469149B1 KR1019970081385A KR19970081385A KR100469149B1 KR 100469149 B1 KR100469149 B1 KR 100469149B1 KR 1019970081385 A KR1019970081385 A KR 1019970081385A KR 19970081385 A KR19970081385 A KR 19970081385A KR 100469149 B1 KR100469149 B1 KR 100469149B1
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gate
film
semiconductor substrate
pattern
plug
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KR19990061131A (en
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박효식
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함) 구조를 구비하는 반도체소자의 제조방법에 관한 것으로, 게이트용 고농도 불순물이 도핑된 다결정실리콘막과 그 측벽에 형성되는 불순물이 도핑되지 않은 다결정실리콘막 스페이서 사이에 측벽 절연막을 형성한 후, 소오스/드레인영역의 반도체 기판과 접촉되는 플러그를 고농도 불순물이 도핑된 다결정실리콘막 패턴으로 형성함으로서 게이트용 다결정실리콘막과 플러그용 다결정실리콘막 사이의 누설전류를 억제하며, 소오스/드레인 전극간의 펀치를 억제하여 소자의 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a structure of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET), wherein the polysilicon film doped with a high concentration impurity for a gate is formed on a sidewall thereof After the sidewall insulating film is formed between the polysilicon film spacers which are not doped with impurities, the polysilicon film for the gate and the plug are formed by forming a plug contacting the semiconductor substrate in the source / drain region with a polysilicon film pattern doped with a high concentration of impurities. The present invention relates to a technique for suppressing leakage current between polysilicon films and suppressing punches between source and drain electrodes to improve device reliability.

Description

반도체소자의 제조방법 Manufacturing method of semiconductor device

본 발명은 MOSFET 구조를 구비하는 반도체소자의 제조방법에 관한 것으로, 특히 다결정실리콘막 스페이서를 이용하여 게이트용 다결정실리콘막과 플러그용 다결정실리콘막 사이의 누설전류를 억제하고, 소오스/드레인의 펀치를 억제하는 트랜지스터를 형성함으로서 소자의 전기적 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a MOSFET structure. In particular, a polysilicon film spacer is used to suppress leakage current between a gate polysilicon film and a plug polysilicon film, and to eliminate source / drain punches. The present invention relates to a technique for improving the electrical characteristics and reliability of a device by forming a suppressing transistor.

반도체의 집적도가 높아짐에 따라 소자의 트랜지스터의 크기도 점점 작아지고 있고, 소자동작영역도 작아짐에 따라 트랜지스터의 제조방법도 다양해지고 있다.As the degree of integration of semiconductors increases, the size of transistors of devices becomes smaller and smaller, and the method of manufacturing transistors also increases as the device operating area becomes smaller.

반도체 디바이스는 수 많은 PMOS 트랜지스터와 NMOS 트랜지스터로 구성되어 있으며, 높은 구동능력을 위해 MOSFET의 문턱전압(threshold)이 제로에 가까운 것이 소자의 우수한 특성을 갖는다.The semiconductor device is composed of many PMOS transistors and NMOS transistors, and the MOSFET's threshold voltage is near zero for high driving capability.

또한, 일반적인 CMOS 로직 회로에서는 PMOS 트랜지스터를 " 하이(high) " 데이터를 읽고 쓰는데 사용하여 높은 전류구동 능력을 위해서는 가능한한 PMOS 트랜지스터의 문턱전압을 낮게 가져가야 한다.In addition, in conventional CMOS logic circuits, PMOS transistors are used to read and write "high" data, so the threshold voltage of the PMOS transistors should be as low as possible for high current drive capability.

도 1a 내지 도 1d 는 종래 기술에 따른 반도체소자의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.

먼저, 반도체 기판(10) 상부에 게이트산화막(12)과 게이트용 다결정실리콘막(14), 실리사이드막(16), 마스크용 산화막(18), 질화막(20)을 순차적으로 형성한후, 게이트용 마스크를 식각마스크로 하여 상기 질화막(20)에서 다결정실리콘막(14)까지 식각하여 반도체 기판(10)을 노출시켜 질화막(20)패턴과, 마스크용 산화막(18)패턴, 실리사이드막(16)패턴이 적층되며 다결정실리콘막(14)패턴과 게이트산화막(12)패턴으로된 게이트전극을 순차적으로 형성한다.First, the gate oxide film 12, the gate polycrystalline silicon film 14, the silicide film 16, the mask oxide film 18, and the nitride film 20 are sequentially formed on the semiconductor substrate 10. Using the mask as an etch mask, the nitride film 20 is etched from the nitride film 20 to the polysilicon film 14 to expose the semiconductor substrate 10 to expose the nitride film 20 pattern, the mask oxide film 18 pattern, and the silicide film 16 pattern. The gate electrodes are stacked and sequentially formed of the polysilicon film 14 pattern and the gate oxide film 12 pattern.

그 다음, 상기 노출되어있는 반도체기판(10)에 저농도 임플란트 공정을 실시하여 상기 게이트전극 양측의 반도체 기판(10)에 저농도 확산영역(22)을 형성한 후, 전표면에 스페이서용 산화막(24)을 형성한다.(도 1a 참조).Next, a low concentration implantation process is performed on the exposed semiconductor substrate 10 to form a low concentration diffusion region 22 in the semiconductor substrate 10 on both sides of the gate electrode, and then the spacer oxide film 24 on the entire surface. (See FIG. 1A).

다음, 상기 스페이서용 산화막(24)을 전면식각하여 상기 패턴(20, 18, 16, 14, 12) 측벽에 절연 스페이서(26)를 형성한 후, (도 1b 참조), 상기 노출되어 있는 반도체기판(10)에 고농도 임플란트 공정을 실시하여 상기 절연 스페이서(26) 양측의 저농도 확산영역(22)과 중첩되는 고농도 확산영역(28)을 형성하고, 상기 구조의 전표면에 플러그용 고농도의 폴리실리콘막(30)과 플러그 패턴닝 마스크인 감광막패턴(32)을 순차적으로 형성한다.(도 1c 참조).Next, after forming the insulating spacer 26 on the sidewalls of the patterns 20, 18, 16, 14, and 12 by etching the spacer oxide layer 24 on the entire surface (see FIG. 1B), the exposed semiconductor substrate is formed. A high concentration implantation process is performed on (10) to form a high concentration diffusion region 28 overlapping the low concentration diffusion region 22 on both sides of the insulating spacer 26, and a high concentration polysilicon film for the plug on the entire surface of the structure. 30 and the photosensitive film pattern 32 which is a plug patterning mask are formed sequentially (refer FIG. 1C).

다음, 상기 감광막패턴(32)을 마스크로 이용하여 상기 질화막(20) 상부 표면이 노출될때 까지 식각하여 플러그용 폴리실리콘막(28)패턴을 형성한다.(도 1d 참조)Next, the photosensitive film pattern 32 is used as a mask to be etched until the upper surface of the nitride film 20 is exposed to form a polysilicon film 28 for plugs (see FIG. 1D).

상기와 같은 종래 기술에 따르면 다음과 같은 문제점이 발생된다.According to the prior art as described above the following problems occur.

첫째, 게이트용 폴리실리콘막과 플러그용 폴리실리콘막 측벽의 스페이서 공간에 있어서 마스크 산화막 아래부분(A)이 다른 부분 보다 상대적으로 가까워 상호간 누설전류가 많이 흐를 수 있게 된다.First, in the spacer space between the sidewalls of the gate polysilicon film and the plug polysilicon film, the lower portion A of the mask oxide film is relatively closer than the other portions so that a large amount of leakage current flows.

둘째, 플러그용 폴리실리콘막이 도핑되면서 증착되기 때문에 후속 공정의 열처리 공정을 거치면서 반도체 기판의 아래 부분이 자동적으로 도핑되는데, 이 때 과도하게 확산이 일어나면 소자의 크기가 미세화되면서 소오스와 드레인간의 펀치현상이 발생하므로서 소자의 신뢰성이 저하되는 문제점이 발생된다.Second, since the polysilicon layer for the plug is deposited while being doped, the lower part of the semiconductor substrate is automatically doped during the heat treatment process in a subsequent process. When excessive diffusion occurs, the size of the device becomes smaller and the punch phenomenon between the source and the drain occurs. This causes a problem that the reliability of the device is lowered.

이에, 본 발명은 상기한 문제점들을 해결하기 위한 것으로 게이트용 고농도 불순물이 도핑된 다결정실리콘막과 그 측벽에 형성되는 불순물이 도핑되지 않은 다결정실리콘막 스페이서 사이에 측벽 절연막을 형성한 후 소오스/드레인 전극의 반도체 기판에 플러그용 고농도 불순물이 도핑된 다결정실리콘막을 형성함으로서 게이트용 다결정실리콘막과 플러그용 다결정실리콘막 사이의 누설전류를 억제하며, 소오스/드레인 전극간의 펀치를 억제하여 소자의 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems, and after forming the sidewall insulating film between the polysilicon film doped with a high concentration impurity for the gate and the polysilicon film spacer not doped with the impurities formed on the sidewall, the source / drain electrode By forming a polysilicon film doped with a high concentration impurity for a plug on a semiconductor substrate of the present invention to suppress the leakage current between the gate polysilicon film and the plug polycrystalline silicon film, and to suppress the punch between the source and drain electrodes to improve the reliability of the device Its purpose is to provide a method for manufacturing a semiconductor device.

상기 목적을 달성하기 위해 본 발명에 따르면,According to the present invention to achieve the above object,

반도체 기판 상부에 형성되어 있는 게이트 산화막상에 도전층패턴과 마스크절연막 패턴 및 식각장벽층 패턴의 적층구조로 이루어진 게이트를 형성하는 공정과,Forming a gate having a stacked structure of a conductive layer pattern, a mask insulating film pattern, and an etch barrier layer pattern on the gate oxide film formed on the semiconductor substrate;

상기 게이트 양측의 반도체 기판에 저농도 확산영역을 형성하는 공정과,Forming a low concentration diffusion region in the semiconductor substrate on both sides of the gate;

상기 구조의 전표면에 측벽용 절연막과 도핑되지 않은 다결정실리콘층을 순차적으로 형성하는 공정과,Sequentially forming a sidewall insulating film and an undoped polysilicon layer on the entire surface of the structure;

상기 다결정실리콘층을 식각하여 게이트의 측벽에 스페이서를 형성하는 공정과,Etching the polysilicon layer to form a spacer on a sidewall of the gate;

상기 스페이서에 의해 노출되어 있는 반도체 기판 표면 및 게이트 상부의 측벽용 절연막을 제거하여 식각장벽층 패턴과 반도체기판을 노출시키는 측벽용 절연막 패턴을 형성하는 공정과,Removing the surface of the semiconductor substrate exposed by the spacer and the sidewall insulating film over the gate to form an etch barrier layer pattern and a sidewall insulating film pattern exposing the semiconductor substrate;

상기 측벽용 절연막 패턴 양측의 반도체 기판에 저농도 확산영역과 중첩되는 고농도 확산영역을 형성하는 공정과,Forming a high concentration diffusion region overlapping the low concentration diffusion region in the semiconductor substrate on both sides of the sidewall insulating film pattern;

상기 구조의 전표면에 플러그용 도전층을 형성하는 공정과,Forming a conductive layer for a plug on the entire surface of the structure;

상기 플러그용 도전층을 패턴닝하여 반도체기판과 접촉되고 상기 식각장벽층 패턴상에도 남아 있는 플러그를 형성하는 공정을 구비하는 것을 특징으로 한다. And patterning the plug conductive layer to form a plug in contact with the semiconductor substrate and remaining on the etch barrier layer pattern.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e 는 본 발명에 따른 모스 전계효과 트랜지스터의 제조공정도이다.2A to 2E are manufacturing process diagrams of a MOS field effect transistor according to the present invention.

먼저, 반도체 기판(50) 상부에 게이트산화막(52)과 게이트용 도전층인 다결정실리콘막(54), 트랜지스터의 저항을 낮추기 위해 실리사이드막으로 구성된 도전층(56), 산화막으로 구성된 마스크용 제 1절연막(58), 질화막으로 구성된 식각장벽용 제 2절연막(60)을 순차적으로 형성한다. 이 때, 상기 다결정실리콘막(54)은 불순물이 고농도로 도핑되어 있다.First, a gate oxide film 52 and a polysilicon film 54 serving as a gate conductive layer on the semiconductor substrate 50, a conductive layer 56 made of a silicide film to lower the resistance of the transistor, and a mask made of an oxide film. An etching barrier second insulating film 60 composed of an insulating film 58 and a nitride film is sequentially formed. At this time, the polysilicon film 54 is doped with a high concentration of impurities.

다음, 게이트용 마스크를 식각마스크로 반도체 기판(50)이 노출될 때까지 순차적으로 패턴닝하여 마스크용 제 2절연막(60)패턴과, 제 1절연막(58)패턴 및 도전층(56)패턴으로 적층되어 게이트가 되는 다결정실리콘막(54)패턴과 게이트산화막(52)패턴을 순차적으로 형성한다.Next, the gate mask is sequentially patterned until the semiconductor substrate 50 is exposed as an etch mask, and thus the second insulating film 60 pattern, the first insulating film 58 pattern, and the conductive layer 56 pattern are formed. The polysilicon film 54 pattern and the gate oxide film 52 pattern which are stacked and formed as gates are sequentially formed.

그 다음, 상기 구조의 전표면에 저농도 이온주입공정을 실시하여 상기 게이트 양측의 반도체 기판(50)에 저농도 확산영역(62)을 형성한다.Next, a low concentration ion implantation process is performed on the entire surface of the structure to form a low concentration diffusion region 62 in the semiconductor substrate 50 on both sides of the gate.

다음, 게이트(60, 58, 56, 54, 52)를 감싸는 산화막 재질의 측벽용 제 3절연막(64)과 도핑되지 않은 다결정실리콘막(66)을 순차적으로 형성한다.(도 2a 참조).Next, the third insulating film 64 for the side wall of the oxide film material surrounding the gates 60, 58, 56, 54, and 52 and the undoped polysilicon film 66 are sequentially formed (see FIG. 2A).

그 다음, 다결정실리콘막(66)을 전면 식각하여 상기 측벽용 절연막(64)의 측벽에 다결정실리콘 스페이서(68)를 형성한다. 이 때, 다결정실리콘 스페이서(68)는 상기 게이트용 고농도 불순물이 도핑된 다결정실리콘막(54)과 후속 공정의 플러그 용 고농도 불순물이 도핑된 다결정실리콘막과의 과도한 확산에 의해 발생하는 누설전류을 억제하는 역할을 한다.(도 2b 참조)Then, the polysilicon film 66 is etched entirely to form the polysilicon spacers 68 on the sidewalls of the sidewall insulating film 64. At this time, the polysilicon spacer 68 suppresses leakage current caused by excessive diffusion between the polysilicon film 54 doped with the high concentration impurity for the gate and the polysilicon film doped with the high concentration impurity for the plug of a subsequent process. Role (see Figure 2b).

다음, 다결정실리콘 스페이서(68)를 식각장벽 마스크로 이용한 식각공정으로 마스크용 제 2절연막(60)패턴의 상부 표면과 반도체 기판(50)이 노출되는 측벽용 절연막(64) 패턴을 형성한다.(도 2c 참조)Next, in the etching process using the polysilicon spacer 68 as an etch barrier mask, an upper surface of the mask second insulating film 60 pattern and a sidewall insulating film 64 pattern in which the semiconductor substrate 50 is exposed are formed. See FIG. 2C)

그 다음, 상기 구조의 전표면에 고농도 이온주입공정을 실시하여 상기 측벽용 절연막(64) 패턴 양측의 반도체 기판(50)에 저농도 확산영역(62)과 중첩되는 고농도 확산영역(70)을 형성하여 소오스/드레인 영역을 형성한 후, 상기 구조의 전표면에 고농도 불순물이 도핑된 다결정실리콘막으로 구성된 플러그용 도전층(72)을 형성하고, 상기 플러그용 도전층(72)을 패턴닝하기 위한 감광막패턴(74)을 형성한다. (도 2d 참조).Next, a high concentration ion implantation process is performed on the entire surface of the structure to form a high concentration diffusion region 70 overlapping the low concentration diffusion region 62 on the semiconductor substrate 50 on both sides of the sidewall insulating film 64 pattern. After forming the source / drain regions, a plug conductive layer 72 made of a polysilicon film doped with a high concentration of impurities is formed on the entire surface of the structure, and a photosensitive film for patterning the plug conductive layer 72 is formed. The pattern 74 is formed. (See FIG. 2D).

그 다음, 상기 감광막패턴(74)을 마스크로 상기 마스크용 제 2절연막(60)패턴이 노출되는 도전층(72) 패턴으로된 플러그를 형성한다. (도 2e 참조).Next, a plug is formed using the photosensitive film pattern 74 as a mask to form a conductive layer 72 pattern through which the mask second insulating film 60 pattern is exposed. (See FIG. 2E).

상기한 바와같이 본 발명에 따르면, 도핑되지 않은 다결정실리콘 스페이서를 사용하여 게이트용 다결정실리콘막과 플러그용 다결정실리콘막 사이의 누설전류를 억제하고, 소오스/드레인의 펀치를 억제하는 트랜지스터를 형성함으로서 다음과 같은 이점이 있다.As described above, according to the present invention, by using a undoped polysilicon spacer to suppress the leakage current between the gate polysilicon film and the plug polycrystalline silicon film, by forming a transistor to suppress the punch of the source / drain This has the same advantages.

첫째, 게이트 측벽의 산화막이 상대적으로 얇은 부분이 없어져 게이트용 다결정실리콘막과 플러그용 다결정실리콘막 사이에 발생되는 누설 전류가 흐를 수 있는 취약한 부분을 제거할 수 있다.First, a relatively thin portion of the oxide film on the sidewall of the gate may be removed, thereby removing a weak portion where leakage current generated between the gate polysilicon film and the plug polysilicon film may flow.

둘째, 게이트에서 소오스/드레인이 되는 반도체 기판에서의 다결정실리콘막이 종래 보다 멀어지기 때문에 펀치현상을 방지할 수 있다.Second, the punch phenomenon can be prevented because the polysilicon film in the semiconductor substrate, which becomes the source / drain at the gate, is farther away than before.

셋째, 다결정실리콘 스페이서가 고농도로 도핑된 게이트용 다결정실리콘막과플러그용 다결정실리콘막의 과도한 확산을 막아주기 때문에 게이트용 다결정실리콘막과 소오스/드레인 영역의 플러그용 다결정실리콘막과의 누설전류를 억제할 수 있어 소자의 전기적 특성 및 신뢰성을 향상시키는 이점이 있다.Third, because the polysilicon spacer prevents excessive diffusion of the heavily doped gate polysilicon film and the plug polycrystalline silicon film, the leakage current between the gate polycrystalline silicon film and the plug / silicon film for the plug in the source / drain region can be suppressed. There is an advantage to improve the electrical characteristics and reliability of the device.

도 1a 내지 도 1d 는 종래 기술에 따른 반도체소자의 제조공정도.1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.

도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 제조공정도.2a to 2e is a manufacturing process diagram of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10, 50 : 반도체 기판 12, 52 : 게이트산화막10, 50: semiconductor substrate 12, 52: gate oxide film

14, 54 : 다결정실리콘막 16 : 실리사이드막14, 54 polysilicon film 16: silicide film

18 : 마스크용 산화막 20 : 질화막18: oxide film for mask 20: nitride film

22, 62 : 저농도 확산영역 24 : 스페이서용 산화막22, 62: low concentration diffusion region 24: oxide film for spacer

26 : 절연 스페이서 28, 70 : 고농도 확산영역26: insulation spacer 28, 70: high concentration diffusion region

30 : 플러그용 다결정실리콘막 32, 74 : 감광막패턴30 polysilicon film for plug 32, 74 photosensitive film pattern

56 : 도전층 58 : 마스크용 제 1절연막56 conductive layer 58 first insulating film for mask

60 : 마스크용 제 2절연막 64 : 측벽용 절연막60: second insulating film for mask 64: insulating film for sidewall

66 : 다결실리콘막 68 : 다결정실리콘막 스페이서66: polycrystalline silicon film 68: polycrystalline silicon film spacer

72 : 플러그용 도전층 72: plug conductive layer

Claims (2)

반도체 기판 상부에 형성되어 있는 게이트 산화막상에 도전층패턴과 마스크절연막 패턴 및 식각장벽층 패턴의 적층구조로 이루어진 게이트를 형성하는 공정과,Forming a gate having a stacked structure of a conductive layer pattern, a mask insulating film pattern, and an etch barrier layer pattern on the gate oxide film formed on the semiconductor substrate; 상기 게이트 양측의 반도체 기판에 저농도 확산영역을 형성하는 공정과,Forming a low concentration diffusion region in the semiconductor substrate on both sides of the gate; 상기 구조의 전표면에 측벽용 절연막과 도핑되지 않은 다결정실리콘층을 순차적으로 형성하는 공정과,Sequentially forming a sidewall insulating film and an undoped polysilicon layer on the entire surface of the structure; 상기 다결정실리콘층을 식각하여 게이트의 측벽에 스페이서를 형성하는 공정과,Etching the polysilicon layer to form a spacer on a sidewall of the gate; 상기 스페이서에 의해 노출되어 있는 반도체 기판 표면 및 게이트 상부의 측벽용 절연막을 제거하여 식각장벽층 패턴과 반도체기판을 노출시키는 측벽용 절연막 패턴을 형성하는 공정과, Removing the surface of the semiconductor substrate exposed by the spacer and the sidewall insulating film over the gate to form an etch barrier layer pattern and a sidewall insulating film pattern exposing the semiconductor substrate; 상기 측벽용 절연막 패턴 양측의 반도체 기판에 저농도 확산영역과 중첩되는 고농도 확산영역을 형성하는 공정과,Forming a high concentration diffusion region overlapping the low concentration diffusion region in the semiconductor substrate on both sides of the sidewall insulating film pattern; 상기 구조의 전표면에 플러그용 도전층을 형성하는 공정과,Forming a conductive layer for a plug on the entire surface of the structure; 상기 플러그용 도전층을 패턴닝하여 반도체기판과 접촉되고 상기 식각장벽층 패턴상에도 남아 있는 플러그를 형성하는 공정을 구비하는 반도체소자의 제조방법.Patterning the plug conductive layer to form a plug in contact with the semiconductor substrate and remaining on the etch barrier layer pattern. 제 1 항에 있어서, 상기 도전층 패턴과 상기 플러그용 도전층은 고농도 불순물이 도핑된 다결정실리콘막으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the conductive layer pattern and the plug conductive layer are formed of a polysilicon film doped with a high concentration of impurities.
KR1019970081385A 1997-12-31 1997-12-31 Manufacturing method of semiconductor device KR100469149B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443649A (en) * 1990-06-11 1992-02-13 Fujitsu Ltd Semiconductor device and its preparation
KR930003430A (en) * 1991-07-20 1993-02-24 김광호 Semiconductor device and manufacturing method thereof
JPH08330588A (en) * 1995-03-27 1996-12-13 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
KR970052859A (en) * 1995-12-29 1997-07-29 김광호 Method of manufacturing silicide semiconductor device
KR19990061128A (en) * 1997-12-31 1999-07-26 김영환 Manufacturing method of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443649A (en) * 1990-06-11 1992-02-13 Fujitsu Ltd Semiconductor device and its preparation
KR930003430A (en) * 1991-07-20 1993-02-24 김광호 Semiconductor device and manufacturing method thereof
JPH08330588A (en) * 1995-03-27 1996-12-13 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
KR970052859A (en) * 1995-12-29 1997-07-29 김광호 Method of manufacturing silicide semiconductor device
KR19990061128A (en) * 1997-12-31 1999-07-26 김영환 Manufacturing method of semiconductor device

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