KR100304283B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100304283B1 KR100304283B1 KR1019980035018A KR19980035018A KR100304283B1 KR 100304283 B1 KR100304283 B1 KR 100304283B1 KR 1019980035018 A KR1019980035018 A KR 1019980035018A KR 19980035018 A KR19980035018 A KR 19980035018A KR 100304283 B1 KR100304283 B1 KR 100304283B1
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- forming
- semiconductor substrate
- gate electrode
- groove
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 활성영역의 테두리 부분 안쪽에 경사진 측벽과 평탄한 저면을 가지는 홈을 형성하고, 상기 홈의 경사면에 게이트전극을 형성하며, 테두리 부분과 저면에 소오스/드레인영역을 형성하였으므로, 작은 면적에서도 게이트전극의 폭을 증가시킬 수 있어 짧은 채널효과가 방지되며, 콘택 제조시 접합 부분의 손상이 방지되어 누설전류가 감소되고, 소자의 고집적화에 유리하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a groove having an inclined sidewall and a flat bottom surface is formed inside an edge portion of an active region, a gate electrode is formed on an inclined surface of the groove, and a source is formed on the edge portion and the bottom surface. Since the / drain region is formed, the width of the gate electrode can be increased even in a small area, thereby preventing short channel effects, preventing damage to the junction portion during contact fabrication, thereby reducing leakage current, and conducive to high integration of the device.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 활성영역의 형상을 변경한 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함)를 형성하여 접합 깊이를 깊게 형성할 수 있어 접합 누설을 방지하고 채널길이를 증가시켜 짧은 채널 효과를 방지할 수 있어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) having a shape changed in an active region can be formed to deeply form a junction depth. The present invention relates to a method for manufacturing a semiconductor device that can prevent leakage and increase channel length to prevent short channel effects, thereby improving process yield and reliability of device operation.
반도체소자가 고집적화되어 감에 따라 소자의 크기를 감소시키기 위하여 MOSFET의 게이트전극이나 소오스/드레인영역 및 이들과의 콘택등 공정 전반의 디자인 룰이 감소되고 있으나, 채널폭의 감소는 문턱전압 감소와 트랜지스터 펀치를 유발하게 된다.As semiconductor devices become more integrated, the overall design rules such as gate electrodes, source / drain regions, and contacts with MOSFETs are reduced to reduce the size of the devices. Will cause a punch.
또한 p 또는 n형 반도체기판에 n 또는 p형 불순물로 형성되는 pn 접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 짧은채널효과(short channel effect)를 방지하기 위하여 채널이온주입과 소오스/드레인영역 이온주입시 에너지를 감소시켜 측면 확산을 방지하는데, 이때 접합깊이가 얕게 형성되어 소자의 동작 특성을 저하시킨다.In addition, a pn junction formed of n or p type impurity on a p or n type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in semiconductor devices with reduced channel width, energy is reduced during channel ion implantation and source / drain region ion implantation in order to prevent short channel effects caused by side diffusion from the diffusion region. At this time, the junction depth is formed to be shallow to reduce the operating characteristics of the device.
짧은 채널효과가 발생되면 게이트전극의 폭 변화에 대하여 문턱전압이 심하게 변화되어 문턱전압 조절이 어렵게되어 공정마진이 적어지는 문제점이 있다.When the short channel effect occurs, the threshold voltage is severely changed with respect to the width change of the gate electrode, which makes it difficult to control the threshold voltage, thereby reducing the process margin.
또한 소오스/드레인영역 상에 형성되는 콘택을 위한 에칭 공정시 기판 표면이 손상되는데, 폴리2난 폴리3 공정, 예를들어 전하저장전극이나 비트라인 콘택홀 형성 공정시 기판 손상에 의한 결합이 주로 얕은 접합 부분에 발생되어 접합 누설의 중요한 용인이 되는데, 이를 방지하기 위하여 플러그패드를 형성하는 방법을 사용하는데, 이 역시 콘택홀 형성시 기판이 손상되기는 마찬가지이고, 주변회로 영역에서도 금속배선 콘택의 경우에도 깊은 콘택 깊이 때문에 기판이 심하게 손상되며, 장벽금속인 Ti을 사용한 TiSix의 형성시에도 기판의 Si이 석출되므로 접합에서의 누설전류가 증가되는 문제점이 있다.In addition, the surface of the substrate is damaged during the etching process for the contacts formed on the source / drain regions. In the poly2 or poly3 process, for example, the bonding due to the damage of the substrate during the formation of the charge storage electrode or the bit line contact hole is mainly shallow. It occurs at the junction and is an important cause of leakage of the junction. In order to prevent this, a plug pad is used to prevent this. This also applies to damaging the substrate when forming the contact hole. Due to the deep contact depth, the substrate is severely damaged, and even when TiSix is formed using Ti as the barrier metal, Si of the substrate is precipitated, thereby increasing the leakage current at the junction.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본발명의 목적은 활성영역을 경사식각하여 MOSFET를 형성하여 얕은 접합을 깊게 형성할 수 있도록하여 접합 깊이에 따른 펀치 특성 저하를 방지하며 콘택 형성시 접합 부분에서의 기판 손상을 방지하여 접합 누설 특성을 향상시키며, 채널폭을 증가시켜 짧은 채널 효과를 방지하고 소자의 고집적화를 유리하게 할 수 있는 반도체소자의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a MOSFET by inclining the active area to form a shallow junction deep to prevent the punch characteristics deterioration according to the junction depth and at the time of contact formation It is to provide a method of manufacturing a semiconductor device that can prevent damage to the substrate in the junction portion to improve the junction leakage characteristics, increase the channel width to prevent short channel effects and advantageously high integration of the device.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체소자의 제조방법.1A to 1C illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10 : 반도체 기판 11 : 트랜치10 semiconductor substrate 11: trench
12 : 산화막 14 : 홈12: oxide film 14: groove
16 : 게이트절연막 18 : 도전층16 gate insulating film 18 conductive layer
20 : 감광막패턴 22 : 저농도 불순물영역20: photoresist pattern 22: low concentration impurity region
24 : 스페이서 26 : 고농도 불순물영역24 spacer 26 high concentration impurity region
상기와 같은 목적을 달성하기 위해 본 발명에 따른 반도체소자 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention to achieve the above object,
반도체기판의 소자분리 영역상에 트랜치 소자분리 방법으로 소자분리 영역을 정의하는 공정과,Defining a device isolation region by a trench device isolation method on the device isolation region of the semiconductor substrate;
상기 반도체기판의 활성영역에서 소오스/드레인영역으로 예정되어있는 부분을 제외한 반도체기판을 일정깊이 식각하여 홈을 형성하는 공정과,Forming a groove by etching the semiconductor substrate at a predetermined depth except for a portion of the semiconductor substrate which is intended as a source / drain region;
상기 홈 양측의 테두리 부분 내측의 반도체기판을 경사진 측벽과 평탄환한 저면을 가지도록 식각하는 공정과,Etching the semiconductor substrate inside the edge portions on both sides of the groove to have an inclined sidewall and a flat bottom surface;
상기 구조의 전표면에 게이트 절연막을 형성하는 공정과,Forming a gate insulating film on the entire surface of the structure;
상기 경사진 측벽의 게이트절연막상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the gate insulating film of the inclined sidewall;
상기 게이트전극 양측의 반도체기판에 저농도 불순물영역을 형성하는 공정과,Forming a low concentration impurity region in the semiconductor substrate on both sides of the gate electrode;
상기 게이트전극의 측벽에 절연 스페이서를 형성하는 공정과,Forming an insulating spacer on sidewalls of the gate electrode;
상기 스페이서 양측의 반도체기판에 고농도 불순물영역을 형성하는 공정을 구비함에 있다.And forming a high concentration impurity region in the semiconductor substrate on both sides of the spacer.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 미세패턴 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의일실시예에 따른 반도체소자의 제조공정도이다.1A to 1C are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.
먼저, 제1도전형, 예를들어 p형 실리콘 웨이퍼 반도체기판(10)에서 소자분리 영역으로 예정되어있는 부분상에 트랜치(11)를 형성하고 상기 트랜치(11)를 산화막(12)으로 메워 소자분리영역을 정의하고, 상기 소자분리영역에 의해 정의되는 활성영역의 테두리 부분을 보호하는 감광막패턴(도시되지 않음)을 형성하고, 상기 감광막패턴에 의해 노출되어있는 반도체기판(10)을 일정깊이, 예를들어 300∼1000Å 정도 깊이로 식각하여 홈(14)을 형성하고, 상기 감광막패턴을 제거한다. 여기서 홈(14) 보다 높은 테두리 부분의 폭은 소자의 소오스/드레인영역의 폭으로서 디자인 룰에 따라 결정한다.First, a trench 11 is formed on a portion of the first conductive type, for example, a p-type silicon wafer semiconductor substrate 10, which is intended as an isolation region, and the trench 11 is filled with an oxide film 12 to form a device. Defining a separation region, forming a photoresist pattern (not shown) to protect the edge portion of the active region defined by the device isolation region, the semiconductor substrate 10 exposed by the photoresist pattern is a predetermined depth, For example, the groove 14 is formed by etching to a depth of about 300 to 1000 mm, and the photoresist pattern is removed. Here, the width of the edge portion higher than the groove 14 is the width of the source / drain regions of the device and is determined according to the design rule.
그 다음 상기 홈(14) 부분의 반도체기판(10)을 식각하되, 측벽이 20∼50°정도로 경사지도록하고, 저면이 평탄부를 가지도록 일정깊이를 식각한다. 여기서 상기평탄부의 폭은 소오스/드레인영역으로서 디자인룰에 따라 결정되고, 경사각 또한 소자의 크기, 활성영역이나 소오스/드레인영역의 크기에 따라 결정한다. (도 1a 참조).Next, the semiconductor substrate 10 in the groove 14 is etched, the sidewalls are inclined at about 20 to 50 °, and a predetermined depth is etched so that the bottom surface has a flat portion. Here, the width of the flat portion is determined according to a design rule as a source / drain region, and an inclination angle is also determined according to the size of the element, the size of the active region or the source / drain region. (See FIG. 1A).
그후, 상기 구조의 전표면에 산화막이나 질화막 또는 산화막/질화막의 게이트절연막(16)을 형성하고, 상기 홈(14)의 경사진 측벽에 다결정실리콘이나 폴리사이드 구조의 도전층(18)을 형성하고, 상기 도전층(18)상에 게이트 패터닝 마스크인 감광막패턴(20)을 형성하고, 상기 감광막패턴(20)에 의해 노출되어있는 도전층(18)을 식각하여 도전층(18) 패턴으로된 게이트전극을 형성한다. 이때 상기 게이트전극은 평탄부상에도 형성할 수 있으며, 홈(14)의 테두리 부분과도 중첩되게 형성할 수 있다.Thereafter, an oxide film, a nitride film, or a gate insulating film 16 of an oxide film / nitride film is formed on the entire surface of the structure, and a conductive layer 18 of polycrystalline silicon or polyside structure is formed on the inclined sidewall of the groove 14. And forming a photoresist pattern 20 as a gate patterning mask on the conductive layer 18 and etching the conductive layer 18 exposed by the photoresist pattern 20 to form a conductive layer 18 pattern. Form an electrode. In this case, the gate electrode may be formed on the flat portion and may overlap the edge portion of the groove 14.
그다음 상기 게이트전극 양측의 반도체기판(10)에 n-저농도 불순물영역(22)을 형성하한다. (도 1b 참조).Then, n − low concentration impurity regions 22 are formed in the semiconductor substrate 10 on both sides of the gate electrode. (See FIG. 1B).
그후, 상기 게이트전극의 측벽에 산화막 재질의 절연 스페이서(24)를 형성한후, 상기 스페이서(24) 양측의 반도체기판(10)에 n+고농도 불순물영역(26)을 형성하여 소오스/드레인영역을 완성한다. (도 1c 참조).Thereafter, an insulating spacer 24 made of an oxide film is formed on sidewalls of the gate electrode, and then n + high concentration impurity regions 26 are formed on the semiconductor substrate 10 on both sides of the spacer 24 to form a source / drain region. Complete (See FIG. 1C).
상기와 같이 형성된 MOSFET는 소오스/드레인영역간의 거리가 멀게 형성되어 접합을 깊이 형성할 수도 있으며, 콘택홀 형성시 접합의 손상이 방지되어 접합 누설전류가 감소되고, 게이트전극의 폭을 넓게 형성할 수 있어 짧은 채널효과도 방지된다.The MOSFET formed as described above can form a deep junction by forming a distance between the source and drain regions, and prevent damage of the junction when forming a contact hole, thereby reducing junction leakage current and widening the width of the gate electrode. Short channel effects are also prevented.
상기에서 경사진 측벽을 가지는 홈을 형성하는 공정의 식각 마스크로서 감광막패턴을 사용하는 방법을 예로 들었으나, 홈이 될 부분을 노출시키는 마스크 산화막 패턴을 홈 형성의 식각 마스크로 사용하고 단계적으로 마스크 산화막 패턴의 측벽에 절연 스페이서를 형성하여 경사진 측벽을 형성할 수도 있으며, 감광막패턴의 에지 부분을 리플로우 방법이나 노광량 조절 등의 방법으로 측벽을 경사지게 형성할 수도 잇으며, 상기의 마스크 산화막을 질화막 패턴으로 하고 절연 스페이서를 질화막으로 형성하여 홈을 경사지게 할수도 있다.Although a method of using a photoresist pattern as an etch mask in the process of forming a groove having an inclined sidewall has been exemplified above, a mask oxide layer pattern exposing a portion to be a groove is used as an etching mask for groove formation, and a mask oxide layer is gradually formed. Insulating spacers may be formed on the sidewalls of the pattern to form inclined sidewalls, and the edge portions of the photoresist pattern may be formed to be inclined sidewalls by a reflow method or an exposure amount control method. The groove may be inclined by forming an insulating spacer as a nitride film.
상기한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 활성영역의 테두리 부분 안쪽에 경사진 측벽과 평탄한 저면을 가지는 홈을 형성하고, 상기 홈의 경사면에 게이트전극을 형성하며, 테두리 부분과 저면에 소오스/드레인영역을 형성하였으므로, 작은 면적에서도 게이트전극의 폭을 증가시킬 수 있어 짧은 채널효과가 방지되며, 콘택 제조시 접합 부분의 손상이 방지되어 누설전류가 감소되고, 소자의 고집적화에 유리한 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a groove having an inclined sidewall and a flat bottom surface is formed inside an edge portion of an active region, a gate electrode is formed on an inclined surface of the groove, and an edge portion and a bottom surface are formed. Since the source / drain regions are formed on the gate electrode, the width of the gate electrode can be increased even in a small area, thereby preventing short channel effects, preventing damage to the junction part during contact manufacturing, and reducing leakage current, which is advantageous for high integration of devices. There is this.
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