KR19990061128A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a silicide film pattern stacked on a semiconductor substrate and an oxide film pattern for a mask are sequentially formed on the semiconductor substrate, and an oxide film for spacers is formed on the entire surface thereof, and then the The polysilicon layer spacer is formed to form an oxide layer spacer having a double structure overlapping with the polysilicon layer spacer, and then a transistor is formed by forming a plug polysilicon layer pattern at a predetermined portion of the bit line and the source / drain electrode to form a transistor. The present invention relates to a technique for improving device characteristics by improving a spacing fail between a gate and an adjacent conductive layer using a spacer having a double structure made of a silicon film.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for improving device characteristics by improving a spacing failure between a conductive layer adjacent to a gate by using a spacer having a double structure consisting of an oxide film and a polysilicon film. will be.

As the degree of integration of semiconductors increases, the size of transistors of devices becomes smaller and smaller, and the method of manufacturing transistors also increases as the device operating area becomes smaller.

The semiconductor device is composed of many PMOS transistors and NMOS transistors, and the MOSFET's threshold voltage is near zero for high driving capability.

In addition, in general CMOS logic circuits, PMOS transistors are used to read and write high data, and the threshold voltage of the PMOS transistors should be as low as possible for the high current driving capability.

1A to 1F are manufacturing process diagrams of a semiconductor device according to the prior art, and are examples of manufacturing processes in N-MOS regions and P-MOS regions except memory cell regions.

First, a gate oxide film (not shown), a gate polysilicon film 12, a silicide film 14, and a mask oxide film 16 are sequentially formed on the semiconductor substrate 10.

Next, the gate mask is etched as an etch mask until the semiconductor substrate 10 is exposed, and the mask oxide layer 16 pattern and the silicide layer 14 pattern are stacked, and the polysilicon layer 12 pattern and the gate oxide layer pattern are formed. After sequentially forming the gate electrodes, a first oxide film 18 for spacers is formed on the entire surface thereof (see FIG. 1A).

Next, after the first polysilicon film for the spacer is formed on the first oxide film 18 for the spacer, the first polysilicon film for the spacer is etched and the first polysilicon film is formed on the sidewall of the first oxide film 18 for the spacer. The spacer 22 is formed (see FIG. 1B).

Next, a second polysilicon film 24 is formed to surround the upper surface of the first polysilicon film spacer 22 and the first oxide film 18 for the spacer (see FIG. 1C).

Next, the second polysilicon film 24 and the first polysilicon film spacer 22 are removed by dry etching until the first oxide film 18 for the spacer is exposed using a plug etching mask. (FIG. 1D). Reference)

Next, the first oxide film 18 for spacers is etched entirely with an N-type mask and a P-type mask, so that the first oxide spacers 26 are formed on the sidewalls of the mask oxide layer 16 pattern, the silicide layer 14 pattern, and the gate electrode. (See FIG. 1E).

Next, the polysilicon layer 28 and the photoresist pattern (not shown) for connecting the capacitor and the source / drain diffusion region or the bit line and the source / drain diffusion region are sequentially formed on the entire surface of the structure. Using the photoresist pattern as a mask, the photoresist pattern is etched until the upper surface of the mask oxide layer 16 pattern is exposed to form a polysilicon layer pattern 26 for plugs (see FIG. 1F).

According to the related art as described above, in the process of forming the memory cell region, the gate and the plug polysilicon film are insulated only by the spacer oxide film for the insulation between the gate polysilicon film and other conductors connected by the source / drain. .

At this time, when the thickness of the spacer oxide film is formed thin, the gap between the left and right edges of the upper gate and the plug-polysilicon film is formed to be considerably small. On the contrary, when the spacer oxide film is formed too thick, the plug in the source / drain diffusion region may be formed. -The contact area between the polysilicon films is small, and there is a problem in that the contact resistance increases when the highly integrated DRAM device is formed, thereby degrading device characteristics.

Accordingly, the present invention is to solve the above problems, and after forming the silicide film pattern and the mask oxide film pattern to be stacked with the gate electrode on the semiconductor substrate in sequence and the oxide film for the spacer on the entire surface, the spacer oxide film sidewall Polysilicon film spacers are formed on the double layer to form an oxide spacer having a double structure overlapping with the polysilicon film spacers, and then a plug polysilicon film pattern is formed at predetermined portions of the bit lines and the source / drain electrodes to form transistors. It is an object of the present invention to provide a method of manufacturing a semiconductor device that improves device characteristics by improving a spacing failure between a gate and an adjacent conductive layer by using a spacer having a double structure made of a polysilicon film.

1A to 1F are manufacturing process diagrams of a semiconductor device according to the prior art.

2a to 2d is a manufacturing process diagram of a semiconductor device according to the present invention

Explanation of symbols for the main parts of the drawings

10, 50: semiconductor substrate 12, 52: polysilicon film for gate

14, 54: silicide film 16, 56: oxide film for mask

18, 58: first oxide film for spacer 22, 62: first polysilicon film spacer

24: second polysilicon film 26: first oxide film spacer

28, 64: polysilicon film for plug

According to the present invention to achieve the above object,

Sequentially forming a silicide film pattern stacked on the semiconductor substrate and an oxide film pattern for a mask on the semiconductor substrate;

Forming an oxide film for a spacer on the entire surface of the structure;

Forming a polysilicon film spacer on the spacer oxide sidewall;

Forming an oxide film spacer having a dual structure overlapping with the polysilicon film spacer;

And forming a plug polysilicon film pattern on a predetermined portion of the bit line and the source / drain electrodes.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D illustrate an example of a process of forming a semiconductor cell in a memory cell region according to the present invention.

First, a gate oxide film (not shown), a gate polysilicon film 52, a silicide film 54, and a mask oxide film 56 are sequentially formed on the semiconductor substrate 50.

Next, the gate mask is etched as an etch mask until the semiconductor substrate 50 is exposed, and thus the mask oxide layer 56 pattern and the silicide layer 54 pattern are stacked to form the polysilicon layer 52 pattern and the gate oxide pattern. Gate electrodes are sequentially formed.

Then, an impurity ion implantation process is performed on the entire surface of the structure to form a source / drain diffusion region (not shown) in the semiconductor substrates on both sides of the gate electrode, and then an oxide film 58 for spacers is formed on the entire surface. (See Figure 2A)

Next, after the spacer polysilicon layer is formed on the spacer oxide layer 58, the polysilicon layer spacer 62 is formed on the sidewall of the spacer oxide layer 58 by a dry etching process without using a mask. To form.

At this time, the spacer polysilicon film 60 is formed to have a thickness of 200 to 400 kHz. (See Fig. 2B.)

Then, the spacer oxide film 58 is dry-etched with a mask that opens only the memory cell region, thereby forming a double spacer structure in which the polysilicon film spacer 62 and the spacer oxide film 58 overlap. 2c)

Next, a plug polysilicon layer 64 is formed on the entire surface of the structure to connect a capacitor and a source / drain diffusion region or a bit line and a source / drain diffusion region, and then, as an etching mask, the oxide layer for the spacer ( 58) Dry etching is performed until the top surface is exposed to form a polysilicon film 64 pattern for plugs.

At this time, the plug polysilicon layer 64 is formed at the portion connecting the capacitor and the source / drain diffusion region or the bit line and the source / drain diffusion region to form a gap between the left and right edges of the gate top and the plug-polysilicon layer. As the thickness of the oxide film is formed, the gap can be maintained as it is, so that structurally more complete insulation can be achieved.

Also, for the remaining portions except for the memory cell region, when the plug polysilicon film 64 is removed during dry etching using a photosensitive film pattern for the spacer polysilicon film and the plug polysilicon film 64, the spacer oxide film ( 58) can be formed (see FIG. 2D).

As a preferred embodiment of the present invention, in order to form an NMOS (or PMOS) transistor in an NMOS region or a PMOS region, only a specific region is opened and dry-etched by using an N-type (or P-type) source / drain mask. The spacer oxide film may be formed on the sidewall of the gate by performing an oxide film dry etching process.

At this time, As (or Bf ₂ ) ions are implanted into the N-type (or P-type) source / drain diffusion region and the photoresist film used as an etching and ion implantation barrier is removed.

As described above, according to the present invention, a spacer is used on a gate sidewall to enhance insulating properties between a gate polysilicon layer and another conductor connected to a source / drain in the process of forming a memory cell region in a DRAM semiconductor device. In addition to forming the dual structure, transistors can be formed in the conventional CMOS region except the memory cell region, thereby improving device characteristics and improving device reliability.

Claims (5)

Sequentially forming a silicide film pattern stacked on the semiconductor substrate and an oxide film pattern for a mask on the semiconductor substrate; Forming an oxide film for a spacer on the entire surface of the structure; Forming a polysilicon film spacer on the spacer oxide sidewall; Forming an oxide film spacer having a dual structure overlapping with the polysilicon film spacer; A method of manufacturing a semiconductor device comprising the step of forming a plug polysilicon film pattern on a predetermined portion of a bit line and a source / drain electrode. The method of claim 1, wherein the polysilicon film is formed to have a thickness of 200 to 400 GPa in the polysilicon film spacer. The method of claim 1, wherein the polysilicon layer spacer is formed by a dry etching process. The oxide dry etching method of claim 1, wherein when forming an NMOS (or PMOS) transistor in an NMOS region or a PMOS region, only a predetermined region is opened and dry-etched using an N-type (or P-type) source / drain mask. A process for producing a semiconductor device, comprising forming a spacer oxide film on a gate sidewall by performing a step. The method of claim 1 or 4, wherein As (or Bf ₂ ) ions are implanted into the N-type (or P-type) source / drain diffusion region, and a photoresist film used as an etching and ion implantation barrier is removed. Method of manufacturing a semiconductor device.