KR930001419B1 - Method of fabricating static ram cell - Google Patents

Abstract

The method for using a P-channel polysilicon MOS transistor as a resistor to reduce the resistance comprises the steps of applying and etching a first conduction layer onto a substrate to form first and second electrodes (17a,17b) to apply a first insulation film (19) thereon, etching the insulation film (19) to form first and second contact windows (21,22), forming a second conduction layer (28) with a polysilicon (23), a silicide (25) and a polysilicon (27), etching the layer (28) to a wiring (31), and third and fourth gate electrodes (33,34) to apply a second insulation film (35) on the substrate, selectively etching the film (35) to form a third insulation film (39) thereon, form a third contact window (40) on the electrode (34) to apply a third conduction layer (41) thereon, and patterning the layer (41) to apply a photoresist film onto the electrode (33) to implant impurity ions into the substrate to form a P-channel polysilicon region.

Description

Manufacturing method of static ram cell

1 is a circuit diagram according to the present invention

2 is a manufacturing process diagram according to the present invention

* Explanation of symbols for main parts of the drawings

17a, 17b, 33, 34: first, second, third and fourth gate electrodes

19: first insulating film 31: wiring

39: gate oxide film 42: third conductive layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (SRAM) in the method of manufacturing a semiconductor memory device, and in particular, a P-channel polycrystalline silicon transistor (hereinafter referred to as a "channel channel transistor") as a resistor. It relates to a method for producing a static ram cell to be used.

The static ram has a pair of high resistance and driving transistors connected in series between the power supply voltage VCC and ground VSS, and a connection node of the high resistance and Morse transistors cross-connected to the gate terminal of each of the driving MOSFETs. The gate terminal is composed of a transfer mode transistor connected to a word line between the node point and the bit line. Recently, due to the advance of the micromachining technology, the static ram is also increasing in capacity, and accordingly, the occupied area of the memory cell has to be reduced.

On the other hand, as described above, the high integration of the static ram using the resistance as a load increases the frequency of the memory destruction phenomenon called soft error. Soft-error refers to a phenomenon in which memory information is destroyed as alpha -particles emitted from uranium or thorium contained in a package material used to seal a memory chip are incident on a cell part.

As a countermeasure for soft errors as described above, a channel channel transistor has been proposed in which a stack structure of silicon and tungsten silicide is used as a gate electrode instead of a polycrystalline silicon resistor as a load means of a static ram cell. In other words, when the polysilicon layer, which is a load means, is jointly used as a wiring, a large voltage drop is caused due to a large resistance value compared to metal or silicide, which adversely affects memory operation. However, when the P-channel MOS transistor is used as a load. Compared with simply using a polycrystalline silicon layer as a load, more current can be supplied at turn-on and turn-off characteristics are better. However, when a gate electrode having a laminated structure of polysilicon and tungsten silicide is jointly used as a wiring, there is a problem in that the characteristics of the gate oxide film grown on the upper surface of the gate electrode, that is, the upper surface of tungsten silicide, are deteriorated. In addition, since the work function of the tungsten silicide is different from that of polycrystalline silicon, it is difficult to control the voltage of the gate electrode.

Accordingly, an object of the present invention is to provide a method for manufacturing a static ram cell having a load means that can be used as a low resistance wiring in the method for manufacturing a static ram cell.

Another object of the present invention is to provide a method for manufacturing a static ram cell having good characteristics of a P-channel MOS transistor which is used as a load means in the method for manufacturing a static ram cell.

Still another object of the present invention is to provide a method for manufacturing a static ram cell which can easily realize high integration by stacking wires in the method of manufacturing a static ram cell.

In order to achieve the objects of the present invention as described above, a device isolation oxide film, an active region, first and second gate electrodes are formed in a conventional static ram cell on a semiconductor substrate, and a first insulating layer is formed on the front surface of the substrate. Coating and forming a first and second contact window by etching a first insulating layer on a predetermined top surface of the active region and a top surface of the first gate electrode until the active region and the first gate electrode are exposed. And etching a predetermined region of the second conductive layer to form wiring and third and fourth gate electrodes, and then applying a second insulating film to the entire surface of the substrate and the second formed on the third gate electrode. After etching the insulating film and forming a gate oxide film, and performing a photolithography process, the second insulating film on the upper surface of the fourth gate electrode is etched to form a third contact window. Applying a third conductive layer to a surface and performing a photolithography process to form a pattern of the third conductive layer, and then a predetermined conductivity is applied to the entire surface of the substrate while the upper portion of the third gate electrode is blocked with a photomask. A process for completing a channel polycrystalline silicon transistor by ion implantation of an impurity having a type is characterized in that it is sequentially performed.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail. 1 is a circuit diagram of a static ram cell using a channel channel transistor according to the present invention as a load means. A pair of P-channel transistors 3 and 4 and a driving mode transistor 1 and 2 connected in series between a power supply voltage VCC and a ground VSS, and the P-channel transistors 3 and 4 and a driving mode The transfer mode transistors 7 and 8 are connected between the connection node points 5 and 6 between the transistors 1 and 2 and the bit lines, and the gates are connected to the word lines. Here, each of the connection node points 5 and 6 and the gates of the channeled transistors 3 and 4 are connected to each other, and each of the connection node points 5 and 6 and the driving mode transistors 1 and 2 are connected to each other. The gates are also connected crosswise. Here, the connection and ground line between the connection node points 5 and 6 and the gates of the PMOS transistors 3 and 4 are formed in a triple structure of polysilicon-silicide-polycrystalline silicon.

Next, the manufacturing method of the present invention according to the configuration of FIG. 1 will be described in detail with reference to FIGS. 2A to 2H.

2A to 2H are manufacturing process diagrams according to the present invention, in which the gate electrode is formed on the semiconductor substrate 10 on which the device isolation oxide film 12 and the active regions 16a, 16b, and 16c are formed in the normal MOS process. After the oxide film 14 is formed, polysilicon or silicide is formed on the entire surface of the substrate 10 to form the first gate electrode 17a and the second gate electrode 17b in a predetermined region. Then, a first insulating film 19 is formed on the upper surface of the substrate. By the above process, in the circuit diagram shown in FIG. 1, the gates of one driving mode transistor 2 and the transfer mode transistor 7 are formed. FIG. 2B illustrates a process of forming first and second contact windows 21 and 22 on an upper surface of a predetermined active region 16a and an upper surface of the first gate electrode 17a, through the first contact window 21. The wiring by the second conductive layer to be formed below and the active region are in contact with each other, and the gate of the PMOS transistor 2 is in contact with the first gate electrode 17a through the second contact window 22. . FIG. 2C is a step of forming a second conductive layer. Following the process of FIG. 2B, the first polysilicon layer 23, the silicide 25, and the second polycrystalline silicon layer 27 are formed on the entire surface of the substrate 10. It is formed sequentially to complete the second conductive layer 28. The first and second polysilicon layers 23 and 27 are doped with a predetermined impurity by diffusion or ion implantation.

FIG. 2D illustrates a process of forming a gate electrode and a gate electrode of a PMOS transistor, wherein the first and second contact windows 21 and 22 and the first insulating layer 19 adjacent thereto and the first gate electrode 17a are formed. Gate electrodes 33 and 34 of the channel channel transistor to be used as the wiring 31 and the load means by etching the second conductive layer 28 formed in a region other than the region corresponding to the upper portion of the center region by a conventional etching process. ). Next, a second insulating layer 35 is formed on the entire surface of the substrate 10. The wiring 31 formed in the process of FIG. 2d corresponds to a common wiring between the driving mode transistors 1 and 2 and the ground in FIG. 1, and the gate electrodes 33 and 34 correspond to the channel channel transistors 3 and 3, respectively. Corresponds to 4) gate.

FIG. 1E is a step of removing the second insulating layer on the upper surface of the first gate electrode. After forming the photoresist layer 37 on the entire surface of the substrate 10, the photoresist layer formed on the upper surface of the gate electrode 33 is removed. The second insulating layer 35 is removed by a normal photolithography process. In FIG. 1F, a gate oxide film is formed. Following the process shown in FIG. 1E, the photoresist layer 37 is removed, and then a gate oxide film 39 is formed by thermal oxidation or chemical vapor deposition.

FIG. 1G is a step of forming a contact field for contacting the third conductive layer and the third conductive layer with the first gate electrode. Subsequently, the third contact window 40 is formed on the upper surface of one end of the first gate electrode 17a by using a normal photolithography process, and then the third conductive layer 41 is formed on the entire surface of the substrate 10. Form. The third conductive layer 41 is formed of polycrystalline silicon, and is used as an active region of a channel MOS transistor to be completed below. By forming the third polycrystalline silicon on the surface of the third contact window 40, the gate of the driving transistor 2 and the source of the transfer transistor 7 of FIG. 1, the drain of the channel channel transistor 3, The gate of another PMOS transistor 4 is in contact to form a connection node 5.

In FIG. 1h, a pattern of the PMOS transistor is formed. A pattern of the PMOS transistor is formed over the wiring 31 in the vicinity of the contact window 40 formed on the upper surface of the first gate electrode 17a. The photoresist 43 is coated on the gate electrode 33. Then, impurities such as B or BF2 are ion-implanted using the photoresist 43 as a mask to form source and drain regions of the channel-MOS transistor. Such impurity injection reduces the resistance of the channel-channel transistor so that it can be commonly used as a low resistance wiring.

As described above, according to the present invention, the second conductive layer used as the gate and the wiring of the PMOS transistor in the manufacturing method of the static ram cell is a triple structure of the first polycrystalline silicon-silicide-second polycrystalline silicon. Compared to the case of using as a load, there is a significant reduction in resistance.

In addition, the present invention has the effect of improving the insulating film characteristics compared to the gate oxide film formed on the upper surface of the conventional tungsten silicide layer by forming a gate oxide film on the upper surface of the second polycrystalline silicon layer, which is the top layer of the second conductive layer. As a result, the threshold voltage and current characteristics of the P-channel MOS transistor for load can be improved.

In addition, the present invention can be used as the gate electrode of the channeled transistor with the second conductive layer having a triple structure, and can also be used as a wiring having low resistance, thereby achieving the multilayering of the wiring. Therefore, there is an advantage that can easily implement high integration of the static ram cell.

Claims (8)

A method of manufacturing a static ram cell on a semiconductor substrate 10 having an element isolation oxide film 12, an active region 16a, 16b, 16c, and a gate oxide film 14 formed thereon, wherein a first conductive film is formed on the substrate 10. After applying the layer, the predetermined region is etched to contact the predetermined active region 16b with the first gate electrode 17a and the second gate over the region corresponding to the predetermined active regions 16b and 16c. A first process of forming an electrode 17b, and then applying a first insulating film 19 to the entire surface of the substrate 10, the upper surface of the predetermined active region 16a and the upper surface of the first gate electrode 17a. A second process of forming the first and second contact windows 21 and 22 by etching the first insulating layer 19 in a predetermined region until the active region 16a and the first gate electrode 17a are exposed; In addition, the second conductive layer 28 in contact with a predetermined region of the active region 16a and the first gate electrode 17a may be formed of the first polycrystalline silicon 23, the silicide 25, and the second region. A third process of forming a triple structure in which the polysilicon 27 is sequentially applied; and an area corresponding to upper surfaces of the first and second contact windows 21 and 22 and an upper portion of the central region of the first gate electrode 17a. The second conductive layer 28 formed in the other region is etched to form the wiring 31 and the third and fourth gate electrodes 33 and 34, and then the second insulating layer 35 is coated on the entire surface of the substrate. A fifth process of selectively etching the second insulating film 35 on the upper surface of the third gate electrode 33 by a photolithography process and forming a third insulating film 39 on the entire surface of the substrate 10; A seventh process of forming a third contact window 40 on the upper surface of the fourth gate electrode 34 by performing a photolithography process and then applying the third conductive layer 41 to the entire surface of the substrate 10; After the etching process is performed to form the pattern of the third conductive layer 41, the photoresist is guided on the upper surface of the third gate electrode 33, and then a predetermined conductivity type is formed on the entire surface of the substrate 10. A method of manufacturing a static ram cell, characterized in that the eighth step of forming an implanted polysilicon by ion implantation of impurities having a. The method of claim 1, wherein the first conductive layer and the third conductive layer are polycrystalline silicon. The method of claim 1, wherein the third insulating layer (39) is an oxide layer. The method of claim 3, wherein the oxide film is a thermal oxide film or an oxide film by chemical vapor deposition. The method of claim 1, wherein the impurity used in the eighth step is B or BF2. A method of manufacturing a static ram cell according to claim 1, wherein the channeled polysilicon formed in the eighth step is a load means. The method of claim 6, wherein the channeled polysilicon is also used as a wiring. The thickness of the first polycrystalline silicon 23 is 500-1500 kPa, the thickness of the silicide layer 25 is 500-3000 kPa. A method of manufacturing a static ram cell, characterized in that the thickness of the 2 polysilicon layer 27 is 100-1000-.

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