KR20000043901A - Formation of contact hole of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to prevent contact resistance increasing owing to much smaller contact hole. CONSTITUTION: First, a gate insulating layer(21), a gate electrode(22) and an etch barrier(23) are successively formed on a semiconductor substrate(100) having an isolation layer(11). Next, a lightly doped regions(31) for source/drain are formed in the substrate(100), and then a gate sidewall etch barrier(25) such as a silicon nitride and an LDD spacer(26) such as silicon oxide are successively deposited over all surfaces. Next, the LDD spacer(26) and the gate sidewall etch barrier(25) are selectively etched to expose the substrate(100). Then, a heavily doped region(32) is formed in a periphery region of the substrate(100), and an interlayer dielectric(41) is formed over all surfaces. Subsequently, the interlayer dielectric(41) and the LDD spacer(26) in a cell region are etched by using both the etch barrier(23) and the gate sidewall etch barrier(25) as an etch mask until the substrate(100) is exposed. By doing so, bit line contact holes(42) and storage electrode contact holes(43) are formed not to be much smaller.

Description

Contact hole formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, a double layer structure of a gate sidewall etching barrier layer and a lightly doped drain (LDD) spacer layer as a gate spacer layer in a cell region and a peripheral region, and a contact of a cell region. The present invention relates to a method of forming a contact hole in a semiconductor device capable of reducing contact resistance because a contact hole is formed by removing an LDD spacer layer and forming a contact hole using a gate sidewall etch barrier layer during hole formation.

In general, as the degree of integration of semiconductor devices increases, the size of the contact itself connecting the upper and lower wirings, the capacitors, and the like decreases with the distance between the peripheral wirings. Therefore, in order to form a contact in a semiconductor device having a multi-layer conductivity, accurate and strict alignment in a manufacturing process is required, thereby reducing process margin. In addition, the reduction of the contact hole size requires a high precision of the semiconductor manufacturing equipment, it is very difficult to form a fine pattern of a certain size, for example 0.1 ㎛ with a current equipment. In consideration of the above-mentioned various matters, the contact hole itself becomes larger in size and distance, making it difficult to integrate the device. One of the methods to solve this problem is a self-aligned contact (SAC) method, which is characterized in that an etch barrier film having an interlayer insulating film and an etching selectivity is formed on the top of the gate electrode (the gate upper etch barrier film) and the sidewall of the gate electrode ( It is formed on the gate sidewall etch barrier film (generally a gate spacer film), and the interlayer insulating film is etched to make contact holes, which can make contact holes with process margin even with current equipment, thereby reducing the size of the cell region. There are advantages to it. In general, however, the gate sidewall etch barrier layer is formed simultaneously with the LDD spacer layer to form the LDD structure when forming transistors in the peripheral region. The thickness of the LDD spacer layer is larger than that required for the gate sidewall etch barrier layer, so that the contact of the cell region is performed. It becomes a problem that the contact resistance increases by making the hole size smaller than necessary.

Accordingly, the present invention provides a double layer structure of a gate sidewall etch barrier layer and an LDD spacer layer as a gate spacer layer in a cell region and a peripheral region, and removes the LDD spacer layer when forming a contact hole in a cell region, thereby using a gate sidewall etch barrier layer. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device capable of reducing contact resistance because the contact hole is formed by an alignment contact process.

A method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention for achieving the above object includes a semiconductor substrate having a gate structure including a gate insulating film, a gate electrode, and an etch barrier layer formed on the cell region and the peripheral region. Provided step; Forming a low concentration impurity region in the semiconductor substrate on both sides of the gate structure of the cell region and the peripheral region; Forming a double spacer layer including a gate sidewall etch barrier layer and an LDD spacer layer on sidewalls of the gate structure, and then forming a high concentration impurity region only in the peripheral region; And forming a bit line contact hole and a charge storage electrode contact hole in the cell region by a self-aligned contact process after forming the interlayer insulating film.

In addition, the contact hole forming method of the semiconductor device according to the second embodiment of the present invention for achieving the above object is a gate structure consisting of a gate insulating film, a gate electrode, an upper gate etch barrier film formed in each of the cell region and the peripheral region Providing a semiconductor substrate; Forming a low concentration impurity region in the semiconductor substrate on both sides of the gate structure of the cell region and the peripheral region; Forming a single spacer layer of a gate sidewall etch barrier layer on sidewalls of the gate structure; Forming a double spacer film by forming a spacer film of an LDD spacer film on the single spacer film, and then forming a high concentration impurity region only in the peripheral region; And forming a bit line contact hole and a charge storage electrode contact hole in the cell region by a self-aligned contact process after forming the interlayer insulating film.

1A and 1B are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

2A and 2B are cross-sectional views of devices for explaining a method for forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

3A and 3B are cross-sectional views of devices for explaining a method for forming contact holes in a semiconductor device according to a third embodiment of the present invention;

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate 11: device isolation film

21: gate insulating film 22: gate electrode

23: gate upper etching barrier layer 25: gate sidewall etching barrier layer

26: LDD spacer film 31: low concentration impurity region

32: high concentration impurity region 41: interlayer insulating film

42: bit line contact hole 43: charge storage electrode contact hole

C: cell area P: surrounding area

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1A, a device isolation layer 11 is formed on a semiconductor substrate 100, and a gate structure including a gate insulating layer 21, a gate electrode 22, and an upper gate etch barrier layer 23 is defined as a cell region (C). ) And the surrounding area P, respectively. Low concentration impurity ions are implanted to form the low concentration impurity region 31 in the semiconductor substrate 100 on both sides of the gate structure of the cell region C and the peripheral region P. The low concentration impurity region 31 serves as a source / drain in the cell region. The gate sidewall etch barrier layer 25 and the LDD spacer layer 26 are sequentially formed on the entire top including the gate structure.

In the above, the gate sidewall etch barrier layer 25 is formed by depositing silicon nitride to a thickness of 200 to 500 Å, and the LDD spacer layer 26 is formed of silicon oxide.

Referring to FIG. 1B, the LDD spacer layer 26 and the gate sidewall etch barrier layer 25 are sequentially etched until the semiconductor substrate 100 is exposed by the front etching process, and then high concentration impurity ions are formed only in the peripheral region P. Is implanted to form a high concentration impurity region 32, thereby forming a junction portion of the LDD structure together with the low concentration impurity region 31 in the peripheral region P. After the interlayer insulating film 41 is formed on the entire structure, a portion of the bit line contact hole and the charge storage electrode contact hole to be formed is opened, and the remaining part is covered with a photoresist pattern (not shown) and a gate. The interlayer insulating layer 41 and the LDD spacer layer 26 are etched until the semiconductor substrate 100 is exposed by a self-aligned contact process using the upper etching barrier layer 23 and the gate sidewall etching barrier layer 25 as an etching mask. The bit line contact hole 42 and the charge storage electrode contact hole 43 are formed.

According to the first embodiment of the present invention, the interlayer is formed by the self-aligned contact process using the gate upper etching barrier layer 23 and the gate sidewall etching barrier layer 25 when forming the contact holes 42 and 43 in the cell region C. Since the contact holes 42 and 43 are formed together with the insulating film 41 by removing the LDD spacer film 26 having an unnecessary thickness, the contact holes 42 and 43 in the cell region C become smaller than necessary. This can improve the contact resistance of the cell region (C).

2A and 2B are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2A, the device isolation layer 11 is formed on the semiconductor substrate 100, and the gate structure including the gate insulating layer 21, the gate electrode 22, and the gate upper etching barrier layer 23 is defined as a cell region (C). ) And the surrounding area P, respectively. Low concentration impurity ions are implanted to form the low concentration impurity region 31 in the semiconductor substrate 100 on both sides of the gate structure of the cell region C and the peripheral region P. The low concentration impurity region 31 serves as a source / drain in the cell region. The gate sidewall etch barrier layer 25 and the LDD spacer layer 26 are sequentially formed on the entire top including the gate structure.

In the above, the gate sidewall etch barrier layer 25 is formed by depositing silicon nitride to a thickness of 200 to 500 Å, and the LDD spacer layer 26 is formed of silicon oxide.

Referring to FIG. 2B, the LDD spacer layer 26 and the gate sidewall etch barrier layer 25 are sequentially etched until the semiconductor substrate 100 is exposed by the front side etching process, and then high concentration impurity ions are formed only in the peripheral region P. Is implanted to form a high concentration impurity region 32, thereby forming a junction portion of the LDD structure together with the low concentration impurity region 31 in the peripheral region P. After the interlayer insulating film 41 is formed on the entire structure, a portion of the bit line contact hole and the charge storage electrode contact hole to be formed is opened, and the remaining part is covered with a photoresist pattern (not shown) and a gate. The interlayer insulating layer 41 and the LDD spacer layer 26 are etched until the semiconductor substrate 100 is exposed by a self-aligned contact process using the upper etching barrier layer 23 and the gate sidewall etching barrier layer 25 as an etching mask. Next, the bit line contact hole 42 and the charge storage electrode contact hole 43 are formed by completely removing the protruding portion of the gate sidewall etching barrier layer 25 in the contact portion with the semiconductor substrate 100.

According to the second embodiment of the present invention, the interlayer is formed by the self-aligned contact process using the gate upper etching barrier layer 23 and the gate sidewall etching barrier layer 25 when forming the contact holes 42 and 43 in the cell region C. In addition to removing the LDD spacer layer 26 having an unnecessary thickness along with the insulating layer 41, a portion of the sidewall etch barrier layer 43 protruding from the bottom of the contact holes 42 and 43 may be removed to remove the contact holes 42 and. Since 43 is formed, the contact holes 42 and 43 of the cell region C can be prevented from becoming smaller than necessary to improve the contact resistance of the cell region C. FIG.

3A and 3B are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to a third embodiment of the present invention.

Referring to FIG. 3A, the device isolation layer 11 is formed on the semiconductor substrate 100, and the gate structure including the gate insulating layer 21, the gate electrode 22, and the gate upper etching barrier layer 23 is defined as a cell region (C). ) And the surrounding area P, respectively. Low concentration impurity ions are implanted to form the low concentration impurity region 31 in the semiconductor substrate 100 on both sides of the gate structure of the cell region C and the peripheral region P. The low concentration impurity region 31 serves as a source / drain in the cell region. After the gate sidewall etch barrier layer 25 is formed on the entire top including the gate structure, the gate sidewall etch barrier layer 25 is etched until the semiconductor substrate 100 is exposed by the front side etching process. Thereafter, the LDD spacer film 26 is formed on the entire structure.

In the above, the gate sidewall etch barrier layer 25 is formed by depositing silicon nitride to a thickness of 200 to 500 Å, and the LDD spacer layer 26 is formed of silicon oxide.

Referring to FIG. 3B, the LDD spacer layer 26 is sequentially etched until the semiconductor substrate 100 is exposed by the entire etching process, and then the high concentration impurity regions 32 are implanted by implanting high concentration impurity ions into the peripheral region P only. As a result, a junction portion of the LDD structure is formed in the peripheral region P together with the low concentration impurity region 31. After the interlayer insulating film 41 is formed on the entire structure, a portion of the bit line contact hole and the charge storage electrode contact hole to be formed is opened, and the remaining part is covered with a photoresist pattern (not shown) and a gate. The interlayer insulating layer 41 and the LDD spacer layer 26 are etched until the semiconductor substrate 100 is exposed by a self-aligned contact process using the upper etching barrier layer 23 and the gate sidewall etching barrier layer 25 as an etching mask. The bit line contact hole 42 and the charge storage electrode contact hole 43 are formed.

The third embodiment of the present invention described above can obtain the same effects as the second embodiment by changing the process sequence from the second embodiment.

As described above, according to the present invention, the gate spacer layer is formed of a double spacer layer including a gate sidewall etch barrier layer having a predetermined thickness and an LDD spacer layer having a predetermined thickness, thereby securing the thickness of the gate spacer layer necessary for forming an LDD structure in the surrounding area. When forming the contact hole in the cell area, the contact hole is formed by removing the LDD spacer layer by the self-aligned contact process using the gate sidewall etching barrier film, thereby reducing the contact resistance in the cell area by reducing the contact hole in the cell area. It is possible to improve the reliability and yield of the semiconductor device.

Claims (9)

Providing a semiconductor substrate having a gate structure formed of a gate insulating film, a gate electrode, and an upper gate etching barrier film in each of a cell region and a peripheral region; Forming a low concentration impurity region in the semiconductor substrate on both sides of the gate structure of the cell region and the peripheral region; Forming a double spacer layer including a gate sidewall etch barrier layer and an LDD spacer layer on sidewalls of the gate structure, and then forming a high concentration impurity region only in the peripheral region; And And forming a bit line contact hole and a charge storage electrode contact hole in said cell region by forming an interlayer insulating film, followed by a self-aligned contact process. The method of claim 1, The gate sidewall etch barrier layer is formed by depositing silicon nitride to a thickness of 200 to 500Å. The method of claim 1, And the LDD spacer layer is formed of silicon oxide. The method of claim 1, The self-aligned contact process may etch the interlayer insulating layer and the LDD spacer layer together with the gate upper etching barrier layer and the gate sidewall etching barrier layer as an etching mask until the semiconductor substrate is exposed. Contact hole formation method. The method of claim 1, The self-aligned contact process may etch the interlayer insulating layer and the LDD spacer layer together with the gate upper etch barrier layer and the gate sidewall etch barrier layer as an etch mask until the semiconductor substrate is exposed, and at the bottom of the contact hole. And removing a portion of the gate sidewall etch barrier layer that protrudes from the gate sidewall. Providing a semiconductor substrate having a gate structure formed of a gate insulating film, a gate electrode, and an upper gate etching barrier film in each of a cell region and a peripheral region; Forming a low concentration impurity region in the semiconductor substrate on both sides of the gate structure of the cell region and the peripheral region; Forming a single spacer layer of a gate sidewall etch barrier layer on sidewalls of the gate structure; Forming a double spacer film by forming a spacer film of an LDD spacer film on the single spacer film, and then forming a high concentration impurity region only in the peripheral region; And And forming a bit line contact hole and a charge storage electrode contact hole in said cell region by forming an interlayer insulating film, followed by a self-aligned contact process. The method of claim 6, The gate sidewall etch barrier layer is formed by depositing silicon nitride to a thickness of 200 to 500Å. The method of claim 6, And the LDD spacer layer is formed of silicon oxide. The method of claim 6, The self-aligned contact process may etch the interlayer insulating layer and the LDD spacer layer together with the gate upper etching barrier layer and the gate sidewall etching barrier layer as an etching mask until the semiconductor substrate is exposed. Contact hole formation method.