JP2985845B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which MOS transistors are arranged at different intervals in two regions and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated and miniaturized, the source and source constituting a MOS transistor have been developed.
The junction of the drain and the like is shallow, and the channel length (gate length) is becoming shorter. On the other hand, there is a problem that hot carriers are generated due to the high electric field and are injected into the gate insulating film of the MOS transistor, thereby deteriorating the characteristics.
On the other hand, in the related art, the LDD structure in which the impurity concentration is lower in the region closer to the gate electrode of the drain reduces the electrolytic concentration near the drain and suppresses the deterioration of the characteristics due to the hot carriers described above. I have.

The LDD structure is used, for example, as a MOS transistor in a peripheral circuit of a semiconductor memory device having a memory cell composed of a MOS transistor and a capacitor. FIG. 3 is a cross-sectional view showing a part of the semiconductor memory device, and here shows a state where a MOS transistor is formed. That is, the semiconductor substrate 3
The memory cell area 304a and the peripheral circuit area 304b are partitioned on the field oxide film 302 by the field oxide film 302.

[0006] Among them, in the memory cell region 304a, a MOS transistor 305 which is partitioned by a field oxide film 304 and forms a memory cell is formed. In the memory cell region 304a, a wiring 306 is formed on the field oxide film 303.
On the other hand, a MOS transistor 307 is formed in the peripheral circuit region 304b. This MOS transistor 30
7 is required to have high breakdown voltage characteristics,
08 has an LDD structure. Note that since the MOS transistor 307 and the MOS transistor 305 are formed at the same time, the MOS transistor 305 is also in a state where the sidewall 309 is formed.

[0005]

By the way, the aforementioned L
The sidewall 309 for forming the DD structure is formed as described below. Here, a description will be given particularly of a region partitioned by the field oxide film 304. First, as shown in FIG.
The gate electrode 305 is formed on the gate electrode 305 via a gate insulating film 305a.
b is formed, and ions are implanted using the gate electrode 305b as a mask to form a low-concentration impurity region 308 serving as a source / drain. Next, as shown in FIG. 4B, a silicon oxide film 401 is deposited thereon by a CVD method or the like. Then, it is etched by a dry etching method having anisotropy such as RIE until the surface of the semiconductor substrate 301 beside the gate electrode 305b is exposed as shown in FIG. 309 are formed.

However, here, the gate electrode 305
Since the etching is performed until the surface of the semiconductor substrate 301 on the side b is exposed, the front end portion 402 of the field oxide film 304 is retreated, and the surface of the semiconductor substrate 301 where the low concentration impurity region 308 does not exist may be exposed. That is, the boundary between the end portions of the source and drain constituting the MOS transistor is exposed once. Thereafter, these regions are covered with an interlayer insulating film or the like, but once the surface is exposed, an interface state is formed as described above. With such a region, a current leaks from the end of the impurity region serving as the source / drain constituting the MOS transistor. This current leak does not cause much problem in the MOS transistor of the peripheral circuit, but it is better that the MOS transistor of the memory cell does not leak as much as possible to retain data.

The present invention has been made to solve the above problems, and has as its object to suppress current leakage from the source / drain of a MOS transistor.

[0008]

According to the present invention, there is provided a semiconductor device comprising a first region in which a memory cell is arranged and a second region in which a peripheral circuit is arranged. Are formed at a smaller interval than the second region, a wiring electrode made of a conductor of the same material as the gate electrode on the gate insulating film and the gate electrode on the field oxide film is formed. , An insulating film is buried, and a sidewall film made of an insulating film is formed on a boundary between the first region and the second region and on a gate electrode in the second region. Therefore, when the sidewall film is formed, the surface of the semiconductor substrate on which the source / drain of the first gate electrode is formed is not exposed in the first region. In addition, the method for manufacturing a semiconductor device according to the present invention includes:
First, a conductive film is formed on the semiconductor substrate including the gate insulating film and the first and second field oxide films. next,
A spacer film is formed on the conductive film. Next, a mask pattern is formed on the spacer film at a smaller interval in the first region than in the second region. Next, the spacer film and the conductive film are selectively etched by using the mask pattern as a mask, and the first and second gate electrodes in which the spacer made of the spacer film is disposed in the first region and the second region. To form Next, by introducing impurities of the second conductivity type into the semiconductor substrate using the first and second gate electrodes as a mask, a source and a drain are formed so as to sandwich the first gate electrode, and the second gate electrode is formed. A low concentration impurity region is formed so as to sandwich the region. Next, an insulating film is formed on the semiconductor substrate including the first and second gate electrodes so as to be embedded between the first gate electrode and the spacers disposed thereon. Then, the side wall film is formed on the side surface of the second gate electrode by etching the insulating film by etching having anisotropy in the vertical direction until the surface of the semiconductor substrate around the second gate electrode is exposed. . Therefore, when the sidewall film is formed, the surface of the semiconductor substrate on which the source / drain of the first gate electrode is formed is not exposed in the first region.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Here, formation of a sidewall (sidewall film) arranged on a side surface of a gate electrode for forming an LDD structure will be described. Hereinafter, the manufacturing method in this embodiment will be described. First, as shown in FIG.
A field oxide film 102 on a silicon substrate 101
After the formation of the gate insulating film 103, a gate insulating film 104 is formed, and a conductive film 105 as a gate electrode material is deposited thereon. Here, the memory cell region 101a and the peripheral circuit region 101b are partitioned by the field oxide film 102,
The memory cell region 1 is formed by the field oxide film 103.
Each memory cell at 01a is partitioned.

Next, as shown in FIG. 1B, a spacer film 106 made of, for example, silicon oxide is formed on the conductive film 105. The formation of this spacer film 106
For example, it may be performed by a CVD method or the like. Further, the thickness of the spacer film 106 is set to be equal to or larger than the insulating film 109 described later. Next, as shown in FIG. 1C, using the resist pattern 107 formed on the spacer film 106 in accordance with the gate electrode formation position as a mask, first, the spacer film 106 is selectively etched, By etching the conductive film 105, the gate electrodes 105a and 105 on which the spacers 106a are disposed are provided.
b and the wiring 105c are formed.

Here, the resist pattern 107 may be formed by a known photolithography technique.
Further, the etching of the spacer film 106 and the conductive film 1
The etching of 05 may be performed by, for example, dry etching using CF ₄ gas. Then, for example, P (phosphorus) is ion-implanted using these formation patterns as a mask to form the low-concentration impurity regions 108.
This low concentration impurity region 108 is
a, it becomes a source / drain, and in the peripheral circuit area, LD
D.

Next, after removing the resist pattern 107, as shown in FIG. 1D, an insulating film 109 is formed thereon by depositing silicon oxide by, for example, a CVD method. At this time, the memory cell region 101a
In FIG. 7, the distance between the gate electrodes 105a is formed narrow, and a spacer 106a is formed on the side wall of the gate electrode 105a. Therefore, in the memory cell region 101a, the insulating film 109 is formed so as to fill the space between the gate electrode 105a and the spacer 106a. However, since the periphery of the gate electrode 105b is formed wide in the peripheral circuit region 101b, the insulating film 109 is not formed up to the position above the spacer 106a on the gate electrode 105b. Therefore, the thickness of the insulating film 109 deposited on the spacer 106 a on the gate electrode 105 b and the thickness of the gate electrode 105
There is not much difference between the thickness of the insulating film 109 around b.

Next, as shown in FIG.
09 having anisotropy in the etching direction, for example, R
Etching is performed by an IE method or the like to form a sidewall (sidewall film) 110. I do. At this time, the gate electrode 1
The gate insulating film 104 around the area 05b is simultaneously etched to expose the silicon substrate 101 in that area. Here, in the memory cell region 101a, the gate electrode 1
The insulating film 109a remains in a state such as during the period 05a. Then, the source / drain 111 of the MOS transistor in the peripheral circuit region 101b is formed by ion-implanting, for example, As (arsenic). Thereafter, by forming an interlayer insulating film, forming a capacitor electrode, and the like, a semiconductor device having a memory cell is formed.

As described above, according to this embodiment, in the memory cell region 101a,
At the time of forming the sidewall 110, for example, the field oxide film 103 is not etched at all. Therefore, since there is no receding edge of the field oxide film 103, the boundary of the low-concentration impurity region 108 and the surface of the silicon substrate 101 outside the boundary are not exposed. Therefore, according to this embodiment, in the MOS transistor formed in memory cell region 101a, occurrence of current leak in such a region is suppressed.

[0015]

As described above, according to the present invention, the first region is made of the same material as the gate electrode on the gate insulating film and the gate electrode on the field oxide film at a smaller interval than the second region. A wiring electrode made of a conductor is formed, an insulating film is buried between the gate electrode and the wiring electrode in the first region, and a boundary between the first region and the second region and a gate electrode in the second region. Has a configuration in which a sidewall film made of an insulating film is formed. That is, first, a conductive film is formed on the semiconductor substrate including the gate insulating film and the first and second field oxide films. Next, a spacer film is formed on the conductive film. Next, a mask pattern is formed on the spacer film at a smaller interval in the first region than in the second region.
Next, the spacer film and the conductive film are selectively etched by using the mask pattern as a mask, and the first and second gate electrodes in which the spacer made of the spacer film is disposed in the first region and the second region. To form Next, by introducing impurities of the second conductivity type into the semiconductor substrate using the first and second gate electrodes as a mask, a source and a drain are formed so as to sandwich the first gate electrode, and the second gate electrode is formed. A low concentration impurity region is formed so as to sandwich the region. Next, an insulating film is formed on the semiconductor substrate including the first and second gate electrodes so as to be embedded between the first gate electrode and the spacers disposed thereon. Then, the side wall film is formed on the side surface of the second gate electrode by etching the insulating film by etching having anisotropy in the vertical direction until the surface of the semiconductor substrate around the second gate electrode is exposed. .

Accordingly, in the first region, the periphery thereof is buried with the insulating film, so that when the side wall film is formed on the side surface of the second gate electrode, the source of the first gate electrode is formed. -The surface of the semiconductor substrate on which the drain is formed is not exposed. As a result, in the transistor with the first gate electrode, the semiconductor substrate of the source / drain formation portion is not exposed. Therefore, according to the present invention, the source / drain edge boundary of the transistor with the first gate electrode is Has the effect that the current leakage of the semiconductor device can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view following FIG. 1 for explaining the method of manufacturing the semiconductor device in the embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a part of a conventional semiconductor memory device.

FIG. 4 is a sectional view schematically illustrating a part of a conventional method for manufacturing a semiconductor memory device.

[Explanation of symbols]

101: silicon substrate, 101a: memory cell region, 1
01b: peripheral circuit region, 102, 103: field oxide film, 104: gate insulating film, 105: conductive film, 10
5a, 105b: gate electrode, 105c: wiring, 106
... spacer film, 106a ... spacer, 107 ... resist pattern, 108 ... low concentration impurity region, 109, 109
a: insulating film, 110: sidewall (sidewall film), 11
1: Source / drain.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/336 H01L 21/8234 H01L 21/8242 H01L 27/088 H01L 29/78

Claims (7)

(57) [Claims] A first region in which a memory cell is arranged;
In a semiconductor device including a second region in which peripheral circuits are arranged, the first region has a smaller interval than the second region,
A wiring electrode made of a conductor of the same material as the gate electrode on the gate insulating film and the gate electrode on the field oxide film is formed, and an insulating film is buried between the gate electrode and the wiring electrode in the first region. A boundary between the first region and the second region and the second region.
A side wall film made of the insulating film is formed on the gate electrode in the region of (1). 2. The semiconductor device according to claim 1, wherein a spacer film having a thickness equal to or greater than a thickness of said sidewall film is formed on said gate electrode and said wiring electrode. apparatus. 3. The semiconductor device according to claim 2, wherein said spacer film is made of an insulator. 4. The MOS device according to claim 1, wherein a source or drain junction of the MOS transistor adjacent to the field oxide film formed in the first region is connected to a gate insulation of the MOS transistor. A semiconductor device covered with the same insulating film as the film. 5. A first field oxide film for partitioning a first region where a memory cell is disposed and a second region where a peripheral circuit is disposed, and partitioning each memory cell in the first region. A first step of forming a second field oxide film on the semiconductor substrate of the first conductivity type, a second step of forming a gate insulating film on the semiconductor substrate, the gate insulating film and the first A third step of forming a conductive film on the semiconductor substrate including the second field oxide film, a fourth step of forming a spacer film on the conductive film, A fifth step of forming a mask pattern on the spacer film at a smaller interval than the second region; and selectively etching the spacer film and the conductive film using the mask pattern as a mask; Area and A sixth step of forming first and second gate electrodes in which the spacer made of the spacer film is disposed on the second region, and the semiconductor substrate using the first and second gate electrodes as a mask. Forming a source / drain so as to sandwich the first gate electrode, and forming a low-concentration impurity region so as to sandwich the second gate electrode. An eighth step of forming an insulating film on the semiconductor substrate including the first and second gate electrodes so as to bury the space between the first gate electrode and the spacers disposed thereon; By the etching having anisotropy in the vertical direction, the second
A ninth step of forming a sidewall film on the side surface of the second gate electrode by etching the insulating film until the surface of the semiconductor substrate around the gate electrode is exposed; and the second gate electrode and the sidewall. A tenth step of forming a source / drain of the second gate electrode so as to sandwich the low-concentration impurity region by introducing an impurity of the second conductivity type at a higher concentration than the low-concentration impurity region using the film as a mask. And a method for manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the spacer film is formed to have a thickness equal to or greater than a thickness of an insulating film including the first and second gate electrodes formed on the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 7. The method for manufacturing a semiconductor device according to claim 5, wherein said spacer film is made of an insulator.