KR970006268B1 - Fabrication method of mosfet - Google Patents

Fabrication method of mosfet Download PDF

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KR970006268B1
KR970006268B1 KR1019930031827A KR930031827A KR970006268B1 KR 970006268 B1 KR970006268 B1 KR 970006268B1 KR 1019930031827 A KR1019930031827 A KR 1019930031827A KR 930031827 A KR930031827 A KR 930031827A KR 970006268 B1 KR970006268 B1 KR 970006268B1
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forming
film
gate electrode
layer
region
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KR1019930031827A
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KR950021273A (en
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박상훈
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현대전자산업 주식회사
김주용
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Priority to KR1019930031827A priority Critical patent/KR970006268B1/en
Priority to US08/365,293 priority patent/US5620911A/en
Priority to DE4447254A priority patent/DE4447254C2/en
Priority to JP7000039A priority patent/JP2624948B2/en
Publication of KR950021273A publication Critical patent/KR950021273A/en
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Publication of KR970006268B1 publication Critical patent/KR970006268B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of fabricating a MOSFET includes the steps of forming a P well in a silicon substrate, depositing an oxide layer and nitride layer and patterning them to leave them only on an active region but remove them formed on a predetermined region of the active region, on which a gate electrode will be formed and implanting P+ impurities into the substrate to form a channel stopper, forming a field oxide layer and temporary field oxide layer on a nonactive region and active region, respectively, removing the nitride layer and oxide layer, forming a photoresist pattern on the temporary field oxide layer and forming an N+ ion implanted region in the silicon substrate, removing the photoresist pattern, depositing a polysilicon layer on the substrate, forming a photoresist pattern on a region other than the temporary field oxide layer, removing the polysilicon layer and temporary field oxide layer to form a trench, removing the photoresist pattern, forming a gate electrode in the trench and forming a gate oxide layer and gate electrode, depositing a PSG layer on the overall surface of the substrate and diffusing doped N- ions into the silicon substrate surrounding the gate electrode through high-temperature heat treatment to form an N- region, etching the PSG layer to exose the polysilicon layer, leaving PSG remnants on the sides of the gate electrode, forming a silicide layer on the polysilicon layer ad gate electrode, forming an interlevel insulating layer on the substrate, removing a predetermined portion of the interlevel insulating layer to form a contact hole exposing the silicide layer and forming a metal line, to thereby restrict spikes when the metal line comes into contact with a lower conductive layer.

Description

반도체 모스펫(MOSFET) 제조방법.Semiconductor MOSFET Manufacturing Method.

제1도는 종래의 방법에 따라 제조된 모스펫(MOSFET)의 단면도.1 is a cross-sectional view of a MOSFET manufactured according to a conventional method.

제2a도 내지 제2e도는 본 발명의 방법에 의해 모스펫을 제조하는 과정을 도시한 단면도.2a to 2e are cross-sectional views showing a process for manufacturing a MOSFET by the method of the present invention.

제3도는 본 발명의 다른 실시예를 도시한 단면도.3 is a cross-sectional view showing another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

2 : 채널스토퍼영역 3 : 필드산화막2: channel stopper region 3: field oxide film

4 : 게이트산화막 5 : 게이트전극4 gate oxide film 5 gate electrode

6 : 스페이서 7 : N+이온주입영역6 spacer 7 N + ion implantation region

8 : 층간 절연막 9 : 콘택홀8 interlayer insulating film 9 contact hole

10 : 금속배선 11 : 산화막10 metal wiring 11 oxide film

12 : 질화막 13 : 폴리실리콘막12: nitride film 13: polysilicon film

14 : 가상 필드산화막 15 : 제1감광막 패턴14 virtual field oxide film 15 first photosensitive film pattern

16 : N+이온주입영역 17 : 폴리실리콘막16: N + ion implantation region 17: polysilicon film

18 : 제2감광막 패턴 19 : 트랜치18: second photosensitive film pattern 19: trench

20 : N-영역 23 : PSG막20: N - region 23: PSG film

24 : 실리사이드 25 : 층간절연층24: silicide 25: interlayer insulating layer

본 발명은 반도체 모스펫 제조방법에 관한 것으로 특히 실리사이드를 형성하여 소오스 및 드레인 전극에 접속되는 금속배선의 접속 스파이킹 현상을 방지하고 가상의 필드산화막을 이용하여 실리콘기판에 대한 게이트전극의 단차를 감소시키는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor MOSFET, in particular to form a silicide to prevent connection spikes of metal wires connected to the source and drain electrodes, and to reduce the step difference of the gate electrode with respect to the silicon substrate by using a virtual field oxide film. It is about a method.

종래의 공정방법에 의하여 형성된 모스펫의 단면도는 제1도와 같다.The cross-sectional view of the MOSFET formed by the conventional process method is shown in FIG.

제1도를 보면 P-웰로 된 실리콘기판(1) 상부에 활성영역과 비활성영역을 설정하고 비활성영역에 P+형 불순물 이온을 주입하여 채널 스토퍼(channel stopper) 영역(2)을 형성한 후 그 상부에 필드산화막(3)을 형성한다.Referring to FIG. 1, an active region and an inactive region are set on the P-well silicon substrate 1, and a P + type impurity ion is implanted into the inactive region to form a channel stopper region 2. The field oxide film 3 is formed on the top.

활성영역의 소정부분에 게이트산화막(4)과 게이트 폴리실리콘막으로 된 게이트전극(5)을 형성하고 N-형 분순물 이온을 주입한 후 게이트전극(5) 측벽에 저온산화막 스페이서(6)를 형성한 다음 N-형 분순물 이온을 주입하여 소오스/드레인전극용 N+이온주입영역(7)을 형성한다.A gate electrode 5 made of a gate oxide film 4 and a gate polysilicon film is formed in a predetermined portion of the active region, and an N − type impurity ion is implanted into the low temperature oxide spacer 6 on the sidewall of the gate electrode 5. After the formation, the N − -type impurity ions are implanted to form the N + ion implantation region 7 for the source / drain electrodes.

전체적으로 층간 절연막(8)을 적층하고 N+이온주입영역(7)에 각각 콘택홀(9)을 형성하여 금속배선(10)을 형성한 단면도이다.Overall, the interlayer insulating film 8 is stacked and the contact holes 9 are formed in the N + ion implantation regions 7 to form the metal wiring 10.

상기와 같은 종래의 모스펫 제조방법은 소오스/드레인 전극에 금속배선이 직접적으로 접속하게 되어 접속 스파이킹 현상이 발생하여 소자의 신뢰성에 문제점이 있게 된다.In the conventional MOSFET manufacturing method as described above, the metal wiring is directly connected to the source / drain electrodes, so that connection spike occurs, thereby causing a problem in reliability of the device.

따라서 본 발명에서는 상기한 문제점을 해결하기 위하여 소오스/드레인 전극 상부에 소정의 실리사이드를 형성하여 소오드/드레인 전극과 접속되는 금속 배선의 접속 여유도를 크게 하고 스파이킹을 방지하며 가상의 필드산화막을 이용하여 게이트전극의 실리콘기판에 대한 단차를 감소키는데 그 목적이 있다.Accordingly, in the present invention, in order to solve the above problems, a predetermined silicide is formed on the source / drain electrodes to increase the connection margin of the metal wires connected to the source / drain electrodes, to prevent spiking, and to provide a virtual field oxide film. The purpose is to reduce the step difference of the gate electrode with respect to the silicon substrate.

이하 본 발명을 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the drawings.

제2a도 내지 제2e도는 본 발명에 의하여 형성한 모스펫의 단면도이다.2A to 2E are cross-sectional views of the MOSFET formed according to the present invention.

제2a도는 P-웰로 형성된 실리콘기판(1) 상부에 제1산화막(11)과 질화막(12)을 순차적으로 적층하고 사진식각법으로 활성영역(A)과 비활성영역(B)을 설정하여 활성영역(A)의 실리콘기판 상부에 산화막(11)과 질화막(12)을 남기고, 활성영역중 게이트전극이 형성될 부분은 식각한 다음 전체적으로 P+형 분순물을 이온주입하여 채널스토퍼영역(2)을 형성한 단면도이며, 제3도와 같이 제1산화막(11)과 질화막(12) 사이에 도핑되지 않은 제1폴리실리콘막(13)을 적충할 수 있다.FIG. 2A shows the first oxide film 11 and the nitride film 12 sequentially stacked on the silicon substrate 1 formed of the P-well, and the active region A and the inactive region B are set by photolithography. The oxide film 11 and the nitride film 12 are left on the silicon substrate of (A), and the portion of the active region where the gate electrode is to be formed is etched and ion implanted into the P + type impurities as a whole to form the channel stopper region 2. As shown in FIG. 3, the undoped first polysilicon film 13 may be filled between the first oxide film 11 and the nitride film 12 as shown in FIG. 3.

제2b도는 필드산화막 형성공정으로 비활성영역(B)에 소자간을 격리시키는 필드산화막(3)을 형성하는 동시에 활성영역(A)의 게이트전극이 형성될 부분에도 가상의 필드산화막(14)을 형성하고 이후 질화막(12) 및 산화막(11)을 제거한 후에 상기 필드산화막(3)과 가상의 필드산화막(14) 상부에 제1감광막 패턴(15)을 형성하여 N+이온주입영역(16)을 형성한 단면도이다.FIG. 2B shows a field oxide film 3 for isolating elements in the inactive region B in the field oxide film forming process, and at the same time, a virtual field oxide film 14 is also formed in the portion where the gate electrode of the active region A is to be formed. After the nitride film 12 and the oxide film 11 are removed, a first photosensitive film pattern 15 is formed on the field oxide film 3 and the virtual field oxide film 14 to form an N + ion implantation region 16. One cross section.

제2c도는 제1감광막 패턴(15)을 제거하고 전체구조 상부에 소정두께의 제2폴리실리콘막(17)을 적충하고 가상의 필드산화막(14)을 제거하기 위하여 제2감광막 패턴(18)을 형성하여 노출된 제2폴리실리콘막(17)의 일부분을 비등방성 식각으로 제거하고 게이트전극 형성을 위하여 노출된 가상의 필드산화막(14)을 동방성 식각으로 제거하여 트렌치(19)를 형성한 단면도이다.FIG. 2C shows the second photoresist pattern 18 for removing the first photoresist pattern 15, filling the second polysilicon film 17 having a predetermined thickness over the entire structure, and removing the virtual field oxide film 14. A portion of the second polysilicon layer 17 formed and exposed is removed by anisotropic etching, and the trench 19 is formed by removing the virtual field oxide layer 14 isotropically etched to form the gate electrode. to be.

제2d도는 상기 제2감광막 패턴(18)을 제거하고 트렌치(19) 내부에 게이트산화막(4)과 도핑된 게이트폴리실리콘막으로 된 게이트전극(5)을 형성하고, PSG막(23)을 전체적으로 증착하고 고온 열처리하여 도프된 N-이온을 게이트전극 주변의 실리콘기판(1)에 확산시켜 N-영역(20)을 형성한 상태의 단면도이다. 상기 트랜치(19) 내부에 게이트전극(4)을 형성하므로써 실리콘기판(1)에 대한 게이트전극의 단차를 감소시킬 수 있다.2d illustrates the removal of the second photoresist layer pattern 18, forming the gate electrode 5 made of the gate oxide layer 4 and the doped gate polysilicon layer in the trench 19, and the PSG layer 23 as a whole. A cross-sectional view of a state in which N - ions are deposited and subjected to high temperature heat treatment is diffused into the silicon substrate 1 around the gate electrode to form the N - region 20. By forming the gate electrode 4 inside the trench 19, the step difference of the gate electrode with respect to the silicon substrate 1 can be reduced.

제2e도는 블랜켓 식각공정으로 상기 PSG막(23)을 상기 제2폴리실리콘막(17)이 노출되기 까지 식각하여 게이트전극(4)을 측면에 PSG막잔여물(23A)을 남기고, 전이 금속을 선택증착하여 폴리실리콘막(17)과 게이트전극(4)의 상부에 실리사이드막(24)이 형성되게 하고 전체구조 상부에 층각절연층(25)을 형성하고, 사진식각공정으로 층간절연층(25)의 일정부분을 제거하여 콘택홀을 형성하고, 금속배선(10)을 형성한 단면도이다. 상기 블랜켓 식각공정으로 상기 PSG막을 상기 제2폴리실리콘막(17)이 노출되기까지 식각할때 PSG막과 제2폴리실리콘막의 식각 선택비가 5 : 1 이상으로 한다.FIG. 2E shows the PSG layer 23 is etched until the second polysilicon layer 17 is exposed by a blanket etching process, leaving the gate electrode 4 with the PSG residue 23A on the side, and the transition metal. Selective deposition is performed so that the silicide film 24 is formed on the polysilicon film 17 and the gate electrode 4, and the laminar insulating layer 25 is formed on the entire structure. 25 is a cross-sectional view of removing contact portions to form contact holes and forming metal wirings 10. When the PSG film is etched until the second polysilicon film 17 is exposed by the blanket etching process, an etching selectivity of the PSG film and the second polysilicon film is set to 5: 1 or more.

상기 금속배선(10)은 실리사이드(24)와 접속되어 있으므로 스파이킹을 방지할 수 있다.Since the metal wire 10 is connected to the silicide 24, it is possible to prevent spiking.

제3도는 본 발명의 다른 실시예이며 제2a도에서 설명한 바와 같이 산화막(11)와 질화막(12) 사이에 도핑되지 않은 폴리실리콘막(13)을 적충할 수 있으며 후속 공정은 제2b도 내지 제2e도와 동일하게 진행된다.FIG. 3 is another embodiment of the present invention and as described in FIG. 2A, an undoped polysilicon film 13 may be interposed between the oxide film 11 and the nitride film 12, and subsequent processes may be performed in FIGS. The same goes for 2e.

상기한 설명에서 알수 있는 바와 같이 소오스/드레인 전극의 상부에 실리사이드를 형성하여 금속배선과 접속되게 하므로써 스파이킹 현상을 방지할 수 있으며 이는 필드산화막 상부에도 연장되어 존재하게 되므로 소오스/드레인 전극과 금속배선과의 접속 여유도를 증가시킬 수 있다.As can be seen from the above description, by forming a silicide on the top of the source / drain electrode to be connected to the metal wiring, it is possible to prevent the spiking phenomenon. Can increase the connection margin.

또한 가상의 필드산화막을 이용하여 실리콘기판에 대한 게이트전극의 단차를 감소시킬 수 있다.In addition, the step of the gate electrode with respect to the silicon substrate can be reduced by using a virtual field oxide film.

Claims (4)

반도체 모스펫 제조방법에 있어서, 실리콘기판에 P-웰을 형성하고 산화막과 질화막을 적층한 다음 사진 식각법으로 활성영역의 실리콘기판 상부에만 산화막과 질화막을 남도록 하는 동시에 활성영역중 게이트전극이 형성될 부분은 식각되도록 하고 전체적으로 P+형 불순물을 주입하여 채널스토퍼 영역을 형성하는 공정과, 비활성영역에 필드산화막을 활성영역에 가상의 필드산화막을 동시에 형성하고, 질화막과 산화막을 제거한 후 필드산화막과 가상필드산화막 상부에 감광막 패턴을 형성하고 실리콘기판에 N+이온주입 영역을 형성하는 공정과, 감광막 패턴을 제거하고 그 상부에 전체적으로 폴리실리콘막을 적층하고 가상 필드산화막 부분을 제외한 나머지 부분에 감광막 패턴을 형성한 다음 폴리실리콘막과 가상필드산화막 제거하여 트렌치를 형성하는 공정과, 감광막 패턴을 제거한 후 트렌치 내부에 공지의 기술로 게이트전극을 형성하고 트렌치 내부에 게이트산화막과 게이트전극을 형성하고 공정과, PSG막을 전체적으로 증착하고 고온 열처리하여 도프된 N-이온을 게이트전극 주변의 실리콘기판(1)에 확산시켜 N-영역을 형성하는 공정과, 블랜켓 식각공정으로 상기 PSG막을 상기 폴리실리콘막이 노출되기까지 식각하여 게이트전극을 측면에 PSG막잔여물을 남기는 공정과, 폴리실리콘막과 게이트전극의 상부에 실리사이드막을 형성하고 전체구조 상부에 층간절연층을 형성하고, 사진식각공정으로 층간절연층의 일정부분을 제거하여 상기 실리사이드가 노출되는 콘택홀을 형성하고, 금속배선을 형성하는 공정으로 이루어져 금속배선을 하부 도전층에 콘택할 때 스파이키잉이 발생되지 않도록 형성하는 것을 특징으로 하는 반도체 모스켓 제조방법.In the method of manufacturing a semiconductor MOSFET, a P-well is formed on a silicon substrate, an oxide film and a nitride film are laminated, and a portion of the active region where the gate electrode is formed while the oxide film and the nitride film are left only on the silicon substrate in the active region by photolithography. To form a channel stopper region by injecting P + -type impurities and forming a field oxide film in the inactive region and a virtual field oxide film in the active region at the same time, removing the nitride film and the oxide film, and then removing the field oxide film and the virtual field. Forming a photoresist pattern on the oxide film and forming an N + ion implantation region on the silicon substrate, removing the photoresist pattern, stacking a polysilicon film on the whole, and forming a photoresist pattern on the remaining portions except the virtual field oxide Next, remove the polysilicon film and the virtual field oxide film to St. step and, after removing the photoresist pattern to form a gate electrode as a known technique in the trench and the formation of the gate oxide film and gate electrode in the trench and the step, PSG a deposited film as a whole and the high temperature heat treatment doped N to - the ion Diffusing the silicon substrate (1) around the gate electrode to form an N − region, and etching the PSG film until the polysilicon film is exposed by a blanket etching process to leave the PSG film residue on the side of the gate electrode. And forming a silicide film on the polysilicon film and the gate electrode, forming an interlayer insulating layer on the entire structure, and removing a portion of the interlayer insulating layer by a photolithography process to form a contact hole through which the silicide is exposed. It is a process of forming metal wiring so that spiking does not occur when the metal wiring is contacted with the lower conductive layer. MOS semiconductor jacket manufacturing method characterized by forming. 제1항에 있어서, 산화막과 질화막 사이에 패드용으로 불순물이 도핑되지 않는 폴리실리콘막을 더 적층하는 것을 포함하는 반도체 모스펫 제조방법.The method of claim 1, further comprising laminating a polysilicon film that is not doped with impurities for the pad between the oxide film and the nitride film. 제1항에 있어서, 상기 실리사이드는 폴리 실리콘막과 게이트전극에 선택적으로 전이금속을 증착한 후 열처리하여 형성되는 것을 특징으로 하는 반도체 모스켓 제조방법.The method of claim 1, wherein the silicide is formed by selectively depositing a transition metal on a polysilicon film and a gate electrode and then heat treating the transition metal. 제1항에 있어서, 상기 블랜켓 식각공정으로 상기 PSG막을 상기 폴리실리콘막이 노출되기 까지 식각할 때 PSG막과 폴리실리콘막의 식각 선택비가 5 : 1 이상으로 하는 것을 특징으로 하는 반도체 모스펫 제조방법.The method of claim 1, wherein the etching selectivity of the PSG film and the polysilicon film is 5: 1 or more when the PSG film is etched until the polysilicon film is exposed by the blanket etching process.
KR1019930031827A 1993-12-31 1993-12-31 Fabrication method of mosfet KR970006268B1 (en)

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KR1019930031827A KR970006268B1 (en) 1993-12-31 1993-12-31 Fabrication method of mosfet
US08/365,293 US5620911A (en) 1993-12-31 1994-12-28 Method for fabricating a metal field effect transistor having a recessed gate
DE4447254A DE4447254C2 (en) 1993-12-31 1994-12-30 Method of manufacturing a metal oxide semiconductor field effect transistor
JP7000039A JP2624948B2 (en) 1993-12-31 1995-01-04 MOS-FET manufacturing method

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