JPH04215451A - Semiconductor device - Google Patents

Abstract

PURPOSE:To accurately monitor the characteristic of the MOS transistor of a semiconductor integrated circuit. CONSTITUTION:Dummy layers 7 and 8 composed of the same material as a gate electrode 4 are extended along the gate electrode 4 on a semiconductor substrate 1. Wiring 11 and 12 are connected with a source area 5 and a drain area 6, respectively, through the dummy layers 7 and 8 on the source area 5 and the drain area 6.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor device.
In particular, MIS for monitoring characteristics in semiconductor integrated circuits.
This is suitable for application to transistors.

0002

[Prior Art] In semiconductor integrated circuits such as MOSLSI, a single characteristic monitoring MOS transistor is installed inside the semiconductor integrated circuit body in order to monitor whether desired transistor characteristics are obtained after the wafer process is completed. Free space and TEG (test elem)
(ent group) area.

FIGS. 3 and 4 show an example of a characteristic monitoring MOS transistor conventionally used in MOSLSI. As shown in FIGS. 3 and 4, for example, p
A field insulating film 102 is formed on the surface of a type silicon (Si) substrate 101, thereby providing isolation between elements. A gate insulating film 103 is formed on the surface of the active region surrounded by this field insulating film 102. Reference numeral 104 indicates a gate electrode formed of a polycrystalline Si film doped with impurities.

[0004] In the p-type Si substrate 101, there is a gate electrode 1.
n+ type source region 105 in self-alignment with respect to 04
and a drain region 106 are formed.

Reference numeral 107 indicates an interlayer insulating film. Further, numerals 108, 109, and 110 indicate aluminum (Al) wiring. Here, the Al wiring 108 is connected to the interlayer insulating film 107.
The gate electrode 104 is connected to one end 104a having a wider width through a contact hole 107a formed in the gate electrode 104. Further, the Al wiring 109 is connected to the interlayer insulating film 1
Contact holes 107b and 107c formed in 07
, 107d to the source region 105. Further, the Al wiring 110 is connected to contact holes 107e, 107f, 107 formed in the interlayer insulating film 107.
It is connected to the drain region 106 through g.

[0006]

[Problems to be Solved by the Invention] As mentioned above, since the characteristic monitoring MOS transistor is formed in an empty space within the semiconductor integrated circuit body, it is necessary to There are no other gate electrodes. That is, it can be said that the gate electrode 104 of this characteristic monitoring MOS transistor is sparse. On the other hand, the M of the semiconductor integrated circuit itself
The gate electrode of the OS transistor is densely formed.

By the way, when a resist pattern is formed by photolithography, even if the pattern width on the photomask (or reticle) is the same, a sparse resist pattern has a larger pattern width than a dense resist pattern. It has a characteristic. Therefore, even if the gate electrode 104 of the MOS transistor for characteristic monitoring is designed to have the same width as the gate electrode of the MOS transistor of the semiconductor integrated circuit itself, the MOS transistor for characteristic monitoring
Since the gate electrode 104 of the transistor is sparser than the gate electrode of the MOS transistor of the semiconductor integrated circuit itself, the width of the gate electrode 104 of the actually formed characteristic monitoring MOS transistor is equal to the width of the MOS transistor of the semiconductor integrated circuit itself. The width of the gate electrode becomes larger than the width of the gate electrode. As a result, even if the characteristics of this characteristic monitoring MOS transistor are measured, there is a problem in that the characteristics of the MOS transistor of the semiconductor integrated circuit itself cannot be accurately monitored.

Therefore, an object of the present invention is to provide a semiconductor device that can accurately monitor the characteristics of the MIS transistor of a semiconductor integrated circuit itself by using it as a characteristic monitoring MIS transistor and measuring its characteristics. It is in.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a gate insulating film (
A gate electrode (4) is formed through the semiconductor substrate (1), and a source region (5) and a drain region (5) are formed in the semiconductor substrate (1).
6), dummy layers (7, 8) made of the same material as the gate electrode (4) extend on the semiconductor substrate (1) along the gate electrode (4). Wirings (11, 12) are connected to the source region (5) and drain region (6) via dummy layers (7, 8) on the source region (5) and drain region (6), respectively.

0010

[Operation] According to the semiconductor device of the present invention configured as described above, the distance between the gate electrode (4) and the dummy layers (7, 8) extending along the gate electrode (4) is reduced. For example, the distance between the resist pattern for forming the gate electrode (4) of this semiconductor device and the gate electrode of the MIS transistor of the semiconductor integrated circuit can be set to be almost the same as the interval between the gate electrodes of the MIS transistor of the semiconductor integrated circuit itself. It is possible to eliminate the difference in density with respect to the resist pattern to be formed. Therefore, the width of the gate electrode (4) of this semiconductor device can be made almost the same as the width of the gate electrode of the MIS transistor of the semiconductor integrated circuit itself. Thereby, by using this semiconductor device as a MIS transistor for characteristic monitoring and measuring its characteristics, it is possible to accurately monitor the characteristics of the MIS transistor of the semiconductor integrated circuit itself.

Moreover, the wiring (1) is connected to the source region (5) and the drain region (6) through the dummy layers (7, 8) on the source region (5) and the drain region (6), respectively.
1 and 12) are connected, the parasitic resistance of the source and drain can be made sufficiently low.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a plan view of a characteristic monitoring MOS transistor according to an embodiment of the present invention, and FIG.
A sectional view taken along line 2-2 of FIG.

As shown in FIGS. 1 and 2, in this embodiment, a field insulating film 2 such as a SiO2 film is formed on the surface of a semiconductor substrate 1 such as a p-type Si substrate.
is formed, thereby providing isolation between elements. A gate insulating film 3 such as a SiO2 film, for example, is formed on the surface of the active region surrounded by the field insulating film 2. Reference numeral 4 indicates a gate electrode. This gate electrode 4 is formed of a polycrystalline Si film doped with an n-type impurity such as phosphorus (P), for example.

In the semiconductor substrate 1, for example, an n+ type source region 5 and drain region 6 are formed in self-alignment with the gate electrode 4.

In this embodiment, dummy layers 7 and 8 extend along the gate electrode 4 on both sides thereof. These dummy layers 7 and 8 are made of the same material as the gate electrode 4. Both end portions of these dummy layers 7 and 8 are placed on the field insulating film 2, and the portions between them are in contact with the source region 5 and drain region 6, respectively, by buried contacts. Here, the distance between the gate electrode 4 and these dummy layers 7 and 8 is set to be approximately the same as the distance between the gate electrodes of the semiconductor integrated circuit itself, for example, MOS transistors in its peripheral circuits. If there are a plurality of intervals between the gate electrodes of the MOS transistors of the semiconductor integrated circuit itself, the interval is set to, for example, the interval that is the largest among these intervals.

These dummy layers 7 and 8 serve as gate electrodes (not shown) of MOS transistors of the semiconductor integrated circuit itself.
and is formed simultaneously in the process of forming the gate electrode 4 of this characteristic monitoring MOS transistor. That is,
After forming the field insulating film 2 and the gate insulating film 3, a polycrystalline Si film for forming a gate electrode is formed over the entire surface by CVD. Next, this polycrystalline Si film is doped with an n-type impurity such as P to lower its resistance. Next, a resist pattern (not shown) having a shape corresponding to the gate electrode of the MOS transistor of the semiconductor integrated circuit itself, the gate electrode 4 of the MOS transistor for characteristic monitoring, and the dummy layers 7 and 8 is formed on this polycrystalline Si film. Formed by photolithography. Thereafter, using this resist pattern as a mask, the polycrystalline Si film is etched by, for example, reactive ion etching (RIE). by this,
Dummy layers 7 and 8 are formed together with the gate electrode of the MOS transistor of the semiconductor integrated circuit itself and the gate electrode 4 of this characteristic monitoring MOS transistor.

Reference numeral 9 is, for example, phosphorus silicate glass (P
SG) film or an interlayer insulating film such as a SiO2 film. Further, reference numerals 10, 11, and 12 indicate, for example, Al wiring. Here, the Al wiring 10 is connected to one end 4a of the gate electrode 4 having a wider width through a contact hole 9a formed in the interlayer insulating film 9. Further, the Al wiring 11 is connected to the dummy layer 7 over the source region 5 through contact holes 9b, 9c, and 9d formed in the interlayer insulating film 9. As mentioned above, since this dummy layer 7 is in contact with the source region 5, this A
The l wiring 11 is connected to the source region 5 via this dummy layer 7. Furthermore, the Al wiring 12 is connected to the dummy layer 8 over the drain region 6 through contact holes 9e, 9f, and 9g formed in the interlayer insulating film 9. Since this dummy layer 8 is in contact with the drain region 6, this Al wiring 11 is connected to the drain region 6 via this dummy layer 8.

The characteristic monitoring MOS transistor of this embodiment configured as described above is formed in an empty space within the semiconductor integrated circuit body, for example, in an empty space between pads at the periphery of the semiconductor integrated circuit chip.

As described above, according to this embodiment, the dummy layers 7 and 8 made of the same material as the gate electrode 4 are extended along the gate electrode 4, and the dummy layers 7 and 8 are made of the same material as the gate electrode 4. Since the spacing between 7 and 8 is set to be almost the same as the spacing between the gate electrodes of the MOS transistor of the semiconductor integrated circuit itself, the gate electrode of the MOS transistor of the semiconductor integrated circuit itself and the gate of this characteristic monitoring MOS transistor are In the photolithography process for forming a resist pattern for forming the electrode 4, a resist pattern for forming the gate electrode 4 of this characteristic monitoring MOS transistor and a gate electrode of the MOS transistor of the semiconductor integrated circuit itself are formed. It is possible to eliminate the difference in density with respect to the resist pattern. Thereby, the width of the gate electrode 4 of this characteristic monitoring MOS transistor can be made the same as the width of the gate electrode of the MOS transistor of the semiconductor integrated circuit itself. Therefore, by measuring the characteristics of this characteristic monitoring MOS transistor, the MOS transistor of the semiconductor integrated circuit itself can be
Transistor characteristics can be accurately monitored.

Further, wiring 11 is connected to dummy layer 7 through contact holes 9b, 9c, and 9d above source region 5.
Since the wiring 12 is brought into contact with the dummy layer 8 through the contact holes 9e, 9f, and 9g above the drain region 6, the parasitic resistance of the source and drain can be sufficiently reduced.

The characteristic monitoring MOS transistor according to this embodiment can be used for bipolar CM as well as MOSLSI.
It is suitable for application to MOS transistors for monitoring characteristics in OSLSI and the like.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made based on the technical idea of the present invention.

For example, as the material of the gate electrode 4 mentioned above, and thus the material of the dummy layers 7 and 8, in addition to the impurity-doped polycrystalline Si film, for example, a material on the impurity-doped polycrystalline Si film may be used. It is also possible to use a polycide film in which high melting point metal silicide films such as tungsten silicide films are stacked.

Furthermore, the characteristic monitoring MO of the above-mentioned embodiment
Although the S transistor is an n-channel type, this invention
The present invention can be similarly applied to a case where the characteristic monitoring MOS transistor is of a p-channel type.

[0026]

As explained above, in the semiconductor device of the present invention, a dummy layer made of the same material as the gate electrode extends on the semiconductor substrate along the gate electrode, and the dummy layer is made of the same material as the gate electrode. Since wiring is connected to the source region and the drain region through the dummy layer in the semiconductor integrated circuit, the characteristics of the MIS transistor of the semiconductor integrated circuit itself can be determined by using this semiconductor device as a characteristic monitoring MIS transistor and measuring its characteristics. can be accurately monitored.

[Brief explanation of the drawing]

FIG. 1: MO for monitoring characteristics according to an embodiment of the present invention
FIG. 2 is a plan view showing an S transistor.

FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. 1;

FIG. 3 is a plan view showing an example of a conventional characteristic monitoring MOS transistor.

FIG. 4 is a cross-sectional view taken along line 4-4 in FIG. 3;

[Explanation of symbols]

1 Semiconductor substrate 3 Gate insulating film 4 Gate electrode 5 Source area 6 Drain region 7 Dummy layer 8 Dummy layer 11 Wiring 12 Wiring

Claims (1)

[Claims] 1. A semiconductor device in which a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region are formed in the semiconductor substrate, wherein the gate electrode is made of the same material as the gate electrode. A dummy layer consisting of a dummy layer extends on the semiconductor substrate along the gate electrode, and wirings are connected to the source region and the drain region via the dummy layer on the source region and the drain region, respectively. A semiconductor device characterized by: