JPH05145026A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a transistor constituting a semiconductor device, when a high voltage surge caused by power supply noise or the like is applied to the semiconductor device. CONSTITUTION:The title device is constituted of the following; a part where the element activation region 1 of a transistor is directly connected with a power supply wiring 3, and a part where the element activation region 1 of a transistor is connected with a power supply wiring 3a via a power supply wiring intermediate layer 4 arranged so as not to overlap with a gate electrode 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved surge breakdown voltage of a transistor having a source / drain connected to a power supply.

[0002]

2. Description of the Related Art FIG. 5 is a layout diagram showing an example of transistor layout in a conventional semiconductor device. Reference numeral 1 is an element activation region of a transistor, 2 is a gate electrode of a transistor, 3b is a power supply wiring to which a power source Vcc is applied, 4a is a power supply wiring intermediate connecting a power supply wiring 3b and a source side of a device activation area 1 of a transistor. Layers 5 are output wirings of the transistors.

Reference numeral 6 denotes an output wiring intermediate layer for connecting the output wiring 5 of the transistor and the drain side of the transistor element activation region 1, and 7 denotes the transistor element activation region 1 and the power supply wiring intermediate layer 4a or the output wiring intermediate layer. Reference numeral 8 is a self-aligned contact hole for connecting with 6, and reference numeral 8 is a contact hole formed by photolithography for connecting the power supply wiring intermediate layer 4a and the power supply wiring 3b.

The power supply wiring intermediate layer 4a is arranged so that the area occupied by the transistors is minimized, and the contact hole 8 is formed.
Are arranged so as to overlap the gate electrode 2 in order to secure a margin.

Reference numeral 9 is a contact hole formed by photolithography for connecting the output wiring intermediate layer 6 and the output wiring 5, 10 is a signal wiring for transmitting an input signal to the gate electrode 2, and 11 is a gate electrode 2 and the output wiring. 5 is a contact hole formed by photolithography for connecting the signal line 10 and the signal line 10.

FIG. 6 shows a sectional view taken along the alternate long and short dash line CC in FIG. An N-type semiconductor region 14 for forming a P-type channel transistor is formed on a P-type semiconductor wafer substrate 13 for forming a semiconductor device, for example, by implanting phosphorus (P) as an N-type impurity by an ion implantation method.

Next, an element isolation insulating film 15 for isolating each element and an element activation region 1 of a transistor are formed on the N-type semiconductor region 14 by the LOCOS method. The element active region 1 of the transistor is an element isolation insulating film 1
It is an area between the five.

Next, boron (B) is implanted by ion implantation in order to obtain a desired transistor threshold value to form a P-type semiconductor region 16 serving as a buried channel that determines the threshold value of the P-type channel transistor, and the gate is thermally oxidized. The insulating film 17 is formed, a gate electrode is deposited by CVD, and the gate electrode 2 is formed by photolithography and dry etching.

Further, after the framed insulating film 18 is formed, boron (B) is implanted by an ion implantation method to form the framed insulating film 1
A P-type semiconductor region 1 serving as a source / drain of a P-type channel transistor including a region having a low concentration under 8
9 is formed, and the first interlayer insulating film 20 is deposited by CVD.

Thereafter, the element activation region 1 of the transistor
To connect the power supply wiring intermediate layer 4a and the output wiring intermediate layer 6 of the transistor, a self-aligned contact hole 7 is formed by dry etching, an intermediate layer material is deposited by CVD, and electrode wiring intermediate is formed by photolithography and dry etching. The layer 4a and the output wiring intermediate layer 6 are formed.

Next, a second interlayer insulating film 21 is deposited by CVD, contact holes 8, 9 and 11 (9 and 11 not shown in FIG. 6) are formed by photolithography and dry etching, and metal is formed by sputtering. A material (aluminum, silicon, copper) is deposited, signal wiring 10, electrode wiring 3b, and transistor output wiring 5 (not shown in FIG. 6) are formed by photolithography and dry etching, and a third interlayer is formed by CVD. The insulating film 22 is deposited. Further, an LDD structure N-type channel transistor is formed in substantially the same manner.

By the way, the self-aligned contact hole 7
Can be surely formed in the element activation region 1 surrounded by the element isolation insulating film 15 and the gate electrode 2, but the contact hole formed by photolithography may be displaced due to the alignment accuracy of the photomask and the like. In order to manufacture a highly reliable transistor with high reliability, a space between the active region 1 of the transistor and the contact hole is required.

Therefore, the channel direction of the active region 1 of the transistor (direction from the source side to the drain side of the transistor) must be increased. In order to avoid this, by using the power supply wiring intermediate layer 4a and the output wiring intermediate layer 6, the intermediate layer is formed on the gate electrode 2 or the interlayer insulating film 20.
Since it is sufficient to make the region of the intermediate layer wider than the contact hole, the positional accuracy of the contact hole can be absorbed by the intermediate layer without enlarging the activation region 1 of the transistor. Area 1
Can be arranged in a small area.

As shown in FIG. 5, the power supply wiring intermediate layer 4 and the output wiring intermediate layer 6 are connected to the activation region 1 and the gate electrode 2 of the transistor.
The area of the intermediate layer can be minimized by overlapping with the channel portion of the. Also, even when using multiple layers such that the intermediate layer must be used, for example, in the case of the drain side of the transistor in FIG. 6, a small area is required and the resistance component of the intermediate layer is also small. You can

That is, a device using such a transistor structure is very effective for obtaining a semiconductor device of the smallest size. During operation, the potential Vcc is applied to the electrode wiring of the P-type channel transistor from the external power source, while the ground level potential GND is applied to the electrode wiring of the N-type channel transistor.

[0016]

However, in the semiconductor device having such a transistor structure, when a high voltage surge voltage due to noise of the power source is applied, the power source wiring intermediate layer 4a and the output wiring intermediate layer 6 are If the resistance is high,
Since the gate electrode 2 and the power supply wiring intermediate layer 4a overlap, depending on the thickness of the overlapping portion of the first interlayer insulating film 20, discharge may occur between the power supply wiring intermediate layer 4a and the gate electrode 2, and the transistor may be discharged. There was a problem that it would be destroyed.

The present invention has been made in order to solve the above problems, and a transistor constituting a semiconductor device is destroyed even when a high voltage surge voltage due to noise of a power source or the like is applied to the semiconductor device. The purpose is not to be.

[0018]

The semiconductor device of the present invention comprises:
The power supply wiring is directly connected to the source / drain impurity semiconductor region.

In the semiconductor device of the present invention, the power supply wiring is connected to the source / drain impurity semiconductor region through the intermediate layer arranged so as not to overlap the gate electrode.

[0020]

In the present invention, the source connected to the power source
Since the drain is connected to the impurity semiconductor regions of the source and drain without an intermediate layer, the resistance on the source side to be connected to the power supply does not increase, and high voltage surge voltage due to noise of the power supply does not occur. Even if applied
Discharge is less likely to occur between the power supply wiring and the gate electrode.

Further, even in a transistor in which the source / drain connection to the power supply is connected to the impurity semiconductor region of the source / drain via the intermediate layer, the gate electrode and the power supply wiring intermediate layer do not overlap each other. In addition, even when the resistance of the intermediate layer becomes high, it becomes difficult to cause a discharge between the power supply wiring intermediate layer and the gate electrode.

[0022]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a memory cell array showing an embodiment of a semiconductor device of the present invention.

In FIG. 1, 1 is an element activation region of a transistor, 2 is a gate electrode of the transistor, and 3 and 3a.
Is a power supply wiring to which the power supply Vcc is applied, 4 is a power supply intermediate layer which is arranged so as to connect the power supply wiring 3a and the source side of the element activation region 1 of the transistor and not to overlap the gate electrode 2, and 5 is a transistor Is the output wiring of.

Reference numeral 6 denotes an output wiring intermediate layer for connecting the output wiring 5 and the drain side of the element activation region 1 of the transistor, and 7
Is an element activation region 1 of a transistor and a power supply wiring intermediate layer 4
Alternatively, a self-aligned contact hole for connecting the output wiring intermediate layer 6 and a power wiring intermediate layer 4 and a power wiring 3a.
Is a contact hole formed by photolithography for connecting to.

Reference numeral 9 is a contact hole formed by photolithography for connecting the output wiring intermediate layer 6 and the output wiring 5, 10 is a signal wiring for transmitting an input signal to the gate electrode 2, and 11 is a gate electrode 2 and the signal wiring. A contact hole formed by photolithography for connecting to 10 and a contact hole 12 formed by photolithography for connecting the drain side of the element activation region 1 of the transistor and the power supply wiring 3.

FIG. 2 is a sectional view taken along one-dot chain line AA in FIG. 1. The manufacturing method will be described below. On the P-type semiconductor wafer substrate 13 for forming a semiconductor device, for example, N
Phosphorus (P) as a type impurity is implanted by an ion implantation method to form an N-type semiconductor region 14 for forming a P-type channel transistor, and an element isolation insulating film 15 for separating each element by a LOCOS method, and The element activation region 1 of the transistor is formed.

Next, boron (B) is implanted by ion implantation in order to obtain a desired transistor threshold value, a P-type semiconductor region 16 to be a buried channel for determining the threshold value of the P-type channel transistor is formed, and the gate is formed by thermal oxidation. The insulating film 17 is formed, the gate electrode material is deposited by CVD, and the gate electrode 2 is formed by photolithography and dry etching.

Further, after the framed insulating film 18 is formed, boron (B) is implanted by an ion implantation method to form the framed insulating film 1.
A P-type semiconductor region 19 serving as a source / drain of the P-type channel transistor including a region having a low concentration under 8 is formed.

After that, the first interlayer insulating film 2 is formed by CVD.
0 is deposited, a self-aligned contact hole 7 is formed by dry etching to connect the element activation region 1 of the transistor to the power supply wiring intermediate layer 4 and the output wiring intermediate layer 6, and the intermediate layer material is deposited by CVD. Electrode wiring intermediate layer 4 by photolithography and dry etching
And the output wiring intermediate layer 6 is formed.

Next, a second interlayer insulating film 21 is deposited by CVD, contact holes 8, 9, 11, 12 are formed by photolithography and dry etching, and a metal material (aluminum, silicon,
Copper) is deposited, the signal wiring 10, the power supply wiring 3, and the output wiring 5 are formed by photolithography and dry etching, and the third interlayer insulating film 22 is deposited by CVD.

As described above, the LDD structure P-type channel transistor is formed. In addition, L
A DD structure N-type channel transistor is also formed. During operation, the potential Vcc is applied to the electrode wiring of the P-type channel transistor by the external power supply, while the ground level potential GND is applied to the electrode wiring of the N-type transistor.

In the above embodiment, the power supply line 3 is not connected to the first transistor directly connected to the impurity semiconductor regions of the source / drain and the power supply line 3 arranged so as not to overlap the gate electrode 2. The layer 4 is composed of a power supply wiring 3a and a second transistor having a source / drain connected to each other. As shown in FIGS.
It is also possible to configure the above transistor in the same manner as the second transistor and to use only the transistor in which the power source wiring 3a and the source / drain are connected by the power source wiring intermediate layer 4 arranged so as not to overlap the gate electrode 2. ..

In this case, it is most suitable for making the distance in the channel direction (source to drain direction) smaller than that in the above-mentioned embodiment.

Although the P-type channel transistor has been described in the above embodiments, the same applies to the N-type channel transistor, and any material and structure may be used as long as it is the same as the manufacturing apparatus for making the structure. .. Also, LD
Although the D-structure transistor has been described, it goes without saying that the same applies to MIS transistors having other structures.

[0035]

As described above, in the semiconductor device according to the present invention, the source / drain impurity semiconductor regions connected to the power supply are directly connected to the power supply wiring. Discharge between the wiring and the gate electrode is less likely, and the transistor is less likely to be destroyed.

On the other hand, since the source / drain impurity semiconductor regions connected to the power supply are connected to the power supply wiring in the intermediate layer which does not overlap with the gate electrode, even if the resistance of the intermediate layer is high, the power supply is not affected. The resistance on the connected source side does not increase, and even if a high-voltage surge voltage due to noise from the power supply is applied, the transistor will not be destroyed due to no discharge between the power supply wiring and the gate electrode. Have.

[Brief description of drawings]

FIG. 1 is a layout view of transistors of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a layout view of transistors of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a sectional view taken along line BB of FIG.

FIG. 5 is a transistor layout diagram showing an example of a conventional semiconductor device.

6 is a cross-sectional view taken along the line CC of FIG.

[Explanation of symbols]

 1 Transistor element activation region 2 Gate electrode 3, 3a Power supply wiring 4 Power supply wiring intermediate layer 5 Output wiring 6 Output wiring intermediate layer 7 Self-aligned contact hole 8, 9, 11, 12 Contact hole 10 Signal wiring

[Procedure amendment]

[Submission date] August 24, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Next, a second interlayer insulating film 21 is deposited by CVD, contact holes 8, 9 and 11 (9 and 11 not shown in FIG. 6) are formed by photolithography and dry etching, and metal is formed by sputtering. Material ( example
AlSiCu etc.) is deposited eg to signal wiring by photolithography and dry etching 10 and the electrode wiring 3
b and the output wiring 5 (not shown in FIG. 6) of the transistor are formed, and the third interlayer insulating film 22 is deposited by CVD. Further, an LDD structure N-type channel transistor is formed in substantially the same manner.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

By the way, the self-aligned contact hole 7
Can be surely formed in the element activation region 1 surrounded by the element isolation insulating film 15 and the gate electrode 2, but the contact hole formed by photolithography may be displaced due to the alignment accuracy of the photomask and the like. In order to manufacture a highly reliable transistor with high reliability, it is necessary to secure a sufficient distance between the gate electrode 2 of the transistor and the contact hole.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

The area of the intermediate layer can be minimized by overlapping the power supply wiring intermediate layer 4a and the output wiring intermediate layer 6 on the active region 1 of the transistor and the channel portion of the gate electrode 2 as shown in FIG. Also, even when using multiple layers such that the intermediate layer must be used, for example, in the case of the drain side of the transistor in FIG. 6, a small area is required and the resistance component of the intermediate layer is also small. You can

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

[0022]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows two semiconductor devices according to one embodiment of the present invention.
3 is a plan view of the transistor of FIG.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

Next, a second interlayer insulating film 21 is deposited by CVD, contact holes 8, 9, 11, 12 are formed by photolithography and dry etching, and a metal material ( for example , AlSiCu) is formed by sputtering.
And the signal wiring 10, the power supply wiring 3, and the output wiring 5 are formed by photolithography and dry etching.
The third interlayer insulating film 22 is deposited by VD.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaki Tsuide 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Laboratory

Claims (2)

[Claims] 1. A plurality of transistors each having a wiring in which an impurity semiconductor region serving as a source / drain is connected through an intermediate layer and a power supply wiring directly connected to the impurity semiconductor region serving as a source / drain. A semiconductor device characterized by. 2. An impurity semiconductor region serving as a source / drain is connected to a wiring via an intermediate layer, and a wiring of the wiring connected to a power source is interposed via the intermediate layer arranged so as not to overlap the gate electrode. A semiconductor device comprising a plurality of transistors connected to a region.