JP2009200197A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure by which two or more different fuses are laminated, a concrete relieving measure for the structure, and to provide a method of manufacturing an identification grant of a semiconductor device. <P>SOLUTION: The semiconductor device includes a primary fuse that blows out by applying a predetermined voltage value or drawing a current higher than a predetermined current value, a secondary fuse that is blown by irradiating a laser beam, and a reflector layer that reflects a laser beam. Further, in the semiconductor device, the reflector layer is laminated onto the primary fuse using an insulating layer, and the secondary fuse is laminated onto the reflector layer through an insulating layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a plurality of different types of fuses and a manufacturing method thereof.

  In recent years, since the capacity of semiconductor devices has increased, for example, it is difficult to manufacture all memory cells constituting the memory unit without malfunction and to function normally. Therefore, the semiconductor device is provided with a redundant circuit for replacing a memory array (column array, row array) having defective memory cells with a spare memory array, and a fuse is used for replacement with the redundant circuit. . In general, by cutting a fuse, a memory array having a defective memory cell cannot be selected, and a spare memory array can be selected.

  Here, the fuse includes a laser fuse and an electric fuse. Information can be written in the laser fuse by fusing the conductive portion by laser light irradiation. On the other hand, the electrical fuse can write information by applying a high voltage to both terminals to cause dielectric breakdown of the capacitance or by blowing a wiring by passing a current.

Further, in a semiconductor device, it is sufficient to increase the number of redundant circuits in order to increase the repair yield. However, an area of about several tens of μm ² is necessary to repair one defect, and the area occupied by the fuse is larger than the entire chip. The size is not negligible.

  Therefore, Patent Document 1 discloses a configuration that can reduce the area occupied by fuses by stacking a plurality of fuses in the vertical direction.

JP 2006-73947 A

  However, when a plurality of different types of fuses are stacked, the configuration and the specific repair flow when laser fuses and electrical fuses are stacked are not disclosed in Patent Document 1.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a structure in which a plurality of different types of fuses are stacked, and a manufacturing method that performs specific relief for the structure and identification of a semiconductor device.

  In one embodiment of the present invention, a first fuse that is cut by applying a predetermined voltage value or flowing a predetermined current value or more, a second fuse that is cut by irradiating laser light, and a laser In the semiconductor device according to one embodiment of the present invention, the reflector layer is stacked on the first fuse via the insulating layer, and is insulated on the reflector layer. A second fuse is stacked through the layers.

  In one embodiment of the present invention, the reflector layer is laminated on the first fuse via the insulating layer, and the second fuse is laminated on the reflector layer via the insulating layer, so that each fuse functions properly. However, it is possible to arrange the fuses more efficiently than when a single fuse is arranged for each, and it is possible to reduce the area occupied by the fuses.

(Embodiment 1)
FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment. In the semiconductor device shown in FIG. 1, a wiring region where a normal wiring of the semiconductor device is formed and a fuse forming region where a fuse is formed are provided. This is a schematic representation. The semiconductor device in FIG. 1 includes a Si substrate 2 in the lower layer. An inter-element isolation region 4 is formed on the Si substrate 2, and a well (not shown) or the like is formed in each region isolated by the inter-element isolation region 4 as necessary. On the Si substrate 2 shown in FIG. 1, a gate electrode 8 is formed via a gate insulating film 6. Sidewalls 10 are formed on both sides of the gate electrode 8 on the Si substrate 2 via a gate insulating film 6. Impurity diffusion layers (source / drain and extension) 12 are formed on both sides of the gate electrode 8 near the surface of the Si substrate 2. A PTEOS film 14 is formed on the Si substrate 2 by embedding the gate electrode 8 and the like. Here, the PTEOS film 14 is a film formed by plasma chemical vapor deposition (p-CVD) using TEOS (tetraethyl orthosilicate). Contact plugs 16 penetrating the PTEOS film 14 and connected to the gate electrode 8 and the surface of the Si substrate 2 are formed.

  On the other hand, in the fuse formation region of the semiconductor device shown in FIG. 1, polyfuses 200 (201 to 204) are formed on the Si substrate 2 using the gate electrode 8. The polyfuse is an electric fuse, and is changed from a conductive state to an open state by applying a voltage from the outside and fusing the polyfuse material.

  Next, a wiring made of barrier metal 24 and Cu 26 is formed in the first wiring layer on the contact layer made of the PTEOS film 14 shown in FIG. Furthermore, wirings made of barrier metal 38a and Cu 40a are formed in the first via layer and the second wiring layer stacked on the first wiring layer. Similarly, as shown in FIG. 1, layers from the second via layer to the fifth wiring layer are sequentially stacked to form a wiring made of barrier metals 38b, c, d and Cu 40b, c, d. Note that the film thickness from the first wiring layer to the fifth wiring layer is the same, and the sixth wiring layer and the seventh wiring layer have a wiring film thickness compared to the first wiring layer to the fifth wiring layer. A thick wiring is formed. For example, the first wiring layer is formed with a wiring layer having a thickness of about 350 nm with respect to 175 nm.

  In the semiconductor device shown in FIG. 1, the wiring fuse 100, which is an electric fuse, is formed in the fuse formation region of the wiring layer using the first to fifth wiring layers having a small thickness. The wiring fuse 100 includes a wiring fuse 101 formed using the same material as the barrier metal 24 and Cu 26 in the first wiring layer, and a wiring fuse formed using the same material as the barrier metal 38a and Cu 40a in the second wiring layer. 102, a wiring fuse 103 formed on the third wiring layer using the same material as the barrier metal 38b and Cu 40b, and a wiring fuse 104 formed on the fourth wiring layer using the same material as the barrier metal 38c and Cu 40c. The fifth wiring layer includes a wiring fuse 105 formed using the same material as the barrier metal 38d and Cu 40d. In addition, as shown in FIG. 1, the wiring fuses 101-105 are arrange | positioned so that each layer may not overlap. Moreover, the wiring fuse melts the barrier metal and Cu, which are constituent materials, by applying a voltage from the outside, and changes from a conductive state to an open state.

  Next, a Cu reflector layer 42 is formed so as to straddle the fuse forming regions of the sixth wiring layer, the sixth via layer, and the seventh wiring layer. Specifically, the sixth wiring layer includes a wiring made of a barrier metal 38e and Cu 40e in the wiring area, and a barrier metal 42b and a Cu reflector layer 42a formed in the fuse forming area with the same material. Similarly, the seventh wiring layer includes a wiring made of the barrier metal 38f and Cu 40f in the wiring area, and a barrier metal 42e and a Cu reflector layer 42d formed in the fuse forming area with the same material. Further, a Cu reflector connection layer 42c for connecting the Cu reflector layer 42a and the Cu reflector layer 42d is formed in the sixth Via layer.

  Next, in the semiconductor device shown in FIG. 1, a wiring made of barrier metal 38g and Cu 40g is formed in the wiring region of the eighth wiring layer stacked on the seventh via layer, and a laser fuse 50 is formed in the fuse forming region of the eighth wiring layer. Is formed. The laser fuse 50 is composed of a barrier metal 50a and Cu 50b. The eighth wiring layer is composed of a SiOF film 36e and a PTEOS film 36f.

  Further, a SiCN film 52 is formed on the PTEOS film 36f, the wiring exposed on the surface thereof, and the laser fuse 50. A PTEOS film 54 is formed on the SiCN film 52. A tungsten plug 55 is formed through the PTEOS film 54 and the SiCN film 52. In the wiring region, an Al pad 56 connected to the tungsten plug 55 is formed on the PTEOS film 54. A barrier metal 58 made of TiN is formed on a part of the surface of the Al pad 56. On the PTEOS film 54, a PTEOS film 60 and a SiN film 62 are stacked as a passivation film for embedding the Al pad 56.

  A polyimide 64 is formed on the SiN film 62 as a protective film. An opening 66 that penetrates the barrier metal 58, the PTEOS film 60, the SiN film 62, and the polyimide 64 is formed in the region on the Al pad 56, and the surface of the Al pad 56 is exposed at the bottom of the opening 66. In the fuse formation region, an opening 68 penetrating the PTEOS film 54, the PTEOS film 60, the SiN film 62, and the polyimide 64 is formed. Therefore, only one layer of the SiCN film 52 is formed on the laser fuse 50, and the positional relationship between the laser fuse 50 and the Cu reflector layer 42 is as shown in the schematic diagram of the opening 68 shown in FIG.

  Since the semiconductor device according to the present embodiment is configured as shown in FIGS. 1 and 2, the laser fuse 50 is formed in the uppermost layer of the wiring layer laminated in multiple layers, and the laser fuse 50 is formed on the laser fuse 50. Only the SiCN film 52 is formed.

  Further, in the sixth and seventh wiring layers immediately below the laser fuse 50, the three Cu reflector layers 42 (42a, 42c, 42d) are arranged, so that the influence upon cutting of the laser fuse 50 is arranged in the lower layer. Prevents electrical fuses (wiring fuses and polyfuses) from reaching. Usually, a laser having a wavelength in the near-infrared region is used for cutting the laser fuse 50. Since the reflectance of Cu with respect to this light is 99% or more, the Cu reflector layer 42 has a large part of the irradiated light. Reflect on the surface. Therefore, there is almost no light that passes through the Cu reflector layer 42 and reaches the lower layer, and the wiring fuses 101 to 105 and the polyfuses 201 to 204 that are electric fuses disposed under the laser fuse 50 have a lower There is almost no influence of the laser beam at the time of cutting.

  In the present embodiment, as the reflector layer, the Cu reflector layer 42 using Cu, which is the same material as the wiring material, is used. However, the present invention is not limited to this, and the laser beam when the laser fuse 50 is cut is reflected. However, other materials may be used as long as the material can reduce the influence on the lower layer. For example, the reflector layer may be made of Al.

  As described above, in the semiconductor device according to the present embodiment, fuses of different types (wiring fuses 101 to 105, polyfuses 201 to 204, and laser fuse 50) are stacked and arranged, and the laser fuse 50 and the electrical fuse are arranged. By providing a reflector layer between the fuse and each fuse, the fuses can function properly, and the fuses can be arranged more efficiently than when a single fuse is arranged in each. It becomes possible to do.

  In the semiconductor device shown in FIG. 1, the electric fuse has a structure in which the wiring fuse and the polyfuse are stacked. However, the present invention is not limited to this, and an electric fuse having another structure may be stacked. Alternatively, the wiring fuse alone or the polyfuse alone may be used.

(Embodiment 2)
The semiconductor device according to the present embodiment also employs a configuration in which a plurality of different fuses are stacked as shown in FIG. 1, but the configuration of the wiring fuse 100 that is an electrical fuse is different from that of the first embodiment. Hereinafter, the configuration of the wiring fuse 100 will be specifically described, but the other configurations are the same, and thus detailed description thereof is omitted.

  In the wiring fuse 100 according to the present embodiment, as shown in FIG. 3, the contamination prevention layer 110 and the via wiring 120 are formed so as to surround the wiring fuse 100, and the distance between the wiring fuse 100 and the contamination prevention layer 110 is At least 400 nm or more (in the case of a fine layer, two or more layers) are opened. Therefore, contamination caused by cutting the wiring fuse 100 does not affect other wirings and fuses.

  In FIG. 3, the fine layers from the M1 layer to the M5 layer are illustrated, the contamination prevention layer 110 is formed on the M1 layer and the M5 layer, and the wiring fuse 100 is formed on the M3 layer. In FIG. 3, only one wiring fuse 100 is described for the sake of simplicity. However, the present invention is not limited to this, and a plurality of wiring fuses 100 are stacked as shown in FIG. It may be a configuration.

  Next, the distance between the contamination prevention layer 110 and the via wiring 120 and the wiring fuse 100 will be specifically described. FIG. 4 shows a cross-sectional view when the contamination prevention layer 110 is provided in the M4 layer and the distance from the M3 layer wiring fuse 100 is 200 nm. FIG. 5 is a cross-sectional view when the contamination prevention layer 110 is provided in the M2 layer and the distance from the M3 layer wiring fuse 100 is 200 nm. 3 to 5, the distance between the via wiring 120 and the wiring fuse 100 is configured to be at least 400 nm.

  6 to FIG. 6 show the results of measuring the fuse current before and after the cutting process (process for applying a current of a predetermined current value or more for cutting) to the wiring fuse 100 having the structure shown in FIGS. 8 respectively. The results shown in FIGS. 6 to 8 show that 1000 wiring fuses 100 each having the structure shown in FIGS. 3 to 5 exist, and the fuse current before and after the cutting process is measured for each electric fuse. Therefore, the horizontal axis of FIGS. 6 to 8 is a fuse number from 1 to 1000.

  The result shown in FIG. 7 is the result using the wiring fuse 100 having the structure shown in FIG. In the result of FIG. 7, the fuse current before the cutting process of the wiring fuse 100 flows about 0.02 A, but after the cutting process of the wiring fuse 100, most of the fuse current is about 1.0E-07A or 1.0E-08A. However, those that vary from about 1.0E-04A to about 1.0E-06A and those that are defective in cutting that flow 1.0E-03A or more are included. That is, the result of FIG. 7 means that when the distance between the M4th contamination prevention layer 110 and the wiring fuse 100 is 200 nm, the relief rate in the wiring fuse 100 decreases.

  Similarly, the result shown in FIG. 8 is a result using the wiring fuse 100 having the structure shown in FIG. In the result of FIG. 8, the fuse current before the cutting process of the wiring fuse 100 flows about 0.02 A, but most of the fuse current after the cutting process of the wiring fuse 100 is about 1.0E-07A. Cutting defects that flow over 0E-03A are included. That is, the result shown in FIG. 8 means that when the distance between the M2th contamination prevention layer 110 and the wiring fuse 100 is 200 nm, the relief rate in the wiring fuse 100 decreases.

  On the other hand, the result shown in FIG. 6 is a result of using the wiring fuse 100 having the structure shown in FIG. In the result of FIG. 6, the fuse current before the cutting process of the wiring fuse 100 flows about 0.02 A, but after the cutting process of the wiring fuse 100, most of the fuse current is stable at about 1.0E-08 A. That is, the result shown in FIG. 6 means that when the distance between the M1 and M5 contamination prevention layers 110 and the wiring fuse 100 is 400 nm, the relief rate in the wiring fuse 100 does not decrease.

  From the results shown in FIGS. 6 to 8, if the contamination prevention layer 110 is too close to the wiring fuse 100, heat generated during the cutting process of the wiring fuse 100 escapes through the contamination prevention layer 110, and the temperature of the wiring fuse 100 at the time of cutting is lost. However, the melting point is not reached and cutting failure is considered to occur. Therefore, in the electrical fuse according to the present embodiment, it is necessary to keep the distance between the contamination prevention layer 110 and the wiring fuse 100 at least 400 nm in order to cut the applied current to a minimum and stably.

  Considering from the viewpoint of releasing heat generated during the cutting process of the wiring fuse 100, it is necessary to keep the distance between the via wiring 120 and the wiring fuse 100 at least 400 nm. Further, even in a configuration without the contamination prevention layer 110 as shown in FIG. 1, the distance from the wiring fuse 100 to the Cu reflector layer 42, wiring (Cu 40 a to d), polyfuse 20, etc. is at least 400 nm for the same reason. Need to keep on.

  As described above, the wiring fuse 100 according to the present embodiment can avoid a reduction in the repair rate of the wiring fuse 100 by adopting the above configuration. When the wiring layer shown in FIG. 3 or the like is formed of a fine layer, since one layer is about 200 nm, it is necessary to form the contamination prevention layer 110 at least two layers away from the wiring fuse 100.

(Embodiment 3)
Next, a method for manufacturing a semiconductor device in which the semiconductor device according to the above embodiment is repaired by a test and a fuse will be described.

  FIG. 9 shows a flowchart of a method for manufacturing a semiconductor device according to the present embodiment. First, in step S1 shown in FIG. 9, a wafer test is performed on a wafer-like semiconductor device manufactured through a predetermined process. In step S2, a portion requiring repair is relieved with a laser fuse (LT fuse) based on the result of the wafer test performed in step S1. Furthermore, in the semiconductor device according to the present embodiment, since a plurality of different fuses are stacked, a portion that cannot be repaired only by the LT fuse is repaired by using the wiring fuse 100 or the polyfuse 200 of the electrical fuse. Can do.

  In the flowchart shown in FIG. 9, if all repair locations can be repaired by repairing the LT fuse in step S2, the product is determined to be non-defective, and if the repair location remains, the remaining repair location is repaired using an electric fuse in step S3. To do. In a conventional semiconductor device in which only one type of LT fuse or only one electric fuse is mounted, the number of fuses that can be mounted in a fixed fuse area is limited due to the single-layer fuse configuration. For this reason, in a semiconductor device in which the capacity and miniaturization of an on-board memory is advanced, it is conceivable that the relief rate is lowered in the conventional fuse configuration. However, since the semiconductor device according to the present embodiment has two or more types of fuses stacked in different layers, even if all the LT fuses are used, the portion that needs to be relieved The relief rate can be improved by repairing with an electric fuse of a different layer. In the semiconductor device according to the present embodiment, fuses can be stacked on different layers, and the number of fuses can be increased without increasing the fuse area.

  If the remaining repaired part can be repaired with the electric fuse in step S3, the semiconductor device becomes a non-defective product, but the semiconductor device that cannot be repaired in this step becomes a defective product. The non-defective semiconductor device is further assembled in step S4, and a final test is performed in step S5. Only semiconductor devices that pass the final test in step S5 are modularized in step S6 and shipped in step S7.

  As described above, since the semiconductor device manufacturing method according to the present embodiment is processed according to the flowchart shown in FIG. 9, the repair location found in the wafer test can be relieved more than the conventional method. . In this embodiment, since the fuses are relieved before assembly, the types of fuses used may be electrical fuses and LT fuses in this order.

  FIG. 10 shows a flowchart of another semiconductor device manufacturing method according to the present embodiment. In the flowchart shown in FIG. 10 as well, a wafer test is performed on the wafer-like semiconductor device in step S1, and based on the result of the wafer test performed in step S1, a portion that needs repair is identified with an LT fuse. Bail out. Also, in the flowchart shown in FIG. 10, if all repair locations can be repaired by repairing the LT fuse in step S2, the product is determined to be non-defective, and if the repair location remains, the remaining repair location using the electric fuse in step S31. To remedy.

  In the flowchart shown in FIG. 10, the repair location found in the final test in step S5 through the assembly in step S4 is further repaired with an electric fuse. Specifically, the repair is performed using a fuse other than the electric fuse used in step S31. Therefore, in step S32, unused electric fuses other than the electric fuse used in step S31 are confirmed by a predetermined circuit. In addition, the predetermined circuit can confirm an unused electric fuse by performing a continuity check of the electric fuse.

  If there is no unused electrical fuse in step S31, the semiconductor device is defective. If there is an unused electrical fuse, relief after packaging is performed using the unused electrical fuse in step S33. If the relief in step S33 is successful, the product becomes a good product, but if it fails, the product becomes a defective product.

  As described above, in another method for manufacturing a semiconductor device according to the present embodiment, since the process shown in the flowchart of FIG. 10 is performed, repair locations found in the final test can be repaired, and the repair rate is higher than that of the conventional method. Get higher. Furthermore, in another method for manufacturing a semiconductor device according to the present embodiment, LT fuse relief is performed in step S2, assembly is then performed in step S4, and post-package relief is performed using an unused electric fuse in step S33. Therefore, the LT fuse and the electric fuse can be used efficiently. Since the LT fuse cannot be used after assembly, when the LT fuse is used after the electrical fuse is used, there is no electrical fuse that can be used after the assembly. Even if the LT fuse remains, it is defective after the assembly. However, in another semiconductor device manufacturing method according to the present embodiment, since an LT fuse is used first after a wafer test before assembly, there is a possibility that a usable electric fuse may remain after assembly. This increases the possibility of repairing the semiconductor device with an electrical fuse after assembly.

  Furthermore, FIG. 11 shows a flowchart of another semiconductor device manufacturing method according to the present embodiment. The flowchart shown in FIG. 11 differs from the flowchart shown in FIG. 10 in that the electrical fuse repair performed after repairing the LT fuse in step S2 performs repair using only a predetermined electrical fuse (first electrical fuse) (step S34). . Here, the first electric fuse may be, for example, the wiring fuse 100 shown in FIG. 1 or the upper two layers 104 and 105 of the wiring fuse.

  In the flowchart shown in FIG. 11, the second electrical fuse previously distinguished from the first electrical fuse used in step S34 is used for the repair location found in the final test in step S5 through the assembly in step S4. Relief is performed (step S35). Here, the second electric fuse may be, for example, the polyfuse 200 shown in FIG. 1 or the lower three layers 101 to 103 of the wiring fuse. In other words, in the flowchart shown in FIG. 11, the first electrical fuse used before assembly and the second electrical fuse used after assembly are physically distinguished from each other as in step S32 of the flowchart shown in FIG. The process of confirming the electric fuse in use is not necessary.

  As described above, in the manufacturing method of another semiconductor device according to the present embodiment, the process shown in the flowchart of FIG. 11 is performed, so that a process for checking an unused electric fuse as in step S32 is not necessary. Can be simplified.

  Further, in another method for manufacturing a semiconductor device according to the present embodiment, a security ID (identification information) of BIST (Built In Self Test) is stamped using an electric fuse. That is, the LT fuse has a different role for each memory and the electric fuse has a different role for BIST security ID marking. This can be realized by providing two or more types of fuses without increasing the fuse area by stacking different layers.

  Also in the flowchart shown in FIG. 12, in step S1, a wafer test is performed on the wafer-like semiconductor device, and in step S2, a portion requiring repair is LT fuse based on the result of the wafer test performed in step S1. Bail out. Next, in step 10, a BIST security ID is stamped using an electric fuse. Thereafter, similarly to the flowchart shown in FIG. 9, the processing from step S4 to step S7 is performed.

  As described above, in another method of manufacturing a semiconductor device according to the present embodiment, a different role can be given to each of a plurality of different types of fuses, and a BIST security ID (identification information) is assigned to the semiconductor device. it can.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is a top view of opening of the semiconductor device concerning Embodiment 1 of the present invention. It is sectional drawing of the wiring fuse vicinity which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the wiring fuse which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the wiring fuse which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the wiring fuse which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the wiring fuse which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the wiring fuse which concerns on Embodiment 2 of this invention. It is a flowchart of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. It is a flowchart of the manufacturing method of another semiconductor device which concerns on Embodiment 3 of this invention. It is a flowchart of the manufacturing method of another semiconductor device which concerns on Embodiment 3 of this invention. It is a flowchart of the manufacturing method of another semiconductor device which concerns on Embodiment 3 of this invention.

Explanation of symbols

  2 Si substrate, 4 element isolation region, 6 gate insulating film, 8 gate electrode, 10 sidewall, 12 impurity diffusion layer, 14, 36f, 54, 60 PTEOS film, 16 contact plug, 24, 38, 50a, 58 barrier Metal, 26, 40, 50b Cu, 36e SiOF film, 42 Cu reflector layer, 50 laser fuse, 52 SiCN film, 56 Al pad, 62 SiN film, 64 polyimide, 66, 68 opening, 100-105 wiring fuse, 110 contamination Prevention layer, 120 via wiring, 200-204 polyfuse.

Claims (9)

A first fuse that is cut by applying a predetermined voltage value or passing a predetermined current value or more;
A second fuse cut by irradiating with laser light;
A reflector layer for reflecting the laser light,
A semiconductor device, wherein the reflector layer is laminated on the first fuse via an insulating layer, and the second fuse is laminated on the reflector layer via an insulating layer. The semiconductor device according to claim 1,
The first fuse includes a polyfuse formed of polysilicon and a wiring fuse formed of a wiring material,
A semiconductor device, wherein the wiring fuse is laminated on the polyfuse via an insulating layer. The semiconductor device according to claim 2,
The wiring fuse is formed in a plurality of layers via an insulating layer, and is provided at a position where the adjacent wiring fuses do not overlap in plan view. The semiconductor device according to claim 2 or 3, wherein
A contamination prevention layer formed on an upper layer and a lower layer of the wiring fuse via an insulating layer;
A semiconductor device, further comprising: a pair of via wirings formed on an insulating layer on a side surface of the wiring fuse and connected to the contamination prevention layer to surround the wiring fuse. The semiconductor device according to claim 4,
A distance between the contamination prevention layer and the via wiring and the wiring fuse is secured to 400 nm or more. A method of manufacturing a semiconductor device, wherein the semiconductor device according to claim 1 is repaired using the first fuse and the second fuse.
A first repair step for repairing the first repair location found based on the wafer test using the second fuse;
A second repair step of repairing the first repair location that has not been repaired in the first repair step using the first fuse;
A method for manufacturing a semiconductor device, comprising: an assembling step for assembling the semiconductor device after the second relief step. A method of manufacturing a semiconductor device according to claim 6,
Performing a test on the semiconductor device after the assembling step, and confirming an unused first fuse in the second repair step for a second repair location found in the test;
A method of manufacturing a semiconductor device, comprising: a third repair step of performing repair using the first fuse that has been confirmed to be unused in the confirmation step. A method of manufacturing a semiconductor device according to claim 6,
A test is performed on the semiconductor device after the assembling step, and the second repair location found in the test is distinguished from the first fuse used in the second relief step in advance. A method of manufacturing a semiconductor device, comprising: a third relief step for carrying out relief using a fuse.   6. A method of manufacturing a semiconductor device according to claim 1, wherein identification information is added to the semiconductor device according to any one of claims 1 to 5 using the first fuse.

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