JPH10150164A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of simplifying the manufacturing steps and having a fuse capable of making an aperture part as well as its manufacturing method. SOLUTION: In the manufacturing method, a storage node electrode (lower part electrode of capacitor) 13 of a capacitor such as a component in a storage cell of a DRAM and an insulating film 14 as a dielectric of the capacitor on the electrode 13 are formed and then a metallic film e.g. a titanium nitride film, etc., made of a high corrosion resistant metal is formed on a semiconductor substrate 1. Furthermore, making use of the photolithographic technology and the selective etching technology, a plate electrode (upper electrode of capacitor) 15a of the capacitor and a fuse 15b are formed by patterning the metallic films. Besides, an aperture part 22 is formed on a part of the fuse 15b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device capable of forming a high-performance fuse using a simple manufacturing process and a method of manufacturing the same. .

[0002]

2. Description of the Related Art The present inventor has studied a technique for manufacturing a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory) having a fuse.
The following is a technique studied by the present inventors, and the outline is as follows.

That is, a DRAM having a fuse
In a semiconductor integrated circuit device having a fuse, the same aluminum layer as an aluminum layer used as a wiring layer is used as a fuse, or the same polycrystalline silicon film as a polycrystalline silicon film used as a gate electrode is used. Is used.

In a semiconductor integrated circuit device having a DRAM having a fuse, when performing a probe test, the passivation film in the region of the fuse is removed, and the fuse is cut in accordance with the result of the probe test. ing.

As a document describing a semiconductor integrated circuit device having a DRAM, there is, for example, a document described in Japanese Patent Application Laid-Open No. 3-214669.

[0006]

However, if the same aluminum layer as the aluminum layer used as the wiring layer is used as the above-mentioned fuse, the fuse made of the aluminum layer has a problem in corrosion resistance. However, there is a problem that the fuse portion cannot be opened.

Further, when the same polycrystalline silicon film as the polycrystalline silicon film used as the gate electrode is used as the above-mentioned fuse, the polycrystalline silicon film is used as the gate electrode in order to improve the performance of the device. When a gate electrode having a laminated structure consisting of a film and a metal film such as tungsten (W) is applied thereon, in a fuse made of the same material, the material of the metal film such as tungsten has a problem in corrosion resistance. However, there is a problem that the fuse portion cannot be opened.

Further, the D having the above-mentioned fuse is provided.
In a semiconductor integrated circuit device having a RAM, when a probe test is performed, the passivation film in the region of the fuse is removed, so that after the probe test, a passivation film is formed again and there is a problem in corrosion resistance. Since it is necessary to cover a fuse made of a material with a passivation film, there are problems that the manufacturing process becomes complicated and the number of manufacturing processes increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device having a fuse capable of simplifying a manufacturing process and opening a hole, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1). The semiconductor integrated circuit device of the present invention has a fuse made of a highly corrosion-resistant metal film such as a titanium nitride film made of the same material as an upper electrode of a capacitor such as a component in a DRAM memory cell. It is formed by the same process as the upper electrode.

(2). The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of: providing a capacitor such as a component in a memory cell of a DRAM in a selective region of an insulating film on a substrate such as a semiconductor substrate on which a plurality of semiconductor elements are formed; After forming a lower electrode and an insulating film as a dielectric of the capacitor on the lower electrode, a metal film such as a titanium nitride film made of a metal having high corrosion resistance is formed on the substrate, and a photolithography technique is selected. The method includes a step of forming an upper electrode and a fuse of the capacitor by patterning a metal film thereof by using an etching technique.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIGS. 1 to 8 are cross-sectional views showing manufacturing steps of a semiconductor integrated circuit device according to an embodiment of the present invention.

The semiconductor integrated circuit device according to the present embodiment has a DRA having a fuse and a capacitor.
1 to 8, the cross-sectional views illustrated on the left side are cross-sectional views illustrating regions where fuses are arranged, and the cross-sectional views illustrated on the right side include capacitors. FIG. 2 is a cross-sectional view showing a region where a DRAM is arranged.

A semiconductor integrated circuit device having a DRAM having a fuse and a capacitor according to the present embodiment and a method of manufacturing the same will be described with reference to FIGS.

First, a selective region on the surface of a p-type semiconductor substrate (substrate) 1 made of, for example, single crystal silicon is thermally oxidized to form a field insulating film made of a silicon oxide film having a LOCOS (Local Oxidation of Silicon) structure. After the formation of the MOSFET 2, a MOSFET is formed in the element formation region of the semiconductor substrate 1 (FIG. 1). In a region where a fuse is arranged in the cross-sectional view shown on the left side, a mode in which it is not necessary to form the field insulating film 2 on the surface of the semiconductor substrate 1 can be adopted.

In this case, the manufacturing process of the MOSFET is as follows. That is, after a gate insulating film 3 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1, the surface of the gate insulating film 3 is made of a conductive material containing impurities such as phosphorus as a gate electrode 4. After depositing a crystalline silicon film using a CVD (Chemical Vapor Deposition) method, an insulating film 5 such as a silicon oxide film is formed thereon using a CVD method.

Next, the patterns of the insulating film 5, the gate electrode (word line in DRAM) 4 and the gate insulating film 3 in the gate region are formed by using the photolithography technique and the selective etching technique. Then, after forming a silicon oxide film on the semiconductor substrate 1 by using the CVD method,
Using a photolithography technique and a selective etching technique, a sidewall spacer (sidewall insulating film) 6 is formed on the sidewall of the gate region. Thereafter, an n-type impurity such as phosphorus is ion-implanted and diffused into the surface of the semiconductor substrate 1 to form an n-type semiconductor region 7 serving as a source and a drain of the N-channel MOSFET.

Next, for example, a silicon oxide film is deposited on the semiconductor substrate 1 by using the CVD method, and if necessary, its surface is flattened by using the CMP (Chemical Mechanical Polishing) method. To form an insulating film 8 having a flat surface.

After that, a connection hole (contact hole) is formed in the insulating film 8 by using a photolithography technique and a selective etching technique. Embed,
The plug 9 is formed. After that, for example, an aluminum layer is deposited on the semiconductor substrate 1 by using a sputtering method, and then, using a photolithography technique and a selective etching technique, for example, a patterned first wiring layer made of an aluminum layer (Bit line in DRAM) 1
0 (FIG. 2).

In this case, according to the design specifications, the plug 9 and the wiring layer 10 are formed by using a process of manufacturing the wiring layer 10 using, for example, an aluminum layer as the wiring layer 10. can do.

After that, for example, a silicon oxide film is deposited on the semiconductor substrate 1 by using the CVD method, and the surface thereof is flattened by using the CMP method, if necessary, to form an insulating film having a flat surface. 11 is formed. In this case, the insulating film 1
For example, in addition to a silicon oxide film, PSG (Ph
ospho Silicate Glass film, BPSG (Boro PhosphoSi)
licate glass) film or SOG (Spin On Glass) film.

Thereafter, a connection hole is formed in the insulating film 11 by using a photolithography technique and a selective etching technique, and then the connection hole is filled with, for example, conductive polycrystalline silicon by using a selective CVD method. The plug 12 is formed. After that, for example, a conductive polycrystalline silicon layer is deposited on the semiconductor substrate 1 by using a CVD method, and then, for example, the conductive polycrystalline silicon layer is formed by using a photolithography technique and a selective etching technique. Patterned storage node electrode (lower electrode of capacitor) 1
3 (FIG. 3).

Next, for example, a silicon nitride film is deposited on the semiconductor substrate 1 by using the CVD method, and then, on the surface of the storage node electrode 13 of the capacitor using photolithography and selective etching. An insulating film serving as a dielectric of the capacitor is formed. In this case, the insulating film 21 may be formed using an insulating film using a dielectric material such as PZT (lead zirconate titanate) or tantalum pentoxide (Ta ₂ O ₅ ) in addition to the silicon nitride film. it can.

After that, for example, a titanium nitride (TiN) film 15 which is a metal film having high corrosion resistance is deposited on the semiconductor substrate 1 by sputtering or CVD, and then photolithography and selective etching are used. Then, a plate electrode (upper electrode of the capacitor) 15a in which the titanium nitride film 15 is patterned and a fuse 15b in which the titanium nitride film 15 is patterned are simultaneously formed (FIG. 4).

In this case, the metal film having high corrosion resistance is a metal film having an excellent property of being hardly corroded by a reaction such as oxidation due to the influence of external air or moisture, and a titanium nitride film is particularly preferred as the metal film. Excellent, but titanium (T
Since i), tantalum (Ta), copper (Cu), gold (Au), and silver (Ag) are also metals having high corrosion resistance, an embodiment in which these metal films are applied can be adopted.

After that, for example, a silicon oxide film is deposited on the semiconductor substrate 1 by using the CVD method, and the surface thereof is flattened by using the CMP method, if necessary, to form an insulating film having a flat surface. 16 are formed. After that, the insulating film 16
After a connection hole (through hole) is formed using a photolithography technique and a selective etching technique, a tungsten (W) is formed in the connection hole using a selective CVD method.
Is embedded to form a plug (plug in the fuse 15b) 17 (FIG. 5).

After that, for example, an aluminum layer is deposited on the semiconductor substrate 1 by using a sputtering method, and then, by using a photolithography technique and a selective etching technique, for example, a patterned 2 layer made of an aluminum layer is formed.
The second wiring layer 1 is formed at the same time when the second wiring layer 18 is formed.
Then, a wiring layer 18 of a fuse made of the semiconductor device 8 is formed (FIG. 6).
In this case, the second wiring layer 18 is a metal layer such as aluminum or copper.

Next, after depositing, for example, a silicon oxide film on the semiconductor substrate 1 by using the CVD method, if necessary, the surface is flattened by using the CMP method, so that an insulating film having a flat surface is formed. A film 19 is formed. Then, fuse 15
An opening 20 is formed in the insulating film 16 and the insulating film 19 on the surface b using a photolithography technique and a selective etching technique (FIG. 7).

After that, for example, a silicon nitride film is deposited on the semiconductor substrate 1 by using the CVD method, and the surface is flattened by using the CMP method, if necessary, to form an insulating film having a flat surface. (Passivation film) 21 is formed. Then, a hole 2 is formed in the insulating film 21 on the fuse 15b.
2 are formed by using the photolithography technique and the selective etching technique, thereby completing the semiconductor integrated circuit device manufacturing process (FIG. 8).

According to the above-described semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, a metal film having high corrosion resistance, for example, a titanium nitride film 15 is formed on the semiconductor substrate 1 by sputtering or CVD. After the deposition, a plate electrode (upper electrode of a capacitor) 15a in which the titanium nitride film 15 is patterned and a fuse 15b in which the titanium nitride film 15 is patterned are simultaneously formed by using a photolithography technique and a selective etching technique. Therefore, when forming the fuse 15b, the same manufacturing process as that for forming the plate electrode 15a of the capacitor is used, so that the fuse 15b can be formed without increasing the number of manufacturing processes. it can.

According to the semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, the fuse 15b is made of a highly corrosion-resistant metal film, for example, a titanium nitride film 1
Since the fuse 15b is made of a metal film having an excellent property of being hardly affected by a reaction such as oxidation due to the influence of the outside air or moisture due to the use of the fuse 5b, the reliability and the performance are high. Fuse 15b.

The use of the metal film having high corrosion resistance, for example, the titanium nitride film 15 as the material of the fuse 15b allows the opening 22 to be formed on the surface of the fuse 15b.

Accordingly, it is possible to perform a probe test or the like at the wafer processing stage, cut the fuse 15b connected to the defective circuit through the opening 22, and replace the fuse 15b with another refill circuit.

Further, a fuse 15b having an opening 22
The fuse 15b due to outside air, moisture, etc.
By not corroding, the manufacturing process of the insulating film (passivation film) which also serves to bury the opening 22 with the insulating film (passivation film) after the probe inspection becomes unnecessary, so that the manufacturing process can be simplified and Since the number of manufacturing steps can be reduced, manufacturing yield and manufacturing cost can be reduced.

(Embodiment 2) FIG. 9 is a plan view showing in perspective a fuse region in a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 10 is a cross-sectional view showing a cross section taken along line AA ′ in FIG.

As shown in FIGS. 9 and 10, the fuse 15b of the present embodiment has the same form as the fuse 15b of the above-described first embodiment.
Is provided around the guard ring 23.

Therefore, the fuse 15 of the present embodiment
The guard ring 23 is arranged around the b, so that even if moisture or contaminants contained in the outside air or the like enter through the opening 22, the guard ring 23 can block the guard ring 23. .

That is, the fuse 15b of the present embodiment
The guard ring 23 is disposed around the periphery of the multi-layer wiring structure, so that even if moisture or contaminants contained in the outside air or the like enter through the opening 22, the guard ring 23 can block the moisture. The insulating films 8, 11, 16, 19, such as interlayer insulating films, the wiring layers 10, 18, the semiconductor substrate 1, and semiconductor elements such as MOSFETs formed thereon are adversely affected by moisture, contaminants, and the like penetrating through the opening 22. Guard ring 23
Therefore, a highly reliable and high-performance semiconductor integrated circuit device can be obtained.

The manufacturing process of the fuse 15b in the semiconductor integrated circuit device according to the present embodiment is the same as that in the first embodiment, and the description is omitted. The manufacturing process of the guard ring 23 formed around the fuse 15b is formed using each manufacturing process in the first embodiment, and is as follows.

That is, the guard ring 23 around the fuse 15b in the semiconductor integrated circuit device according to the present embodiment is formed by the first wiring layer 10 and the second wiring layer 18.
And the plugs 9 and 17a formed thereunder are laminated, and their wiring layers 10 and 18 are stacked.
And the plugs 9 and 17a are MOSFETs on the semiconductor substrate 1.
Is formed, and a pattern is formed in this region by using each manufacturing process (each manufacturing process in the first embodiment described above) when forming a multilayer wiring layer thereon. Note that the plug 17a is the same as that of the first embodiment.
Is deeper than the plug 17 in the first embodiment, and is connected to the lower wiring layer 10. Therefore, the manufacturing process of the guard ring 23 around the fuse 15b in the semiconductor integrated circuit device according to the present embodiment does not require any special manufacturing process because each manufacturing process of the first embodiment is used. Therefore, it can be formed by a simple manufacturing process.

(Embodiment 3) The fuse of the embodiment 1 or 2 can be applied to a fuse area in a conventional semiconductor integrated circuit device, and can be applied to a DC (Direct Current).
The present invention can be applied to various kinds of rescue such as direct current) remedy, defect remedy, and trimming remedy.

Further, in the fuse of the present invention including the fuse 15b of the present embodiment, an insulating film (passivation film) for filling the opening 22 after performing DC relief or the like.
Since the number of manufacturing steps can be reduced, the manufacturing steps can be simplified.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, according to the present invention, a semiconductor substrate on which a semiconductor element is formed can be changed to an SOI (Siliconon Insulator) substrate,
And a semiconductor integrated circuit device in which various semiconductor elements such as bipolar transistors are combined, and a method of manufacturing the same.

Further, the present invention relates to a MOSFET, a CMOS,
Logic system including FET, BiCMOSFET, etc. or DRAM, SRAM (Static Random Ac
cessMemory), an MIM (Metal Insulator Metal) capacitor,
The present invention can be applied to a semiconductor integrated circuit device having various capacitors such as an S (Metal Insulator Semiconductor) capacitor and a method of manufacturing the same.

[0049]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, after depositing a highly corrosion-resistant metal film such as a titanium nitride film on a substrate such as a semiconductor substrate,
When a fuse is formed by using a photolithography technique and a selective etching technique to simultaneously form a plate electrode (upper electrode of a capacitor) in which the metal film is patterned and a fuse in which the metal film is patterned. In addition, since the same manufacturing process as that for forming the plate electrode of the capacitor is used, the fuse can be formed without increasing the number of manufacturing processes.

(2). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, since a highly corrosion-resistant metal film such as a titanium nitride film is used as a material of the fuse, oxidation or the like is affected by outside air or moisture. Since the fuse is made of a metal film having an excellent property of being less susceptible to a corrosive action due to a reaction, a highly reliable and high-performance fuse can be obtained.

Further, by using a metal film having high corrosion resistance, for example, a titanium nitride film as a material of the fuse, an opening can be formed on the surface of the fuse.

Therefore, it is possible to perform an operation such as performing a probe test at the wafer processing stage, cutting the fuse connected to the defective circuit through the opening, and replacing it with another replenishing circuit.

Further, even if the fuse has an opening, since the fuse does not corrode due to outside air or moisture, an insulating film (passivation film) which also serves to bury the opening with an insulating film (passivation film) after a probe test or the like. Since the manufacturing process of the film is unnecessary, the manufacturing process can be simplified and the number of manufacturing processes can be reduced, so that the manufacturing yield and the manufacturing cost can be reduced.

(3). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, since the guard ring is disposed around the fuse, moisture or contaminants contained in the outside air or the like enter through the opening. Can also be of a structure that can be blocked by a guard ring.

That is, around the fuse of the present invention,
By arranging the guard ring, even if moisture or contaminants contained in the outside air enter through the opening, it can be blocked by the guard ring, so that the insulating film such as an interlayer insulating film of a multilayer wiring structure and the like. Substrates such as wiring layers and semiconductor substrates and MOSFETs formed on them
Such a semiconductor element is prevented by the guard ring from being adversely affected by moisture, contaminants, and the like that have entered through the opening, so that a highly reliable and high-performance semiconductor integrated circuit device can be obtained.

The manufacturing process of the guard ring around the fuse in the semiconductor integrated circuit device according to the present invention uses a special manufacturing process by using each manufacturing process of the MOSFET, the multilayer wiring layer, etc. of the semiconductor integrated circuit device. Since a process is not required, it can be formed by a simple manufacturing process.

(4). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, an opening can be formed in the surface of the fuse because a fuse made of a metal film having high corrosion resistance can be manufactured, and thus the fuse can be DC-relieved, defect-relieved or trimmed It can be applied to various remedies such as remedies.

Further, in the fuse of the present invention, the steps of manufacturing an insulating film (passivation film) for filling an opening after DC relief and the like can be reduced, so that the manufacturing steps can be simplified.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 9 is a plan view transparently showing a region of a fuse in a semiconductor integrated circuit device according to another embodiment of the present invention.

10 is a cross-sectional view showing a cross section taken along line AA 'in FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 insulating film 6 sidewall spacer (sidewall insulating film) 7 semiconductor region 8 insulating film 9 plug 10 wiring layer 11 insulating film 12 plug 13 storage node electrode (for capacitor Lower electrode 14 insulating film (insulating film serving as dielectric of capacitor) 15 titanium nitride film (metal film having high corrosion resistance) 15a plate electrode (upper electrode of capacitor) 15b fuse 16 insulating film 17 plug 17a plug 18 wiring layer 19 insulating Film 20 Opening 21 Insulating film (passivation film) 22 Opening 23 Guard ring

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8244 H01L 27/10 671C 27/11

Claims (8)

[Claims] 1. A semiconductor integrated circuit device having a fuse made of the same material as an upper electrode of a capacitor made of a metal having high corrosion resistance, such as titanium nitride, and formed in the same step as the upper electrode. . 2. The semiconductor integrated circuit device according to claim 1, wherein a part of the surface of the fuse is exposed by an opening formed in an insulating film. Semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein a guard ring is formed around the fuse. 4. The semiconductor integrated circuit device according to claim 1, wherein said capacitor is a DRA.
A semiconductor integrated circuit device, which is a component of a memory cell of M or SRAM. 5. A step of forming a lower electrode of a capacitor in a selective region of an insulating film on a substrate on which a plurality of semiconductor elements are formed, and forming an insulating film as a dielectric of the capacitor on the lower electrode. Forming a metal film made of a metal having high corrosion resistance on the substrate, and forming an upper electrode and a fuse of the capacitor by patterning the metal film using a photolithography technique and a selective etching technique. And a method for manufacturing a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein after forming an upper electrode of the capacitor and the fuse, an insulating film is formed on the substrate including the upper electrode and the fuse. A method of manufacturing a semiconductor integrated circuit device, comprising a step of forming an opening in an insulating film on a part of the surface of the fuse by using a photolithography technique and the selective etching technique. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein a peripheral portion of the fuse is formed by using a process of manufacturing a plug and a wiring layer embedded in a connection hole in a multilayer wiring structure. A method of manufacturing a semiconductor integrated circuit device, further comprising a step of forming a guard ring. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said fuse and said upper electrode of said capacitor are made of a metal having high corrosion resistance, such as titanium nitride. The method for manufacturing a semiconductor integrated circuit device, wherein the material is a material, and the capacitor is a component of a memory cell of a DRAM or an SRAM.