JP2007201485A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten manufacturing time by shortening the formation time of the opening portion of the upper portion of a fuse portion without inviting decrease in reliability by the cutting of the fuse portion and decrease in manufacturing yield in a semiconductor integrated circuit device in which multilayer wiring is provided corresponding to miniaturization and high integration. <P>SOLUTION: The invention comprises an insulating film 41 formed on a semiconductor substrate 11 and a fuse portion 13 comprising a wiring layer formed on the insulating film 41. The wiring layer of the fuse portion 13 has a conducting metal layer 13A comprising at least copper. In addition, the wiring layer of the fuse portion 13 further comprises a barrier metal layer 40 formed on the insulating film 41. The conducting metal layer 13A is formed on the barrier metal layer 40. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having a fuse portion used for a redundant relief circuit, a function adjustment circuit, or the like of a large-capacity memory, and a manufacturing method thereof.

  In recent years, microfabrication technology has advanced in semiconductor integrated circuits, and the capacity of storage devices of semiconductor integrated circuits represented by dynamic random access memory (DRAM), static random access memory (SRAM), etc. is of the G bit class. Has been developed. In order to achieve high integration, multilayer wiring technology has been used for wiring connecting circuit elements. As the memory capacity of semiconductor integrated circuits has increased due to advances in microfabrication technology, even fine dust in the manufacturing process can cause defective bits that can degrade device functionality or cause malfunctions. As such, the semiconductor integrated circuit becomes defective as a whole, and a reduction in manufacturing yield becomes a problem. One solution to this is a redundant relief technique. This is because spare memory bits are manufactured in advance at the same time as the chip manufacturing process in excess of the memory capacity of the product, and even if there is a defect in a part of the chip and a defective memory bit is generated, it is switched to the spare memory bit. This is a defective bit remedy technique in which all the memory capacity of the product is made into good bits. One method for switching between a defective memory bit and a spare memory bit is a redundant relief technique by laser processing. This is a technology that realizes the switching by irradiating a laser beam to blow / cut the fuse portion of the redundant relief switching circuit on the chip.

  Conventionally, one of the fuse materials to be processed by laser is mainly made of polysilicon and silicide of the same material as the gate electrode and bit signal line of the MOS transistor and polycide obtained by stacking them in multiple layers because of the simplicity of the manufacturing process. Fuse material has been used.

  The fuse portion used in the conventional redundant relief switching circuit will be described below. FIG. 22 is a main part sectional view of a conventional semiconductor integrated circuit device. In FIG. 22, 1 is a semiconductor substrate, 2 is an interlayer insulating film, 3 is a fuse portion made of, for example, a polycide layer, 4 is an inorganic insulating protective film, 5 is an organic insulating protective film, 6 is an opening, and 7 is a pad electrode. . The pad electrode 7 is an electrode for connecting with a package assembly lead, and the organic insulating protective film 5 and the inorganic insulating protective film 4 on the pad electrode 7 are removed and opened by etching using a normal method. At the same time, the organic insulating protective film 5 and the inorganic insulating protective film 4 above the fuse part 3 are removed by selective etching so that the fuse part 3 can be easily cut by laser light irradiation, thereby forming an opening 6. 3 is also thinned.

  However, semiconductor integrated circuits have become multi-layered in response to high integration and miniaturization, so that the conventional configuration has a new technical problem. In other words, since multilayer wiring is used, there are many wiring layers above the fuse part made of polycide layer, etc., and as a result, the thickness of the interlayer insulating film above the fuse part has increased. . Therefore, when forming the opening of the interlayer insulating film for making electrical contact between the multilayer wiring layers above the fuse, a process of removing the opening of the interlayer insulating film above the fuse part at the same time is applied as necessary. Various efforts have been made to adopt a process of thinning the interlayer insulating film above the fuse. Otherwise, the thickness of the protective film and interlayer insulating film on the upper part of the fuse part will increase, and the fuse material gasified by laser irradiation when the fuse part is melted will break the protective film and insulating film on the upper part of the chip This is because a large explosive force was required to scatter to the outside. In other words, it was necessary to increase the instantaneous explosion pressure at that time by increasing the irradiation energy of the laser to the fuse portion to melt and gasify the fuse portion in a shorter time.

  However, the pressure also exerted simultaneously on the direction of the semiconductor substrate below the blown fuse part at the time of explosion and the peripheral direction of the cut fuse part. At the same time, excessive thermal energy for cutting the fuse portion is accompanied by excessive heating of the semiconductor substrate portion below the fuse portion. For this reason, excessive laser energy irradiation causes damage such as cracking and fusing to the semiconductor substrate portion below the fuse portion. Even if this damage is small with respect to the initial fluctuation in electrical characteristics of the semiconductor integrated circuit, there is a possibility of affecting the reliability. In addition, if a large explosion occurs at the same time in the semiconductor substrate portion, the adjacent fuse portion that does not need to be cut will also be blown up and cut off, making it impossible to operate the desired redundancy relief circuit, and memory bit relief is possible. It became impossible to cause a decrease in manufacturing yield.

  Therefore, as countermeasures, the insulating film and interlayer film above the fuse portion have been removed by selective etching and the remaining film is thinned. In recent years, some multilayer wirings for highly integrating semiconductor integrated circuits have more than three layers, and the thickness of the interlayer insulating film above the fuse portion is also increasing. For this reason, the thickness of the interlayer insulating film to be removed by etching is about 1 μm to several μm or more, and a long etching removal time is required. This is a technical problem that the throughput of the etching apparatus is reduced and the manufacturing time is long. In addition, it is difficult to keep in-plane variations and fluctuations in the etching rate small during etching removal with a wafer having a large diameter of 8 inches or more. There was also a technical problem that it was difficult to uniformly control the surface.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device capable of preventing a decrease in reliability and a decrease in manufacturing yield due to cutting of a fuse portion in a semiconductor integrated circuit device having a multi-layer wiring corresponding to fine and high integration, and its manufacture Is to provide a method.

  Furthermore, another object of the present invention is to provide a semiconductor integrated circuit device and a method for manufacturing the semiconductor integrated circuit device that can shorten the manufacturing time by shortening the formation time of the opening above the fuse portion.

  2. The semiconductor integrated circuit device according to claim 1, further comprising: a fuse portion including an insulating film formed on the semiconductor substrate and a wiring layer formed on the insulating film. The wiring layer has a conductive metal layer made of at least copper.

  The semiconductor integrated circuit device according to claim 2 is the semiconductor integrated circuit device according to claim 1, wherein the wiring layer of the fuse portion further includes a barrier metal layer formed on the insulating film, and the conductive metal layer includes: It is formed on the barrier metal layer.

  A semiconductor integrated circuit device according to claim 3 is the semiconductor integrated circuit device according to claim 2, wherein the barrier metal layer is formed of a single layer film or a multilayer film.

  The semiconductor integrated circuit device according to claim 4 is the semiconductor integrated circuit device according to claim 2, wherein the barrier metal layer is a single layer film made of titanium nitride, titanium, or tungsten nitride, or a multilayer film thereof. It is characterized by that.

  The semiconductor integrated circuit device according to claim 5 is the semiconductor integrated circuit device according to any one of claims 2 to 4, wherein the thickness of the barrier metal layer is 150 nm or less.

  The semiconductor integrated circuit device according to claim 6 is the semiconductor integrated circuit device according to any one of claims 1 to 5, further comprising an inorganic insulating protective film formed on the wiring layer and the insulating film. It is characterized by being.

  The semiconductor integrated circuit device according to claim 7 is the semiconductor integrated circuit device according to claim 6, wherein the inorganic insulating protective film is a single layer of any one of a silicon oxide film, a silicon oxynitride film, and a plasma silicon nitride film. It is a film or a multilayer film combining these.

  The semiconductor integrated circuit device according to claim 8 is the semiconductor integrated circuit device according to claim 6 or 7, wherein the inorganic insulating protective film on the fuse portion is not thinned or remains by etching.

  The semiconductor integrated circuit device according to claim 9 is the semiconductor integrated circuit device according to any one of claims 6 to 8, wherein the inorganic insulating protective film on the fuse portion has a thickness of 0.1 μm to 0 μm. .8 μm.

  The semiconductor integrated circuit device according to claim 10 is the semiconductor integrated circuit device according to any one of claims 6 to 9, further comprising an organic insulating protective film formed on the inorganic insulating protective film. It is characterized by being.

  A semiconductor integrated circuit according to an eleventh aspect is the semiconductor integrated circuit device according to the tenth aspect, wherein an opening is formed in the organic insulating protective film on the fuse portion.

  A semiconductor integrated circuit device according to claim 12 is the semiconductor integrated circuit device according to claim 10 or 11, wherein the organic insulating protective film is polyimide.

  The semiconductor integrated circuit device according to claim 13 is the semiconductor integrated circuit device according to any one of claims 1 to 12, wherein the fuse portion is formed of a plurality of wiring layers formed on the insulating film. It is formed by the uppermost wiring layer.

  The semiconductor integrated circuit device according to claim 14 is the semiconductor integrated circuit device according to any one of claims 1 to 13, wherein the upper limit value of the width of the fuse portion is 1.0 μm and the lower limit value is fine. It is a processing limit.

  The semiconductor integrated circuit device according to claim 15 is the semiconductor integrated circuit device according to any one of claims 1 to 14, wherein the wiring layer of the fuse portion is provided for holes and wirings provided in the insulating film. It has a dual damascene wiring structure in which a conductive metal layer is formed in the groove.

  The semiconductor integrated circuit device according to claim 16 is the semiconductor integrated circuit device according to claim 15, wherein the conductive metal layer is formed on a barrier metal layer formed on an inner surface of the hole and the groove for wiring. It is characterized by that.

  A semiconductor integrated circuit device according to a seventeenth aspect is the semiconductor integrated circuit device according to the fifteenth or sixteenth aspect, wherein the holes are provided in communication with the bottom surfaces on both sides of the wiring groove.

  A semiconductor integrated circuit device according to claim 18, wherein the semiconductor integrated circuit device according to any one of claims 15 to 17 is a lower insulating film formed under the insulating film and a lower insulating film. The wiring layer further includes a lower wiring layer embedded in a wiring groove, and the holes reach the lower wiring layer.

  The semiconductor integrated circuit device according to claim 19 is the semiconductor integrated circuit device according to any one of claims 1 to 18, wherein the fuse portion is surrounded by a guard band made of a conductive layer. And

  The semiconductor integrated circuit device according to claim 20 is the semiconductor integrated circuit device according to claim 19, wherein the conductive layer of the guard band uses a wiring layer from the uppermost layer to the lowermost layer and a plug metal layer for contact between the wirings. It is characterized by that.

  The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein in the method of manufacturing a semiconductor integrated circuit device having a fuse portion, a step (a) of forming an insulating film on the semiconductor substrate, and a wiring layer on the insulating film And a step (b) of forming a fuse portion, wherein the wiring layer of the fuse portion has at least a conductive metal layer made of copper.

  The method for manufacturing a semiconductor integrated circuit device according to claim 22 is the method for manufacturing a semiconductor integrated circuit device according to claim 21, wherein the step (b) includes a step (b1) of forming a barrier metal layer on the insulating film. And (b2) forming a conductive metal layer on the barrier metal layer.

  The method of manufacturing a semiconductor integrated circuit device according to claim 23 is the method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the step (b) is a step (b1) of forming a hole and a trench for wiring in the insulating film. ), A step (b2) of forming a barrier metal film on the inner surface of the hole and the wiring groove in the insulating film, and a step (b3) of embedding the conductive metal layer in the hole and wiring groove after the step (b2). And after the step (b3), a step (b4) of forming a fuse portion by planarizing the conductive metal layer using at least one of a chemical mechanical polishing technique and an etchback technique It is characterized by having.

  25. The method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the semiconductor integrated circuit device according to any one of claims 21 to 23 is formed on the wiring layer and the insulating film after the step (b). And (c) forming an inorganic insulating protective film, and (d) forming at least a thin film by etching the inorganic insulating protective film on the fuse portion.

  As described above, according to the present invention, the fuse portion including the wiring layer formed on the insulating film is provided, and the wiring layer of the fuse portion includes at least the conductive metal layer made of copper. Thus, the fuse portion can be formed. Thus, it is not necessary to etch the interlayer insulating film to form the opening above the fuse portion as in the prior art, and the time for forming the opening can be shortened and the entire manufacturing time can be shortened. Since only the inorganic insulating protective film is formed on the fuse part, the fuse part can be easily cut without increasing the laser beam irradiation energy. High reliability and high productivity can be realized without incurring a decrease in production yield.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a fragmentary sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, 11 is a semiconductor substrate, 12 is an interlayer insulating film, 13 is a fuse portion, and 14 is inorganic insulation protection. A film, 15 is an organic insulating protective film, 16 and 19 are openings of the organic insulating protective film 15, 17 is a pad electrode which is an external extraction electrode, and 18 is an opening of the inorganic insulating protective film.

  In the semiconductor integrated circuit device of the present embodiment, the fuse portion 13 and the pad electrode 17 are formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the organic insulating protective film is formed on the fuse portion 13. 15 openings 16 are provided, and the upper portion of the pad electrode 17 is opened by an opening 18 of the inorganic insulating protective film 14 and an opening 19 of the organic insulating protective film 15. Further, in order to reduce the thickness of the inorganic insulating protective film 14 on the fuse portion 13, the inorganic insulating protective film 14 exposed in the openings 16 and 19 of the organic insulating protective film is etched and thinned. Further, the opening 19 of the organic insulating protective film 15 provided on the pad electrode 17 is formed in a wider area than the opening 18 of the inorganic insulating protective film 14, and is formed in the pad electrode 17 and a region in the vicinity thereof. Yes.

  In this embodiment, in order to reduce the pad electrode 17 that is an external extraction electrode to the package assembly limit, to mount a large number of pad electrodes 17 at a high density, and to reduce the chip size, the opening 19 is an opening. Although the case where it is wider than 18 is shown, the present invention is not limited to this, and the case where the opening 19 and the opening 18 are the same width or the case where the opening 19 is narrower than the opening 18 may be used. Needless to say. And although the case where the inorganic insulation protective film 14 was thinned was shown, it is not limited to this, and when the inorganic insulation protective film 14 is thin with respect to fuse cutting from the beginning, it is not necessary to dare to thin the film. Needless to say.

  Further, in the present embodiment, the case where the two fuse portions 13 are formed under one opening portion 16 is illustrated, but the present invention is not limited to this, and under the one opening portion 16. Needless to say, one fuse portion 13 or three or more fuse portions 13 may be provided.

  FIG. 2 is a process cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 3 is a process flow diagram showing the same manufacturing method. This will be described below with reference to FIGS.

  Elements formed on the semiconductor substrate 11 are wired by a multilayer wiring layer (not shown). A fuse portion 13 and a pad electrode 17 are formed as the uppermost metal wiring layer on the interlayer insulating film 12 of the multilayer wiring, and a plasma silicon nitride film [a silicon nitride film formed by a plasma CVD (Chemical Vapor Deposition) method is formed thereon. ] About 1 μm is formed (steps S11 and S12 in FIG. 2A).

  Thereafter, a photoresist (not shown) is applied, an opening is formed in the resist above the pad electrode 17, and the inorganic insulating protective film 14 above the pad electrode 17 is removed by selective etching by a normal dry etching process. Then, the opening 18 is formed. Thereafter, the photoresist (not shown) is removed (FIG. 2B, steps S13 to S16 in FIG. 3).

  Next, a photosensitive organic insulating protective film 15 is applied to the entire surface to a thickness of about 10 μm, and patterned by a lithography process. An opening 16 is formed above the fuse portion 13 and an opening 19 is formed above the pad electrode 17. It forms (FIG.2 (c), step S17, S18 of FIG. 3). Usually, the organic insulating protective film 15 uses a photosensitive polyimide film or the like, but is not limited thereto, and the thickness of about 10 μm has been described, but it is needless to say that the organic insulating protective film 15 is not limited thereto.

  Thereafter, the inorganic insulating protective film 14 exposed in the opening 16 and the opening 19 is etched as necessary, so that the thickness of the inorganic insulating protective film 14 on the upper portion of the fuse portion 13 is 0.1 to 0.8 μm. Until it becomes (the configuration in FIG. 1, step S19 in FIG. 3). The etching amount is not limited to this, and the fuse tends to be surely cut as the thickness of the inorganic insulating protective film 14 above the fuse portion 13 is smaller. However, if the inorganic insulating protective film 14 is thin, the inorganic insulating protective film 14 is easily affected by a resin-sealing filler when the package is assembled later. From the viewpoint of moisture resistance, the inorganic insulating protective film 14 is thick. Better. In addition, when the space | interval of the adjacent fuse part 13 is wide, the inorganic insulation protective film 14 does not need to be thinned by an etching. This is because, when the fuse portion 13 is cut by laser light irradiation performed later, the larger the thickness of the inorganic insulating protective film 14 on the fuse portion 13 is, the larger the opening diameter is, and the interval between the fuse portions 13 is narrow. This is because, in some cases, the adjacent fuse portions 13 are affected, but when the interval between the fuse portions 13 is wide, the adjacent fuse portions 13 are not affected.

  As described above, according to the present embodiment, the fuse portion 13 is formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the organic insulating protective film 15 is formed as the opening 16 above the fuse portion 13. Since the opening only needs to be formed, for example, the interlayer insulating film 2 does not need to be etched to form the opening 6 above the fuse portion 3 as in the conventional case shown in FIG. The formation time of the part 16 can be shortened, and the entire manufacturing time can be shortened. Furthermore, the opening 16 at the top of the fuse portion 13 can be formed at the same time as the opening 19 at the top of the pad electrode 17, and no particular time is required for forming the opening 16 at the top of the fuse portion 13. Further, since only the inorganic insulating protective film 14 is formed on the upper portion of the fuse portion 13, the fuse portion 13 can be easily cut without increasing the laser irradiation energy. High reliability and high productivity can be realized without causing a decrease in productivity and a decrease in manufacturing yield. Moreover, since the fuse part 13 is covered with the inorganic insulating protective film 14, moisture resistance can be improved.

  Further, after the step of FIG. 2C, the inorganic insulating protective film 14 is etched to be thinned to have the structure of FIG. 1, so that the fuse part 13 can be easily cut by laser light irradiation.

  Further, in this embodiment, since the fuse portion 13 is formed by the uppermost wiring layer on the interlayer insulating film 12, a wafer having a large diameter of 8 inches or more is conventionally used to accurately connect the interlayer above the fuse portion. There is no problem that it is difficult to uniformly control the remaining amount of the insulating film within the wafer surface.

  Furthermore, in the present embodiment, the film thickness of the inorganic insulating protective film 14 on the fuse portion 13 can be uniformly controlled in the wafer plane with a wafer having a large diameter of 8 inches or more. In the case of the configuration of FIG. 2C, uniformity can be ensured within the wafer surface within about ± 10% (within about ± 0.1 μm) of the formed film thickness (about 1 μm) of the inorganic insulating protective film 14. In the case of the configuration of FIG. 1 in which the inorganic insulating protective film 14 is thinned to about 0.1 to 0.8 μm, the etching amount for thinning corresponds to about 0.9 to 0.2 μm. The etching variation within about ± 10% (within about ± 0.09 to 0.02 μm) can be controlled, and the square sum of the variation in the formed film thickness (about ± 10%) and the etching variation (about ± 10%) The wafer in-plane uniformity can be controlled within about ± 0.15 μm of the square root.

  In the above embodiment, the case where the inorganic insulating protective film 14 is formed to have a thickness of about 1 μm has been described. However, when the interlayer insulating film 12 has good flatness, there may be no problem in the moisture resistance and characteristics of the product. Needless to say, the inorganic insulating protective film 14 may be thinner than about 1 μm. In addition, in the case of the wiring method (damascene) in which the interlayer insulating film is flattened by CMP technology and embedded after forming the trench in the formation of multilayer wiring, the uppermost layer wiring is relatively flat and has good coverage, and inorganic insulation Even if the protective film 14 is made thinner than 1 μm, the uppermost wiring is relatively flat and the coverage of the inorganic insulating protective film 14 is improved, and there is no problem in the moisture resistance and characteristics of the product. Needless to say, it is not necessary to further reduce the film thickness by etching.

  On the contrary, when the flatness of the interlayer insulating film 12 is poor or when the moisture resistance performance is deteriorated in the product reliability test, the inorganic insulating protective film 14 is formed to be about 1 μm or more and divided into one or more times. To do. Needless to say, the inorganic insulating protective film 14 may be formed of a combination of a single layer or multiple layers of a silicon nitride film or a silicon oxide film.

  Moreover, although the film thickness of the inorganic insulating protective film 14 above the fuse portion 13 is reduced to about 0.1 to 0.8 μm, it is not limited to this. For example, there is a case where the inorganic insulating protective film 14 on the fuse portion 13 does not remain (film thickness 0), and even if the inorganic insulating protective film 14 does not remain, there is a case where no problem occurs in the moisture resistance and characteristics of the product. Needless to say.

  However, when the inorganic insulating protective film 14 does not exist on the fuse portion 13, since the moisture-resistant protective film disappears, the reliability generally tends to deteriorate. In addition, when the etching amount is set to be large for the purpose of completely removing the inorganic insulating protective film 14 on the fuse part 13, the etching of the upper part of the fuse part 13 proceeds in parallel at the same time. It becomes thinner, away from the design value, and eventually increases in resistance, leading to disconnection. Further, when the inorganic insulating protective film 14 does not exist on the fuse portion 13, the cutting of the fuse portion 13 by the laser becomes unstable. In general, the wiring layer constituting the fuse portion 13 is connected to a lower wiring layer through a contact hole, a thin barrier metal layer having a high melting point is formed on the wall surface of the contact hole, and an aluminum metal is formed thereon. And a main conductive metal layer made of an aluminum-copper alloy or the like, a thin barrier metal layer having a high melting point is laid on the lower layer of the fuse portion 13. Only the aluminum and aluminum-copper-based main conductive metal layers are heated in advance and melted and gasified immediately after laser irradiation, but the barrier metal layer with a high melting point is below. This is because the barrier metal layer may be left uncut as a result, resulting in defective fuse cutting. When the inorganic insulating protective film 14 remains on the upper and side portions of the fuse portion 13 as much as possible, the thin barrier metal layer laid on the lower portion of the fuse portion 13 is melted by receiving heat conduction from the heated aluminum. You can earn time. As a result, when the fuse part 13 is melted and gasified to break the inorganic insulating protective film and the fuse part 13 scatters, the barrier metal layer also scatters at the same time, so that the fuse can be cut reliably.

  Further, when the fuse portion 13 is configured by the uppermost wiring layer, after the inorganic insulating protective film 14 is formed, the corner portion of the fuse portion 13 is rounded on a semicircle so as to cover the fuse portion 13. Covered. When the inorganic insulating protective film 14 is thinned by dry etching, the thickness of the inorganic insulating protective film 14 remaining on the side wall of the fuse portion 13 is larger than the thickness of the inorganic insulating protective film 14 remaining on the upper portion of the fuse portion 13. (See the inorganic insulating protective film 39 in FIG. 19), it is possible to obtain a sufficient time from the laser irradiation of the fuse cutting to the scattering, and the inorganic insulation on the upper portion of the fuse portion 13 that is easy to fly upward. The thickness of the protective film 14 can be reduced. On the other hand, when the inorganic insulating protective film is formed on the fuse portion 13 with a thin film thickness, the thickness of the inorganic insulating protective film on the upper portion and the side portion of the fuse portion 13 may be made almost the same. Although it is possible, the cutting probability in this case is high, but it is not sufficiently stable. This is because, since the side film is thin, the fuse starts to fly quickly, so that the barrier metal layer is not sufficiently heated and melted, and the remaining part of the barrier metal layer may be generated.

[Second Embodiment]
FIG. 4 is a fragmentary sectional view of a semiconductor integrated circuit device according to the second embodiment of the present invention. In FIG. 4, 11 is a semiconductor substrate, 12 is an interlayer insulating film, 13 is a fuse portion, and 14 is inorganic insulation protection. Film, 15 is an organic insulating protective film, 16 and 19 are openings of the organic insulating protective film 15, 17 is a pad electrode which is an external extraction electrode, 18 is an opening of the inorganic insulating protective film 14, and 20 is on the fuse part 13. It is an inorganic insulating protective film.

  In the semiconductor integrated circuit device of the present embodiment, the fuse portion 13 and the pad electrode 17 are formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the organic insulating protective film is formed on the fuse portion 13. 15 openings 16 are provided, and the upper portion of the pad electrode 17 is opened by an opening 18 of the inorganic insulating protective film 14 and an opening 19 of the organic insulating protective film 15. Furthermore, in order to reduce the thickness of the inorganic insulating protective film 20 on the fuse portion 13, the inorganic insulating protective film 14 exposed in the opening 16 of the organic insulating protective film is etched and thinned. Further, the opening 19 of the organic insulating protective film 15 provided on the pad electrode 17 is formed in a wider area than the opening 18 of the inorganic insulating protective film 14, and is formed in the pad electrode 17 and a region in the vicinity thereof. Yes.

  In this embodiment, in order to reduce the pad electrode 17 that is an external extraction electrode to the package assembly limit, to mount a large number of pad electrodes 17 at a high density, and to reduce the chip size, the opening 19 is an opening. Although the case where it is wider than 18 is shown, the present invention is not limited to this, and the case where the opening 19 and the opening 18 are the same width or the case where the opening 19 is narrower than the opening 18 may be used. Needless to say. Although the case where the inorganic insulating protective film 14 is thinned to form the inorganic insulating protective film 20 above the fuse portion 13 is shown, the present invention is not limited to this, and the opening 18 of the pad electrode 17 can be easily formed. Needless to say, the inorganic insulating protective film 14 in the opening 19 may be thinned.

  Further, in the present embodiment, the case where the two fuse portions 13 are formed under one opening portion 16 is illustrated, but the present invention is not limited to this, and under the one opening portion 16. Needless to say, one fuse portion 13 or three or more fuse portions 13 may be provided.

  5 and 6 are process cross-sectional views showing a method of manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 7 is a process flow chart showing the same manufacturing method. This will be described below with reference to FIGS.

  Elements formed on the semiconductor substrate 11 are wired by a multilayer wiring layer (not shown). A fuse portion 13 and a pad electrode 17 are formed as the uppermost metal wiring layer on the interlayer insulating film 12 of the multilayer wiring, and a plasma silicon nitride film [a silicon nitride film formed by a plasma CVD (Chemical Vapor Deposition) method is formed thereon. ] About 1 μm is formed (FIG. 5A, steps S21 and S22 in FIG. 7).

  Thereafter, a photoresist 21 is applied, and an opening A is formed in the resist above the fuse portion 13 (FIG. 5B, steps S23 and S24 in FIG. 7). Subsequently, the inorganic insulating protective film 14 in the opening A above the fuse portion 13 is thinned by a normal dry etching process. The inorganic insulating protective film 14 below the opening A is thinned until the inorganic insulating protective film 20 above the fuse part 13 has a thickness of about 0.1 to 0.8 μm. Thereafter, the photoresist 21 is removed (FIG. 5C, steps S25 and S26 in FIG. 7).

  Next, a photoresist 22 is applied to form an opening B in the resist above the pad electrode 17 (FIG. 6A, steps S27 and S28 in FIG. 7). Subsequently, the inorganic insulating protective film 14 in the opening B above the pad electrode 17 is removed by selective etching to form an opening 18 by a normal dry etching process. At this time, the inorganic insulating protective film 20 above the fuse portion 13 whose thickness has already been reduced is not removed by etching. Thereafter, the photoresist 22 is removed (FIG. 6B, steps S29 and S30 in FIG. 7).

  Next, a photosensitive organic insulating protective film 15 is applied to the entire surface to a thickness of about 10 μm, and patterned by a lithography process. An opening 16 is formed above the fuse portion 13 and an opening 19 is formed above the pad electrode 17. It forms (step S31, S32 of FIG. 4, FIG. 7). Usually, the organic insulating protective film 15 uses a photosensitive polyimide film or the like, but is not limited thereto, and the thickness of about 10 μm has been described, but it is needless to say that the organic insulating protective film 15 is not limited thereto.

  Then, as a result of measuring the film thickness of the inorganic insulating protective film 20 on the fuse portion 13 with a normal measuring instrument, if necessary, the inorganic insulating protective films 20 and 23 exposed to the opening 16 and the opening 19 are used. The thickness of the inorganic insulating protective film 20 on the upper portion of the fuse portion 13 may be adjusted by etching. Needless to say, if it is not necessary to adjust the film thickness of the inorganic insulating protective film 20, it is not necessary to perform etching.

  As described above, according to the present embodiment, after forming the openings 16 and 19 by patterning the organic insulating protective film 15, the thickness of the inorganic insulating protective film 23 in the opening 19 is as long as it is not etched. The thickness of the inorganic insulating protective film 14 under the organic insulating protective film 15 is the same as that of the organic insulating protective film 15. This is advantageous for the moisture resistance of the semiconductor chip because the thickness of the inorganic insulating protective film is not reduced. Further, since the fuse portion 13 is formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the opening portion may be formed in the organic insulating protective film 15 as the opening portion 16 above the fuse portion 13, for example, It is not necessary to etch the interlayer insulating film 2 to form the opening 6 at the top of the fuse portion 3 as in the prior art shown in FIG. 22, and the time for forming the opening 16 at the top of the fuse portion 13 is shortened. The manufacturing time can be shortened.

  5C (step S25 in FIG. 7), the etching time for adjusting the film thickness of the inorganic insulating protective film 20 above the fuse portion 13 depends on the opening area ratio of the pad electrode 17. It is possible to set it independently without any problems. Further, the metal (aluminum or the like) of the pad electrode 17 is not exposed to the etching gas, the film thickness of the pad electrode 17 itself does not decrease, and no metal deposit (adhered material) is generated during the etching. Therefore, it is possible to perform etching with stable film thickness adjustment.

  Further, in order to perform the adjustment etching of the film thickness of the inorganic insulating protective film 20 first, the organic insulating protective film 15 (usually used photosensitive polyimide) to be performed later is patterned by a lithographic process, thermally cured, and the opening portion. When forming 16 and 19, even if the organic insulating protective film (polyimide film) remains very thin, the film thickness of the inorganic insulating protective film 20 is not affected. As a result, since the inorganic insulating protective film 20 having a reduced film thickness is formed on the fuse part 13, the fuse part 13 can be easily cut without increasing the laser irradiation energy. Cutting the fuse portion 13 can achieve high reliability and high productivity without reducing reliability and manufacturing yield. Moreover, since the fuse part 13 is covered with the inorganic insulating protective film 20, moisture resistance can be improved.

  Further, in this embodiment, since the fuse portion 13 is formed by the uppermost wiring layer on the interlayer insulating film 12, a wafer having a large diameter of 8 inches or more is conventionally used to accurately connect the interlayer above the fuse portion. There is no problem that it is difficult to uniformly control the remaining amount of the insulating film within the wafer surface.

  Further, in the present embodiment, the film thickness of the inorganic insulating protective film 20 on the fuse portion 13 can be uniformly controlled within the wafer surface with a wafer having a large diameter of 8 inches or more. In the case of the configuration of FIG. 4, uniformity can be ensured within the wafer surface within about ± 10% (within about ± 0.1 μm) of the formed film thickness (about 1 μm) of the inorganic insulating protective film 14. Further, the etching amount for thinning the inorganic insulating protective film 20 on the fuse portion 13 to about 0.1 to 0.8 μm corresponds to about 0.9 to 0.2 μm and is within about ± 10% ( It is possible to control the etching variation within about ± 0.09 to 0.02 μm, and about ± 0.15 μm of the square root of the square sum of the variation in the formed film thickness (about ± 10%) and the etching variation (about ± 10%). Within the wafer surface uniformity can be controlled.

  In the above embodiment, the case where the inorganic insulating protective film 14 is formed to have a thickness of about 1 μm has been described. However, when the interlayer insulating film 12 has good flatness, there may be no problem in the moisture resistance and characteristics of the product. Needless to say, the inorganic insulating protective film 14 may be thinner than about 1 μm. In addition, in the case of the wiring method (damascene) in which the interlayer insulating film is flattened by CMP technology and embedded after forming the trench in the formation of multilayer wiring, the uppermost layer wiring is relatively flat and has good coverage, and inorganic insulation Even if the protective film 14 is made thinner than 1 μm, the uppermost wiring is relatively flat and the coverage of the inorganic insulating protective film 14 is improved, and there is no problem in the moisture resistance and characteristics of the product. Needless to say, it is not necessary to further reduce the film thickness by etching.

  On the contrary, when the flatness of the interlayer insulating film 12 is poor or when the moisture resistance performance is deteriorated in the product reliability test, the inorganic insulating protective film 14 is formed to be about 1 μm or more and divided into one or more times. To do. Needless to say, the inorganic insulating protective film 14 may be formed of a combination of a single layer or multiple layers of a silicon nitride film or a silicon oxide film. Moreover, although the film thickness of the inorganic insulating protective film 20 above the fuse part 13 is reduced to about 0.1 to 0.8 μm, the present invention is not limited to this. For example, there is a case where the inorganic insulating protective film 20 on the fuse portion 13 does not remain (film thickness 0), and even if the inorganic insulating protective film 20 does not remain, there is a case where no problem occurs in the moisture resistance and characteristics of the product. Needless to say.

[Third Embodiment]
FIG. 8A is a plan view showing the arrangement of the main parts of the semiconductor integrated circuit device according to the third embodiment of the present invention, and FIGS. 8B and 8C are respectively x in FIG. 8A. _{1 -x 1 ', x 2 -x} 2' is a cross-sectional view taken along. FIG. 9 is a cross-sectional view taken along line yy ′ of FIG. 8 and 9, 12 is an interlayer insulating film formed on a semiconductor substrate (not shown), 13 is a fuse portion, 13A is a main conductive metal layer constituting the fuse portion 13, 13a is an antireflection layer, 13 b is a barrier metal layer, 14 is an inorganic insulating protective film, 15 is an organic insulating protective film, 16 is an opening of the organic insulating protective film 15, and 20 is an inorganic insulating protective film on the fuse portion 13.

  The semiconductor integrated circuit device according to the present embodiment exemplifies a case where the fuse portion 13 and the pad electrode (not shown) are formed by the uppermost wiring layer formed on the interlayer insulating film 12. After a via hole (not shown) is formed in the interlayer insulating film 12, a barrier metal layer 13b is formed to improve adhesion to the lower wiring and prevent a plug electrode metal or the like from penetrating. As the barrier metal layer 13b, a single layer film of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) and a metal layer of a multilayer film are formed with a thickness of about 100 nm. . After forming the barrier metal layer 13b, a plug electrode (not shown) of metal such as tungsten is formed in the via hole, and the barrier metal layer 13b in the region of the opening C in FIG. 8A (see FIG. 11A). Is removed by selective etching. On the upper part, a fuse part 13 is formed by the uppermost wiring layer. The main conductive metal layer 13A of the fuse portion 13 is mainly made of an aluminum metal and an aluminum-copper alloy, and an upper portion thereof is often used in a stepper intended for microfabrication in order to facilitate microfabrication in a lithography process. As an antireflection layer 13a for preventing reflection of light during exposure, such as a potassium fluoride (KrF: 248 nm) laser or i-line (365 nm) as an exposure light source, a titanium nitride (TiN) film or the like that is often used is used. The film is formed with a thickness of about 10 to 50 nm.

  As shown in FIG. 8B, a barrier metal layer 13b is formed at the lower portion of the fuse portion 13 and an antireflection layer 13a is formed at the upper portion. However, before the main conductive metal layer 13A is formed, the barrier metal layer 13b is formed in advance. The barrier metal layer 13b in the region of the opening C in FIG. 8 (a) is selectively etched, and the barrier metal layer 13b is not formed below the fuse portion 13 as shown in FIG. 8 (c). Note that, even when the thickness of the barrier metal layer 13b is reduced in the region of the opening C, the cutability of the fuse is improved. However, if the film is removed by etching, the cutability of the fuse is further improved.

  An opening 16 of the organic insulating protective film 15 is provided above the fuse portion 13, and an opening (not shown) of the inorganic insulating protective film 14 and an opening of the organic insulating protective film 15 are above the pad electrode (not shown). It is opened by a part (not shown). Further, when the inorganic insulating protective film 20 on the fuse portion 13 is thinned to ensure fuse cutting, the inorganic insulating protective film 14 exposed in the opening 16 of the organic insulating protective film is selectively etched as necessary. The film is thinned.

  As shown in FIG. 9, a laser beam (hv) pulse is focused and irradiated on a portion where the barrier metal layer 13b is not present, so that the fuse portion 13 is heated and exploded to blow. At this time, the antireflection layer 13a is also melted at the same time. Further, the inorganic insulating protective film 20 is also scattered at the same time when the fuse portion 13 is exploded and scattered. Since there is no high melting point barrier metal layer 13b, the fuse is cut more reliably. Further, the opening (not shown) of the organic insulating protective film 15 provided above the pad electrode (not shown) is formed in a wider range than the opening (not shown) of the inorganic insulating protective film 14. , Pad electrodes (not shown) and the vicinity thereof. The pad electrode and its vicinity can be configured in the same manner as in FIGS.

  In addition, although the case where the fuse portion 13 is formed of the uppermost wiring layer is illustrated, the present invention is not limited to this, and a wiring layer that is one or two layers below the uppermost layer may be used. Needless to say. This is because when the barrier metal layer 13b exists under the fuse portion 13, the fuse portion 13 is one layer lower than the uppermost layer than when the uppermost wiring layer is used for the fuse portion 13. Since the interlayer insulating film layer is flatter when the wiring layer two layers below is used, the remaining probability of the barrier metal layer at the time of fuse cutting increases and the probability of disconnection failure increases. This is because the barrier metal layer 13b does not exist in the embodiment, so that cutting can be performed more reliably.

  In the present embodiment, the case where the two fuse portions 13 are formed under one opening portion 16 is illustrated, but the present invention is not limited to this, and the fuse portion 13 is formed under one opening portion 16. Needless to say, the number of the sections 13 may be one, or three or more.

  10 to 12 are process sectional views showing a method of manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention, and FIG. 13 is a process flow diagram showing the same manufacturing method. This will be described below with reference to FIGS.

  In FIG. 10A, the elements formed on the semiconductor substrate 11 are wired with a multilayer wiring layer (25, etc.) formed on the interlayer insulating film 24 and a plug metal (not shown). A trench for wiring is formed on the surface of the interlayer insulating film 24, a wiring layer 25 buried in the trench is formed, and then the next interlayer insulating film 26 is formed on the entire surface (step S41 in FIG. 13). Here, the case where the wiring layer 25 is buried in the groove is illustrated, but the present invention is not limited to this. The wiring layer 25 is formed on the surface of the flattened interlayer insulating film 24, and then the next layer is formed on the entire surface. Needless to say, the interlayer insulating film 26 may be formed and the surface thereof may be planarized.

  Next, a via hole 27 for contact is formed in the interlayer insulating film 26 above the wiring layer 25 to be connected (FIG. 10B, step S42 in FIG. 13). Next, a barrier metal layer 28 for improving adhesion to the lower wiring layer 25 and preventing penetration of plug electrode metal or the like is formed over the entire surface of the semiconductor substrate by a CVD method or the like, which is a normal method. As the barrier metal layer 28, a single-layer film and a multi-layer metal layer of dense metal films such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) are formed to a thickness of about 100 nm. Next, a plug electrode 29 made of a metal such as tungsten is formed in the via hole 27 by a normal selective growth method (FIG. 10C, steps S43 and S44 in FIG. 13).

  Next, a photoresist 30 is applied to the entire surface, and an opening C is formed in the resist corresponding to the fuse portion by ordinary mask exposure / development. Thereafter, the barrier metal layer 28 in the opening C of the photoresist 30 and the metal layer of the plug electrode 29 that may remain in a small amount are removed by selective etching (FIG. 11A, step S45 in FIG. 13). S47). Note that, even when the thickness of the barrier metal layer 28 is reduced, the cutting performance of the fuse is improved, but the cutting performance of the fuse is further improved by removing it by etching.

  Next, as shown in FIG. 11B, the photoresist 30 is removed (step S48 in FIG. 13), and then the uppermost main conductive metal layer 13A is formed here, and the antireflection layer is formed thereon. After forming 13a, the fuse portion 13 is formed simultaneously with a pad electrode (not shown) as an external extraction electrode by a normal lithography / etching technique (step S49 in FIG. 13). At this time, the barrier metal layer 28 is also etched into the same shape as the antireflection layer 13a and the main conductive metal layer 13A to form the barrier metal layer 13b. The main conductive metal layer 13A of the fuse portion 13 is mainly made of an aluminum metal and an aluminum-copper alloy, and an upper portion thereof is often used in a stepper intended for microfabrication in order to facilitate microfabrication in a lithography process. As an antireflection layer 13a for preventing reflection of light during exposure, such as a potassium fluoride (KrF: 248 nm) laser or i-line (365 nm) as an exposure light source, a titanium nitride (TiN) film or the like that is often used is used. The film is formed with a film thickness of about 10 to 50 nm.

Next, a plasma silicon nitride film (P-SiN) is formed to a thickness of about 1 μm as the inorganic insulating protective film 14 (step S50 in FIG. 13). The inorganic insulating protective film 14 is not limited to the plasma silicon nitride film, and is usually a silicon oxide film (SiO ₂ film), a silicon oxynitride film (SiON film), or a single layer film of a plasma silicon nitride film. Needless to say, it may be a multilayer film combining these.

  Next, a photoresist (not shown) is applied on the inorganic insulating protective film 14, the photoresist on the upper portion of the fuse portion 13 is opened, and the inorganic insulating protective film 20 in the opening A corresponding to the opening is formed by normal etching. The film is thinned to about 0.1 to 0.8 μm (FIG. 11 (c)). By making the inorganic insulating protective film 20 thinner, the fuse part 13 can be fused and cut stably and reliably with a smaller laser energy than when the inorganic insulating protective film 20 is thick. Damage to the lower interlayer insulating film 26 and the like can be reduced. However, when there is no inorganic insulating protective film on the upper portion of the fuse portion 13, since the moisture-resistant protective film is lost, the reliability tends to deteriorate.

  Then, after opening (not shown) the inorganic insulating protective film 14 on the pad electrode (not shown) which is an external extraction electrode, a photosensitive polyimide film is applied and baked as the organic insulating protective film 15 to form a film of about 10 μm. The film is formed with a thickness. An opening 16 on the fuse portion 13 and an opening (not shown) on a pad electrode (not shown), which is an external lead electrode, are formed by exposure and development processing and cured in a thermosetting furnace (FIG. 12).

  It should be noted that the adjustment of thinning of the thickness of the inorganic insulating protective film 20 on the fuse portion 13 is not limited to the previous etching process, and the thinning adjustment is further performed by etching after the opening and curing of the organic insulating protective film 15. Needless to say, you can.

  In this embodiment, the case where the fuse portion 13 is formed of the uppermost wiring layer is illustrated. In this case, the steps after the formation of the inorganic insulating protective film 14 are performed in the first embodiment described above. The steps described in the embodiment and the second embodiment can be applied.

  In the above, the case where the fuse portion 13 is formed of the uppermost wiring layer is illustrated. However, when the fuse portion 13 is formed using a wiring layer one layer lower than the uppermost layer, the process shown in FIG. After the antireflection layer 13a, the fuse portion 13 and the barrier metal layer 13b are formed in a desired shape, an interlayer insulating film is formed, and then a wiring layer (uppermost layer) is formed, and an inorganic insulating protection is formed thereon. A film 14 is formed. In this case, the inorganic insulating protective film 14 on the fuse portion 13 is completely removed by selective etching, and the interlayer insulating film is subsequently etched to make the thickness of the interlayer insulating film on the fuse portion 13 0.1 to 0.8 μm. Thin film. In this case, the configuration of the upper portion of the fuse portion 13 is the same as that in the case of FIG. The same applies to the case where the fuse portion 13 is formed using a wiring layer two layers below the uppermost layer. In these cases, the etching time is longer than in the case where the uppermost wiring layer is formed, and the variation of the film thickness of the interlayer insulating film on the fuse portion 13 after the etching becomes large.

[Fourth Embodiment]
14 and 15 are process sectional views showing a method of manufacturing a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 15B is a main partial cross-sectional view of the semiconductor integrated circuit device according to this embodiment. In FIG. 15B, 11 is a semiconductor substrate, 24 and 41 are interlayer insulating films, and 13 is a main conductive metal layer. 13A is a fuse part, 14 is an inorganic insulating protective film, 15 is an organic insulating protective film, 16 is an opening of the organic insulating protective film 15, 20 is an inorganic insulating protective film on the fuse part 13, 40 is a barrier metal layer, 42 Is a via hole, and 43 is a groove for wiring.

  In the semiconductor integrated circuit device of this embodiment, as shown in FIG. 15B, the fuse portion 13 and the pad electrode (not shown) are formed by the uppermost wiring layer formed in the groove 43 of the interlayer insulating film 41. The case where is formed is illustrated. Via holes 42 and trenches 43 are formed in the interlayer insulating film 41 to form a so-called dual damascene wiring structure. A barrier metal layer 40 is formed to improve adhesion to the lower wiring and prevent penetration. As the barrier metal layer 40, a single-layer film and a multi-layer metal layer of dense metal films such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) are formed with a thickness of about 100 nm. . After the barrier metal layer 40 is formed, the barrier metal under the fuse portion 13 is removed by selective etching, and then copper or the like is formed on the via hole 42 and the groove 43 by a commonly used technique such as plating. An inorganic insulating protective film 14 and an organic insulating protective film 15 are formed on the main conductive metal layer 13A and the interlayer insulating film 41. Above the fuse portion 13, the inorganic insulating protective film 20 is a region of the opening A. The organic insulating protective film 15 has an opening 16 formed therein.

  This embodiment is different from the third embodiment in that the wiring layer for forming the fuse portion 13 has the above-described dual damascene wiring structure and no antireflection layer on the main conductive metal layer 13A. As in the third embodiment, since the high melting point barrier metal layer 40 is not present under the fuse portion 13, the fuse cutting is more reliable. In addition, although the case of the copper wiring fuse was illustrated, it is not limited to this, and an embedded wiring of aluminum or another metal may be used. Needless to say, the fuse portion 13 is not limited to the uppermost wiring layer.

  FIG. 16 is a process flow diagram showing the manufacturing method in the present embodiment. Hereinafter, a method for manufacturing the main part will be described with reference to FIGS.

  In FIG. 14A, elements formed on the semiconductor substrate 11 are wired with a multilayer wiring layer (25, etc.) formed on the interlayer insulating film 24 and a plug metal (not shown). A wiring trench is formed on the surface of the interlayer insulating film 24, the wiring layer 25 buried in the groove is formed, and then the next interlayer insulating film 41 is formed on the entire surface (step S61 in FIG. 16).

  Next, a via hole 42 and a wiring groove 43 are formed in the interlayer insulating film 41, and a barrier metal layer 40 is formed on the inner surface to improve adhesion to the lower wiring and prevent penetration (FIG. 14B). ), Steps S62 and S63 in FIG. Here, as the barrier metal layer 40, a single-layer film and a multi-layer metal layer of dense metal films such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) are formed to a thickness of about 100 nm. To do.

  Next, a photoresist 30 is applied to the entire surface, and an opening C is formed in the resist corresponding to the fuse portion by ordinary mask exposure / development. Then, the barrier metal layer 40 in the opening C of the photoresist 30 is removed by selective etching (FIG. 14C, steps S64 to S66 in FIG. 16). Here, even when the thickness of the barrier metal layer 40 is reduced by etching, the cutability of the fuse may be improved, but it is removed as much as possible.

  Next, after removing the photoresist 30, a main conductive metal layer 13A such as copper is formed in the via hole 42 and the groove 43 by a commonly used technique such as plating. At this time, the main conductive metal layer 13A is buried in the via hole 42 and the groove 43, and then planarized by using at least one of the chemical mechanical polishing technique and the etch back technique. Thereby, the fuse part 13 and a pad electrode (not shown) are formed. On top of this, an inorganic insulating protective film 14 such as a plasma silicon nitride film is formed (FIG. 15A, steps S67 to S69 in FIG. 16).

  Thereafter, as in the third embodiment, the inorganic insulating protective film 20 above the fuse portion 13 is thinned to a thickness of about 0.1 to 0.8 μm by etching in the region of the opening A. Thereafter, an organic insulating protective film 15 such as polyimide is formed, and an opening 16 of the organic insulating protective film 15 is formed above the fuse portion 13. Note that the openings of the inorganic insulating protective film 20 and the organic insulating protective film 15 above the pad electrode (not shown) can be formed in the same manner as in the third embodiment.

  In the third embodiment, a plug electrode 29 made of metal such as tungsten is formed in the via hole 27 (step S44), and the main conductive metal layer 13A for fuse is formed thereon (step S49). On the other hand, in the fourth embodiment, the main conductive metal layer 13A for the fuse is formed in both the via hole 42 and the groove 43 (step S68).

[Fifth Embodiment]
The fifth embodiment can be applied to the first to fourth embodiments described above, and only the main part will be described here. 17 (a) and 17 (b) are plan views showing the arrangement of the main parts of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. In FIGS. 17 (a) and 17 (b), reference numerals 100 to 106 denote fuse wirings each having one electrically continuous fuse portion, D and E are thinned regions of the inorganic insulating protective film, and organic insulation. It is an opening of a protective film. L0, L1, L′ 1, L3, L′ 3, L ″ 3, L5, L′ 5, L6, L′ 6, and L ″ 6 are laser irradiation units.

  In FIG. 17A, conventionally, the fuse wiring 100 is melted and cut only by the laser irradiation part L0, and the both ends 0 and 0 ′ of the fuse wiring 100 are electrically cut. On the other hand, in the present embodiment, the fuse wiring 101 is electrically cut between the two end portions 1 and 1 ′ of the fuse wiring 101 at two locations of the laser irradiation portions L1 and L′ 1. Further, the fuse wiring 103 is electrically disconnected between the both end portions 3 and 3 ′ of the fuse wiring 103 at three locations of the laser irradiation portions L3, L′ 3, and L ″ 3. The fuse wirings 102 and 104 show a state where they are not cut.

  As in this embodiment, by cutting a plurality of electrically continuous fuse portions at a plurality of locations, the cutting resistance value at one place is in series, so that the cutting resistance value of the fuse can be increased. . In addition, even if the cutting failure is caused at one place, it is possible to cut at the other fuse cutting portion, so that the cutting can be ensured. That is, the cutting resistance value is a multiple of the cutting location, and the cutting accuracy (probability) is the product of the cutting probability at one location.

  Furthermore, by using the configuration shown in FIG. 17B, the fuse can be cut at a high speed. In FIG. 17B, the two fuse wirings 105 and 106 are connected to the electrical ends 5 and 5 of the fuse wiring 105 by the laser irradiation portions L5, L′ 5 and L6, L′ 6, L ″ 6. 'And the electrical ends 6 and 6' of the fuse wiring 106 are cut in circuit operation.

  That is, two fuse wirings 105 and 106 each having a fuse part that can be cut at a plurality of positions are provided in one opening E, and their laser irradiation parts L5, L'5, L6, L'6, L '' All 6 are arranged on a straight line along the line II ′. With this arrangement, the laser feed of the laser processing device is usually realized by moving the wafer, but it is possible to irradiate the laser on a straight line, and the fuse can be moved at high speed while moving without stopping the semiconductor substrate. Can be cut. As a result, throughput can be improved, productivity is improved, and TAT is shortened.

  In the above-described embodiment, the number of cut portions in each of the fuse wirings 102 to 106 is two or three. However, the number of cut portions is not limited to this and may be plural. FIG. 17B shows the case where the two fuse wirings 105 and 106 are provided in one opening E, but it goes without saying that the number may be three or more. However, although the cutting accuracy increases as the number of cutting points increases, the occupied area increases, and the number of chips that can be taken decreases as the area increases. That is, there is a trade-off relationship between the cutting accuracy and the number of chips, and the cutting location is determined by the relationship between the two.

  Further, when the above-described configuration is applied to the third and fourth embodiments, the barrier metal layer is removed at least under the planned cutting site (laser irradiation part).

  Needless to say, even when the configuration of the present embodiment is applied to the conventional configuration shown in FIG. 22, the specific effects described in the present embodiment can be obtained.

[Sixth Embodiment]
The sixth embodiment can be applied to the first to fifth embodiments described above (however, the fuse portion is formed of the uppermost wiring layer), and here the main part thereof is described. Only explained. FIG. 18 is a plan view of the main part of the semiconductor integrated circuit device according to the sixth embodiment of the present invention. In FIG. 18, 31 is a fuse portion, 32, 33 and 34 are metal wiring layers, 35 is a guard band, F is a thinned region of the inorganic insulating protective film, G is an opening of the organic insulating protective film, and CH1 to CH3 are wirings. It is a contact hole part between layers.

  In FIG. 18, the fuse portion 31 is formed of the uppermost wiring layer, and is electrically connected to the wiring layer 32 one layer lower than the uppermost layer by a plug metal in the contact hole portion CH1. The other of the fuse portions 31 is electrically connected to the wiring layer 34 one layer lower than the uppermost layer via the plug metal in the contact hole CH2, and then connected to the wiring layer 33 via the plug metal in the contact hole CH3. Connected. The wiring layer 33 may be a top layer wiring, or may be a wiring layer two or more layers below the top layer. In addition to the configuration of FIG. 18, both ends of the fuse portion 31 may be an electrical wiring layer change using a single contact hole as in the wiring layer 32, or may be performed twice or more as in the wiring layer 33. Needless to say, the electrical wiring layer may be changed using contact holes. Further, the size relationship between the thinned region F of the inorganic insulating protective film and the opening G of the organic insulating protective film is not particularly limited.

  The guard band 35 is formed of a conductive layer. As the conductive layer, a wiring layer from the uppermost layer to the lowermost layer, a plug metal layer for contact between wirings, a substrate portion, or the like is used. The wiring layers constituting the guard band 35 are electrically connected to each other. Further, the guard band 35 surrounds the contact holes CH1 to CH3 as shown in FIG. However, the wiring layers 32 and 33 for electrically drawing out the fuse part 31 are separated by a predetermined distance so as not to be electrically connected to the guard band 35. Therefore, if the portion of the guard band 35 that intersects with the lead-out wiring layers 32 and 33 is the same wiring layer, the portion that is not partially connected can be a very small portion.

  According to the present embodiment, by reconnecting the fuse wiring inside the guard band 35 with the contact holes CH1 to CH3, moisture and ionic components are removed from the cut portion (not shown) of the fuse portion 31 after cutting. The path of penetration through the remaining fuse wiring is extended, and the plug metal embedded in the contact holes CH1 to CH3 is a metal that is not easily corroded, such as tungsten. It can be blocked by the metal part. Further, since the entire periphery of the contact holes CH1 to CH3 is surrounded by the guard band 35, it is possible to prevent moisture and ion components from penetrating inside the card band 35, and to the outside of the guard band 35 (semiconductor element portion). Water and ionic components do not come and reliability can be improved. The potential of the guard band 35 is also connected to the semiconductor substrate, and can be freely determined within the well. That is, it goes without saying that positive, negative and zero potentials can be set freely. In addition, although the case of the single guard band 35 is illustrated, the area increases, but the double or more guard bands 35 are used, and positive and negative voltages are applied and zero potential is set, respectively. It is good also as a trap of ion and moisture.

  In this embodiment, both ends of the wiring of the fuse part 31 are connected to the lower wiring layer through the contact holes CH1 to CH3 having the plug metal part, but only one end of the wiring of the fuse part 31 is connected. Is connected to the lower wiring layer through a contact hole, it is possible to prevent corrosion reaction and penetration of moisture and ionic components at one end thereof.

  Further, even when the contact holes CH1 and CH2 at the end of the wiring of the fuse portion 31 are not filled with the plug metal as in the fourth embodiment (see FIG. 15B), the corrosion prevention effect by the plug metal is achieved. However, the effect obtained by providing the guard band 35 can be obtained.

  Next, in the configurations of the first and second embodiments (see FIGS. 1 and 4), the fuse portion 13 is formed of at least a main conductive metal layer and a barrier metal layer formed thereunder. In the case, preferable dimensions of each part will be described with reference to FIGS. 19 and 20.

  FIG. 19 is a main cross-sectional view for explaining dimensions of each part of the semiconductor integrated circuit device according to the embodiment of the present invention. In FIG. 19, 12 is an interlayer insulating film, 36 is a fuse portion, 37 is a barrier metal layer, 38 is an antireflection layer, and 39 is an inorganic insulating protective film. FIG. 20 is a diagram showing the relationship between the dimensions of each part and the ease of cutting the fuse part by laser irradiation.

In FIG. 19, an inorganic insulating protective film 39 such as a plasma silicon nitride film is formed on the interlayer insulating film 12 with the uppermost wiring layer, and a region including the fuse part 36 is opened. The inorganic insulating protective film 39 is thinned by normal dry etching using a resist as a mask. Assuming that the thickness of the inorganic insulating protective film 39 on the fuse portion 36 is t _p1 and the thickness of the inorganic insulating protective film 39 on the side wall of the fuse portion 36 is t _p2 ,
t _p1 <t _p2
It is shown by the relational expression.

This is a shape that occurs because the normal dry etching of the inorganic insulating protective film 39 is anisotropic etching, and the etching speed in the horizontal direction is slower than the etching speed in the vertical direction. This is the same as the principle of the method of forming the side wall spacer of the gate electrode portion of the LDD (Lightly Doped Drain) transistor. On the other hand, since wet etching is isotropic etching, the film thickness t _p2 of the inorganic insulating protective film 39 on the side wall of the fuse portion 36 is also substantially equal to the film thickness t _p1 of the inorganic insulating protective film 39 on the fuse portion. .

It is desirable that the ease of cutting Y (au) of the fuse portion 36 is as thin as t _p1 . When other conditions are evaluated as shown in FIG. Further, if the upper width W _FT and the lower width W _FB (≧ W _FT ) of the fuse portion 36 are larger than about 1.0 μm, it becomes difficult to cut the fuse portion 36 easily (see FIG. 20B). Further, when the thickness t _F3 of the barrier metal layer 37 exceeds about 150 nm, the barrier metal or the like remains, and the fuse cutting performance deteriorates (see FIG. 20C).

In other words, the ease of cutting Y of the fuse portion 36 depends on whether or not the barrier metal layer 37 can be scattered, depending on the fact that the inorganic insulating protective film 39 prevents the explosion from proceeding until it is heated to a sufficiently high temperature with laser light. ing. However, when the film thickness t _p1 of the inorganic insulating protective film 39 is too thick, the energy that explodes the fuse part is also applied as damage in the direction of the interlayer insulating film 12 and cracks are generated, so that no damage occurs. An upper limit value of energy (about 800 nm) can be set (FIG. 20 (a)). The lower limit value is a set value including an etching variation so that there is no film thickness variation of the fuse portion 36 itself due to overetching of the fuse portion 36.

The wider the width W _FB of the fuse portion 36, the higher the possibility that the barrier metal layer 37 remains when the fuse is cut. _Therefore , the width W _FB is preferably as thin as possible. The film thickness t _{F2 of the} main conductive metal layer 36A made of, for example, an aluminum layer is about 500 nm. In this case, the upper limit value of the width of the fuse portion 36 is about 1.0 μm, and the lower limit value is a limit for fine processing. This is also the case in the third and fourth embodiments when the barrier metal layers 13b and 40 (see FIG. 12, FIG. 15 (b), etc.) below the fuse portion 13 are not completely removed and are thinned. It is the same.

The thickness t _F3 of the barrier metal layer 37 is preferably thin, but the lower limit is determined by the barrier property at the contact portion, and cannot be 0 nm at the contact portion. Therefore, the film thickness t _F3 of the barrier metal layer 37 is desirably about 50 to 150 nm. However, it is needless to say that the barrier property is not limited to this.

  For fine processing of the fuse portion 36, a silicon dioxide film or the like (not shown) may be thinly formed and patterned on the fuse portion 36 to form an etching mask for the fuse wiring layer. In this case, the film thickness of the silicon dioxide film or the like can be considered as the film thickness of the inorganic insulating protective film 39 on the fuse portion 36.

Further, the film thickness t _F1 of the antireflection layer 38 is a film thickness that provides an effect of preventing reflection of light with respect to the exposure light source, and a cutting characteristic is obtained at a thickness of about 10 to 50 nm of a commonly used titanium nitride (TiN) film. There is no difference.

  Further, as a laser used for cutting the fuse portion in the semiconductor integrated circuit device of the above embodiment, for example, a laser beam from a YLF (yttrium-lithium-fluoride) crystal is an infrared ray having a wavelength of 1047 to 1053 nm, and a pulse width is about Those having a short pulse of 2 to 10 nsec are preferable. In addition, there are other YAG (yttrium-aluminum-garnet) short crystal infrared rays with a wavelength of 1064 nm and a pulse width of about 40 nsec, but the pulse width shorter than 10 nsec is advantageous for cutting the fuse portion of the metal wiring. Tend to be. This is because if the pulse width is too long, damage to the base of the fuse portion is likely to occur.

  Further, as shown in FIG. 19, the fuse portion 36 includes, for example, an antireflection layer 38, a main conductive metal layer 36A, and a barrier metal layer 37. The main conductive metal layer 36A is made of an aluminum-based metal, and the antireflection layer. When the fuse 38 and the barrier metal layer 37 are made of a titanium nitride film, a titanium film, or the like, when the fuse portion 36 is cut, the processing yield is increased by cutting using a laser light source having two or more wavelength components. It becomes possible. In this example, it is possible to increase the processing yield by using a laser processing apparatus using so-called SDWL (Simultaneous dual wavelength lasers) having two types of oscillation wavelengths of laser light of 1340 nm and 1050 nm.

  This is because, when laser light having a wavelength of 1340 nm is used for cutting the main conductive metal layer 36A made of a metal mainly made of aluminum, heat absorption is high and the energy margin is increased with respect to silicon of the underlying semiconductor substrate. It is possible to take. Further, the antireflection layer 38 and the barrier metal layer 37 made of a titanium nitride film, a titanium film, or the like can be cut by heating with an infrared ray of 1050 nm. That is, laser processing of a multilayer film having different absorption characteristics is possible. Since the laser energy margin can be increased, the processing yield can be further increased by using this apparatus for cutting the fuse.

  Next, a method for evaluating a semiconductor integrated circuit device according to an embodiment of the present invention will be described. Here, an evaluation method of the above-described ease of cutting the fuse portion Y (see FIG. 20) will be described. FIGS. 21A and 21B are a conceptual diagram and a characteristic diagram for explaining this evaluation method.

  As shown in FIG. 21 (a), it has a fuse group in which n, m, and h fuse portions 51 formed on a semiconductor substrate are connected in parallel (n, m, and h are different numbers of 2 or more, respectively). Make a sample. The fuse portions 51 of these samples are the same as those of the semiconductor integrated circuit device to be evaluated, and the fuse portions 51 of each sample are connected by a wiring layer 52 that forms the fuse portion 51. Next, the resistance value between the terminals of the fuse group of each sample (between ab, ad, ac, bd, etc.) is measured as an initial characteristic. Next, laser irradiation is performed to cut all the fuse portions for each sample, and then the resistance value between the terminals of the fuse group (between ab, ad, ac, bd, etc.) is again measured. It is measured as a characteristic after cutting. For each sample, the ease of cutting (cutting yield) Y is calculated from the results of the initial characteristics and the characteristics after cutting, and plotted (FIG. 21 (b)). In FIG. 21B, the number of cuts is plotted on the horizontal axis (log scale), and the ease of cutting (cutting yield) Y is plotted on the vertical axis (linear scale).

  In addition, although resistance value between ab, ad, ac, bd, etc. was measured as said initial characteristic and the characteristic after cutting | disconnection, these are examples and looked at from terminal a. Conductivity confirmation of other terminals b, c, and d is measured with initial characteristics, and after cutting, the disconnection is confirmed with a resistance value between ab and a-d and a resistance value between bc and the conductivity of the electrode. For confirmation, measurement between a-c and b-d is necessary.

  Moreover, the method of calculating the ease of cutting (cutting yield) Y from the results of the initial characteristics (characteristics before cutting) and the characteristics after cutting, specifically, compares the resistance value before cutting and the resistance value after cutting. , It is determined that the resistance value before and after cutting has changed more than a certain value is determined to be cut, or the resistance value after cutting is determined to be higher than a certain resistance value and can be cut. The ease of cutting (cutting yield) Y is calculated by dividing the number by the total number of cutting processes. That is, the ease of cutting (cutting yield) Y means the rate of cutting.

  In each sample, since most of the fuse parts can be cut, it is impossible to calculate the cutting probability of each individual fuse. However, as shown in FIG. The h ease of cutting Y is on a straight line, and it becomes possible to accurately estimate and evaluate the ease of cutting Y in the number applied (actual use) to an actual semiconductor integrated circuit device.

  In this example, three samples are used in the case where the number of parallel-connected fuse portions is n, m, and h. However, it is possible to use two or more samples. As the number of samples increases, the accuracy of estimating the easiness of cutting Y in the actual number of fuses increases.

  Conventionally, the resistance values at both ends of each fuse portion are measured after cutting, but there is a limit to the number of electrodes that can be arranged on the wafer. In addition, in order to measure on a wafer, the conductivity between the probe and the electrode must be reliable, and even if the probe is displaced from the electrode, the resistance value increases, and even if it cannot be cut, it is mistakenly assumed that it could be cut. There was a possibility of judging. In addition, it was impossible to evaluate the cutting yield when the number of cuttings in the cutting yield nearly 100% increased.

  INDUSTRIAL APPLICABILITY The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention have effects such as prevention of a decrease in reliability and a decrease in manufacturing yield due to the cutting of the fuse portion, a redundant relief circuit, a function adjustment circuit, etc. for a large capacity memory It is useful for a semiconductor integrated circuit device or the like having a fuse portion used for the above.

1 is a main part sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 5 is a process cross-sectional view illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. 1 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. The principal part sectional drawing of the semiconductor integrated circuit device in the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 2nd Embodiment of this invention. The flowchart which shows the manufacturing method of the semiconductor integrated circuit device in the 2nd Embodiment of this invention. 10 is a plan view and a sectional view of main parts of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. FIG. 7 is a main part sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 3rd Embodiment of this invention. The flowchart which shows the manufacturing method of the semiconductor integrated circuit device in the 3rd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 4th Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor integrated circuit device in the 4th Embodiment of this invention. The flowchart which shows the manufacturing method of the semiconductor integrated circuit device in the 4th Embodiment of this invention. The top view of the semiconductor integrated circuit device in the 5th Embodiment of this invention. The top view of the semiconductor integrated circuit device in the 6th Embodiment of this invention. Sectional drawing for demonstrating the preferable dimension of each part of the semiconductor integrated circuit device in embodiment of this invention. It is a figure which shows the relationship between the dimension of each part of the semiconductor integrated circuit device in embodiment of this invention, and the cutting | disconnection ease of a fuse part. The figure for demonstrating the evaluation method of the semiconductor integrated circuit device in embodiment of this invention. FIG. 10 is a main part sectional view of a conventional semiconductor integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Interlayer insulating film 13 Fuse part 14 Inorganic insulating protective film 15 Organic insulating protective film 16 Opening part 17 Pad electrode 18 Opening part 19 Opening part 20 Inorganic insulating protective film on a fuse part

Claims (24)

In a semiconductor integrated circuit device having a fuse portion,
An insulating film formed on the semiconductor substrate;
Comprising the fuse portion comprising a wiring layer formed on the insulating film;
The semiconductor integrated circuit device according to claim 1, wherein the wiring layer of the fuse portion has a conductive metal layer made of at least copper. The semiconductor integrated circuit device according to claim 1,
The wiring layer of the fuse portion further includes a barrier metal layer formed on the insulating film,
The semiconductor integrated circuit device, wherein the conductive metal layer is formed on the barrier metal layer. The semiconductor integrated circuit device according to claim 2,
The semiconductor integrated circuit device, wherein the barrier metal layer is formed of a single layer film or a multilayer film. The semiconductor integrated circuit device according to claim 2,
The semiconductor integrated circuit device, wherein the barrier metal layer is a single layer film made of titanium nitride, titanium, or tungsten nitride, or a multilayer film thereof. The semiconductor integrated circuit device according to any one of claims 2 to 4,
The semiconductor integrated circuit device, wherein the barrier metal layer has a thickness of 150 nm or less. The semiconductor integrated circuit device according to any one of claims 1 to 5,
A semiconductor integrated circuit device, further comprising an inorganic insulating protective film formed on the wiring layer and the insulating film. The semiconductor integrated circuit device according to claim 6.
The inorganic insulating protective film is a single-layer film of a silicon oxide film, a silicon oxynitride film, or a plasma silicon nitride film, or a multi-layer film that is a combination of these films. . The semiconductor integrated circuit device according to claim 6 or 7,
2. The semiconductor integrated circuit device according to claim 1, wherein the inorganic insulating protective film on the fuse portion is not thinned or remains by etching. The semiconductor integrated circuit device according to any one of claims 6 to 8,
The semiconductor integrated circuit device according to claim 1, wherein the inorganic insulating protective film on the fuse portion has a thickness of 0.1 μm to 0.8 μm. The semiconductor integrated circuit device according to any one of claims 6 to 9,
A semiconductor integrated circuit device, further comprising an organic insulating protective film formed on the inorganic insulating protective film. The semiconductor integrated circuit device according to claim 10.
A semiconductor integrated circuit device, wherein an opening is formed in the organic insulating protective film on the fuse portion. The semiconductor integrated circuit device according to claim 10 or 11,
The semiconductor integrated circuit device, wherein the organic insulating protective film is polyimide. The semiconductor integrated circuit device according to any one of claims 1 to 12,
2. The semiconductor integrated circuit device according to claim 1, wherein the fuse portion is formed of an uppermost wiring layer among a plurality of wiring layers formed on the insulating film. The semiconductor integrated circuit device according to any one of claims 1 to 13,
An upper limit value of the width of the fuse portion is 1.0 μm, and a lower limit value is a limit of fine processing. The semiconductor integrated circuit device according to any one of claims 1 to 14,
2. The semiconductor integrated circuit device according to claim 1, wherein the wiring layer of the fuse portion has a dual damascene wiring structure in which the conductive metal layer is formed in a hole and a wiring groove provided in the insulating film. The semiconductor integrated circuit device according to claim 15,
2. The semiconductor integrated circuit device according to claim 1, wherein the conductive metal layer is formed on a barrier metal layer formed on an inner surface of the hole and the wiring groove. The semiconductor integrated circuit device according to claim 15 or 16,
The semiconductor integrated circuit device according to claim 1, wherein the holes are provided in communication with the bottom surfaces on both sides of the wiring groove. The semiconductor integrated circuit device according to any one of claims 15 to 17,
A lower insulating film formed under the insulating film; and
Further comprising a lower wiring layer embedded in a wiring groove provided in the lower insulating film;
The semiconductor integrated circuit device according to claim 1, wherein the hole reaches the lower wiring layer. The semiconductor integrated circuit device according to any one of claims 1 to 18,
The semiconductor integrated circuit device, wherein the fuse portion is surrounded by a guard band made of a conductive layer. The semiconductor integrated circuit device according to claim 19,
A semiconductor integrated circuit device using a wiring layer from the uppermost layer to the lowermost layer and a plug metal layer for contact between the wirings as the conductive layer of the guard band. In a method for manufacturing a semiconductor integrated circuit device having a fuse portion,
Forming an insulating film on the semiconductor substrate (a);
And (b) forming the fuse portion made of a wiring layer on the insulating film,
The method of manufacturing a semiconductor integrated circuit device, wherein the wiring layer of the fuse portion includes at least a conductive metal layer made of copper. The method of manufacturing a semiconductor integrated circuit device according to claim 21,
The step (b) includes a step (b1) of forming a barrier metal layer on the insulating film and a step (b2) of forming the conductive metal layer on the barrier metal layer. A method of manufacturing a semiconductor integrated circuit device. The method of manufacturing a semiconductor integrated circuit device according to claim 21,
The step (b)
Forming a hole and a groove for wiring in the insulating film (b1);
Forming a barrier metal film on the inner surface of the hole and the wiring groove in the insulating film (b2);
After the step (b2), a step (b3) of embedding the conductive metal layer in the hole and the trench for wiring;
After the step (b3), a step (b4) of forming the fuse portion by planarizing the conductive metal layer by using at least one of a chemical mechanical polishing technique and an etch back technique. A method for manufacturing a semiconductor integrated circuit device, comprising: In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 21 to 23,
After the step (b), a step (c) of forming an inorganic insulating protective film on the wiring layer and the insulating film, and a step of etching the inorganic insulating protective film on the fuse portion to at least reduce the thickness ( d) A method of manufacturing a semiconductor integrated circuit device.

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