CN111785680B - Method and device for manufacturing fuse - Google Patents

Method and device for manufacturing fuse Download PDF

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Publication number
CN111785680B
CN111785680B CN202010607902.7A CN202010607902A CN111785680B CN 111785680 B CN111785680 B CN 111785680B CN 202010607902 A CN202010607902 A CN 202010607902A CN 111785680 B CN111785680 B CN 111785680B
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groove
layer
trench
target area
metal layer
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CN111785680A (en
Inventor
卓红标
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

Abstract

The application discloses a manufacturing method and a device of a fuse, wherein the method comprises the following steps: forming a metal layer on the dielectric layer; etching the first target area and the second target area to expose the dielectric layers of the first target area and the second target area, forming a first groove in the first target area, and forming a second groove in the second target area; forming a passivation layer on the metal layer and in the first groove and the second groove; etching the first target area, the second target area and the third target area, forming a third groove in the first target area, forming a fourth groove in the second target area and forming a fifth groove in the third target area; forming a protective layer on the surfaces of the passivation layer, the third groove, the fourth groove and the fifth groove; and removing the protective layers at the bottoms of the third groove, the fourth groove and the fifth groove above the passivation layer, and reserving the protective layers on the side walls of the third groove, the fourth groove and the fifth groove. The protection layer is formed on the side wall of the fuse, so that the yield is improved.

Description

Method and device for manufacturing fuse
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method and a device for manufacturing a fuse.
Background
In a chip of a semiconductor integrated circuit, a fuse is generally provided to protect the chip. When the current in the chip is too large, the heat generated by the fuse can fuse the fuse, and the current is disconnected, so that the chip is protected.
Referring to fig. 1, a schematic cross-sectional view of a fuse provided in the related art is shown. As shown in fig. 1, a metal layer 120 is formed on a dielectric layer 110, a passivation layer 130 is formed on the metal layer 120, a first fuse trench 101 and a second fuse trench 102 are formed in the passivation layer 130, the metal layer 120 and the dielectric layer 110, the metal layer 120 between the first fuse trench 101 and the second fuse trench 102 forms a fuse (as shown by a dotted line in fig. 1), an extraction trench 103 is formed in the passivation layer 130, and the metal layer 120 at the bottom of the extraction trench 103 is exposed and can be used as an extraction solder joint (Pad).
As shown in fig. 1, since the fuse provided in the related art is small and thin in size, there is a certain probability that it will be damaged by water pressure during dicing in dicing a wafer on which the fuse is formed, thereby reducing the manufacturing yield.
Disclosure of Invention
The application provides a manufacturing method and a device of a fuse, which can solve the problem of lower manufacturing yield caused by the fact that the fuse provided in the related technology has a certain probability of being damaged by water pressure in the dicing process.
In one aspect, an embodiment of the present application provides a method for manufacturing a fuse, including:
forming a metal layer on the dielectric layer;
etching a first target area and a second target area to expose dielectric layers of the first target area and the second target area, forming a first groove in the first target area, and forming a second groove in the second target area;
forming a passivation layer on the metal layer and in the first trench and the second trench;
etching the first target region, the second target region and the third target region, wherein the first target region and the second target region are etched to the target depth of the dielectric layer, a third groove is formed in the first target region, a fourth groove is formed in the second target region, a fifth groove is formed in the third target region, a metal layer between the third groove and the fourth groove is exposed, and a metal layer at the bottom of the fifth groove is exposed;
forming protective layers on the surfaces of the passivation layer, the third groove, the fourth groove and the fifth groove;
and removing the protective layers at the bottoms of the third groove, the fourth groove and the fifth groove above the passivation layer, and reserving the protective layers on the side walls of the third groove, the fourth groove and the fifth groove.
Optionally, the protective layer includes an oxide and/or an oxynitride.
Optionally, forming a protective layer on the surfaces of the passivation layer, the third trench, the fourth trench and the fifth trench includes:
and depositing oxide and/or oxynitride on the surfaces of the passivation layer, the third groove, the fourth groove and the fifth groove to form the protective layer.
Optionally, depositing oxide and/or oxynitride on surfaces of the passivation layer, the third trench, the fourth trench and the fifth trench to form the protection layer includes:
the protective layer is formed by depositing oxide and/or oxynitride on surfaces of the passivation layer, the third trench, the fourth trench, and the fifth trench by a chemical vapor deposition (chemical vapor deposition, CVD) process.
Optionally, the oxide comprises silicon dioxide (SiO 2 )。
Optionally, the oxynitride comprises silicon oxynitride (SiON).
In another aspect, an embodiment of the present application provides a device, including:
a dielectric layer;
the metal layer is formed on the dielectric layer;
a passivation layer formed on the metal layer;
a third groove and a fourth groove are formed in the dielectric layer, the metal layer and the passivation layer, a fuse is formed in the metal layer between the third groove and the fourth groove, the top layer of the fuse is exposed, a fifth groove is formed in the passivation layer, and the metal layer at the bottom of the fifth groove is exposed;
and the side walls of the third groove, the fourth groove and the fifth groove are provided with protective layers.
Optionally, the protective layer includes an oxide and/or an oxynitride.
Optionally, the oxide comprises silicon dioxide.
Optionally, the nitrogen oxides include silicon oxynitride.
Optionally, the metal layer comprises copper and/or aluminum.
Optionally, the dielectric layer is an interlayer dielectric (inter layer dielectric, ILD) layer or a metal dielectric (inter metal dielectric, IMD) layer.
Optionally, the dielectric layer includes an oxide and/or an oxynitride.
Optionally, the passivation layer includes an oxide.
The technical scheme of the application at least comprises the following advantages:
through forming the protective layer on the side walls of the grooves on two sides of the fuse in the manufacturing process of the fuse, the probability that the fuse is damaged by water pressure in the subsequent scribing process is reduced, and the manufacturing yield is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic cross-sectional view of a fuse provided in the related art;
FIG. 2 is a flowchart of a method of manufacturing a fuse provided in one exemplary embodiment of the present application;
fig. 3 to 8 are flowcharts of manufacturing a fuse provided in an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Referring to fig. 2, a flowchart of a method for manufacturing a fuse according to an exemplary embodiment of the present application is shown, where the method may be applied to a manufacturing process of a device including the fuse, and the method includes:
in step 201, a metal layer is formed on a dielectric layer.
Referring to fig. 3, a schematic cross-sectional view of a metal layer formed on a dielectric layer is shown. As shown in fig. 3, a metal layer 320 is formed on dielectric layer 310. For example, the metal layer 320 may be deposited on the dielectric layer 310 by a physical vapor deposition (physical vapor deposition, PVD) process or an electroplating process. The dielectric layer 310 may be an ILD layer or an IMD layer.
Optionally, the constituent materials of dielectric layer 310 include oxides (e.g., silicon dioxide) and/or oxynitrides (e.g., silicon oxynitride); optionally, the constituent material of the metal layer 320 includes aluminum and/or copper.
Step 202, etching the first target area and the second target area to expose the dielectric layers of the first target area and the second target area, forming a first trench in the first target area, and forming a second trench in the second target area.
Referring to fig. 4, a schematic cross-sectional view of etching the first target region and the second target region to form a first trench and a second trench is shown. As shown in fig. 4, the first target area and the second target area are blank areas on two sides of the fuse, the first target area and the second target area to be etched can be defined through a photolithography process, the etching exposes the dielectric layer 310 under the first target area and the second target area, the first trench 301 is formed in the first target area, and the second trench 302 is formed in the second target area.
A passivation layer is formed on the metal layer and in the first trench and the second trench 203.
Referring to fig. 5, a schematic cross-sectional view after forming a passivation layer is shown. Optionally, the constituent material of passivation layer 330 includes an oxide (e.g., silicon dioxide). Illustratively, as shown in fig. 5, the passivation layer 330 may be formed by depositing an oxide in the surface of the metal layer 320, the first trench 301, and the second trench 302 by a CVD process, for example, a plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD) process.
And 204, etching the first target area, the second target area and the third target area, wherein the first target area and the second target area are etched to the target depth of the dielectric layer, a third groove is formed in the first target area, a fourth groove is formed in the second target area, a fifth groove is formed in the third target area, a metal layer between the third groove and the fourth groove is exposed, and a metal layer at the bottom of the fifth groove is exposed.
Referring to fig. 6, a schematic cross-sectional view of the first, second and third target regions after etching is shown. For example, a first target region, a second target region and a third target region to be etched may be defined by a photolithography process, the passivation layer 330 in the first trench 301 and the second trench 302 is etched and removed, and the first trench 301 and the second trench 302 are respectively etched down to a target depth of the dielectric layer 310, and a third trench 303 and a fourth trench 304 are respectively formed, wherein the metal layer 320 between the third trench 303 and the fourth trench 304 is exposed, and the metal layer 320 between the third trench 303 and the fourth trench 304 forms a fuse (as shown by a dotted line in fig. 6), and simultaneously, the passivation layer 330 in the fifth target region is etched and removed, so that the metal layer 320 at the bottom of the region is exposed to form a fifth trench 305.
In step 205, a protective layer is formed on the surfaces of the passivation layer, the third trench, the fourth trench, and the fifth trench.
Referring to fig. 7, a schematic cross-sectional view of the resulting protective layer is shown. Optionally, the protective layer 340 may be comprised of materials including oxides (e.g., silicon dioxide) and/or oxynitrides (e.g., silicon oxynitride). Illustratively, as shown in fig. 7, a protective layer 340 may be formed by depositing oxide and/or oxynitride on the surfaces of the passivation layer 330, the third trench 303, the fourth trench 304, and the fifth trench 305. Alternatively, in embodiments of the present application, the process of depositing oxide and/or oxynitride to form protective layer 340 may be a CVD process (e.g., a PECVD process).
And 206, removing the protective layers at the bottoms of the third groove, the fourth groove and the fifth groove above the passivation layer, and reserving the protective layers on the side walls of the third groove, the fourth groove and the fifth groove.
Referring to fig. 8, a schematic cross-sectional view of the passivation layer above the passivation layer is shown after removal of the protective layer at the bottom of the third, fourth and fifth trenches. As shown in fig. 8, the protective layer 340 at the bottom of the third trench 303, the fourth trench 304, and the fifth trench 305 is etched away over the passivation layer 330.
In summary, in the embodiment of the present application, the protective layer is formed on the side wall of the groove on both sides of the fuse in the manufacturing process of the fuse, so that the probability of the fuse being damaged by water pressure in the subsequent dicing process is reduced, and the manufacturing yield is improved.
Referring to fig. 8, which shows a schematic cross-sectional view of a device provided by an exemplary embodiment of the present application, the device may be manufactured by the above-described embodiments, the device includes:
a dielectric layer 310;
a metal layer 320 formed on the dielectric layer 310;
a passivation layer 330 formed on the metal layer 320;
the dielectric layer 310, the metal layer 320 and the passivation layer 330 are formed with a third trench 303 and a fourth trench 304, the metal layer 320 between the third trench 303 and the fourth trench 304 forms a fuse (as shown by a dotted line in fig. 8), the top layer of the fuse is exposed, the passivation layer 330 is formed with a fifth trench 305, the metal layer 320 at the bottom of the fifth trench 305 is exposed, and the sidewalls of the third trench 303, the fourth trench 304 and the fifth trench 305 are formed with a protection layer 340.
Optionally, the protective layer 340 includes an oxide and/or oxynitride; optionally, the oxide in the protective layer 340 includes silicon dioxide; optionally, the oxynitride in the protective layer 340 includes silicon oxynitride.
Optionally, the metal layer 320 includes copper and/or aluminum.
Optionally, dielectric layer 310 is an ILD layer or an IMD layer; optionally, dielectric layer 310 includes an oxide and/or oxynitride; optionally, the oxide in dielectric layer 310 includes silicon dioxide; optionally, the oxynitride in dielectric layer 310 comprises silicon oxynitride.
Optionally, passivation layer 340 includes an oxide; optionally, the oxide in passivation layer 340 includes silicon dioxide.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (14)

1. A method of manufacturing a fuse, comprising:
forming a metal layer on the dielectric layer;
etching a first target area and a second target area to expose dielectric layers of the first target area and the second target area, forming a first groove in the first target area, and forming a second groove in the second target area;
forming a passivation layer on the metal layer and in the first trench and the second trench;
etching the first target region, the second target region and the third target region, wherein the first target region and the second target region are etched to the target depth of the dielectric layer, a third groove is formed in the first target region, a fourth groove is formed in the second target region, a fifth groove is formed in the third target region, a metal layer between the third groove and the fourth groove is exposed, and a metal layer at the bottom of the fifth groove is exposed;
forming protective layers on the surfaces of the passivation layer, the third groove, the fourth groove and the fifth groove;
and removing the protective layers at the bottoms of the third groove, the fourth groove and the fifth groove above the passivation layer, and reserving the protective layers on the side walls of the third groove, the fourth groove and the fifth groove.
2. The method of claim 1, wherein the protective layer comprises an oxide and/or oxynitride.
3. The method of claim 2, wherein forming a protective layer on surfaces of the passivation layer, the third trench, the fourth trench, and the fifth trench comprises:
and depositing oxide and/or oxynitride on the surfaces of the passivation layer, the third groove, the fourth groove and the fifth groove to form the protective layer.
4. The method of claim 3, wherein depositing oxide and/or oxynitride on surfaces of the passivation layer, the third trench, the fourth trench, and the fifth trench to form the protective layer comprises:
and depositing oxide and/or oxynitride on the surfaces of the passivation layer, the third groove, the fourth groove and the fifth groove through a CVD process to form the protective layer.
5. The method of claim 4, wherein the oxide comprises silicon dioxide.
6. The method of claim 4, wherein the nitrogen oxides comprise silicon oxynitride.
7. A device, comprising:
a dielectric layer;
the metal layer is formed on the dielectric layer;
a passivation layer formed on the metal layer;
a third groove and a fourth groove are formed in the dielectric layer, the metal layer and the passivation layer, a fuse is formed on the metal layer between the third groove and the fourth groove, the metal layer between the third groove and the fourth groove is exposed, a fifth groove is formed in the passivation layer, and the metal layer at the bottom of the fifth groove is exposed;
and the side walls of the third groove, the fourth groove and the fifth groove are provided with protective layers.
8. The device of claim 7, wherein the protective layer comprises an oxide and/or oxynitride.
9. The device of claim 8, wherein the oxide comprises silicon dioxide.
10. The device of claim 8, wherein the oxynitride comprises silicon oxynitride.
11. A device according to any of claims 7 to 10, characterized in that the metal layer comprises copper and/or aluminium.
12. The device of any of claims 7 to 10, wherein the dielectric layer is an ILD layer or an IMD layer.
13. The device of claim 12, wherein the dielectric layer comprises an oxide and/or oxynitride.
14. A device according to any of claims 7 to 10, wherein the passivation layer comprises an oxide.
CN202010607902.7A 2020-06-30 2020-06-30 Method and device for manufacturing fuse Active CN111785680B (en)

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CN111785680B true CN111785680B (en) 2024-02-06

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201485A (en) * 1999-07-06 2007-08-09 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its manufacturing method
CN111128770A (en) * 2019-12-16 2020-05-08 华虹半导体(无锡)有限公司 Method for forming aluminum pad and device containing aluminum pad

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101586270B1 (en) * 2009-02-04 2016-01-19 삼성전자주식회사 Semiconductor device including fuse

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201485A (en) * 1999-07-06 2007-08-09 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its manufacturing method
CN111128770A (en) * 2019-12-16 2020-05-08 华虹半导体(无锡)有限公司 Method for forming aluminum pad and device containing aluminum pad

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