CN112420672A - Method for forming photoetching alignment pattern in back-end process - Google Patents
Method for forming photoetching alignment pattern in back-end process Download PDFInfo
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- CN112420672A CN112420672A CN202011295925.5A CN202011295925A CN112420672A CN 112420672 A CN112420672 A CN 112420672A CN 202011295925 A CN202011295925 A CN 202011295925A CN 112420672 A CN112420672 A CN 112420672A
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- dielectric layer
- layer
- barrier layer
- groove
- metal layer
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000001259 photo etching Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 239000006227 byproduct Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000004380 ashing Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005240 physical vapour deposition Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a method for forming a photoetching alignment pattern in a back-end procedure, which comprises the following steps: carrying out planarization treatment through a CMP process, and removing a metal layer with a preset depth, wherein the metal layer is formed on a barrier layer, the barrier layer is formed on the surfaces of a dielectric layer and a groove, the dielectric layer is formed on a substrate, the groove is formed in the dielectric layer, and the groove corresponds to an alignment pattern in a photoetching process; ashing treatment is carried out through a photoresist remover to remove byproducts generated in the planarization treatment process; and etching to remove the dielectric layer and the barrier layer outside the trench. According to the method, by-products in the CMP process are removed by ashing, so that the problem that the subsequent photoetching process is influenced due to the reaction by-products in the groove in the related technology is solved, and the photoetching alignment degree in the back-end procedure is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for forming an alignment mark in back end of line (BEOL) processing.
Background
In the back-end process of semiconductor manufacturing, a through hole of a metal connection line is usually formed in a dielectric layer by etching, a first metal layer is filled, the first metal layer is planarized, the metal layer in the through hole forms the metal connection line, a second metal layer is formed, and interconnection of an upper metal layer and a lower metal layer is realized. Wherein, the photoetching alignment pattern and the metal connecting line are formed in the same process.
Referring to fig. 1, a cross-sectional view of a back-end process provided in the related art after planarization by a Chemical Mechanical Polishing (CMP) process is shown. As shown in fig. 1, a dielectric layer 120 is formed on a substrate 110, a trench 101 is formed in the dielectric layer 120, the trench 101 is used as a photolithography alignment pattern in a subsequent process, and after a metal layer 130 is formed, planarization processing is performed through a CMP process, and a byproduct 200 generated in polishing is trapped in the trench 101 with a high probability in the planarization process due to the deep trench 101, thereby reducing the photolithography alignment accuracy in the subsequent process.
Disclosure of Invention
The application provides a method for forming a photoetching alignment pattern in a back-end procedure, which can solve the problem of poor photoetching alignment accuracy caused by the fact that a grinding byproduct is clamped in a groove of the photoetching alignment pattern with high probability in the method for forming the photoetching alignment pattern in the back-end procedure provided by the related technology.
In one aspect, an embodiment of the present application provides a method for forming a lithographic alignment pattern in a back-end process, including:
carrying out planarization treatment through a CMP (chemical mechanical polishing) process to remove a metal layer with a preset depth, wherein the metal layer is formed on a barrier layer, the barrier layer is formed on the surfaces of a dielectric layer and a groove, the dielectric layer is formed on a substrate, the groove is formed in the dielectric layer, and the groove corresponds to an alignment pattern in a photoetching process;
ashing treatment is carried out through a photoresist remover to remove byproducts generated in the planarization treatment process;
and etching to remove the dielectric layer and the barrier layer outside the groove.
Optionally, before the planarization by the CMP process, the method further includes:
forming the dielectric layer on the substrate;
forming the groove in the dielectric layer;
and sequentially forming the barrier layer and the metal layer.
Optionally, the dielectric layer includes silicon dioxide (SiO)2)。
Optionally, the forming the dielectric layer on the substrate includes:
and depositing silicon dioxide on the substrate by a Chemical Vapor Deposition (CVD) process to form the dielectric layer.
Optionally, the barrier layer comprises titanium (Ti) and/or titanium nitride (TiN).
Optionally, the metal layer comprises tungsten (W).
Optionally, the sequentially forming the barrier layer and the metal layer includes:
depositing titanium and/or titanium nitride on the dielectric layer and the surface of the groove by a Physical Vapor Deposition (PVD) process to form the barrier layer;
and depositing tungsten on the surface of the barrier layer by a PVD process to form the metal layer.
The technical scheme at least comprises the following advantages:
after a barrier layer and a metal layer are sequentially formed on the surface of a groove and a dielectric layer of a rear-end structure, planarization treatment is carried out through a CMP process, the metal layer with a certain thickness is reserved, ashing treatment is carried out through a photoresist remover to remove byproducts generated in the planarization treatment process, the residual barrier layer and the metal layer outside the groove are removed through an etching process, and the byproducts in the CMP process are removed through ashing, so that the problem that the subsequent photoetching process is influenced due to the reaction byproducts in the groove in the related technology is solved, and the photoetching alignment degree in the rear-end process is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of a related art back-end process after planarization by a CMP process;
FIG. 2 is a flow chart of a method for forming a lithographic alignment pattern in a back-end-of-line process as provided by an exemplary embodiment of the present application;
fig. 3 to 6 are schematic diagrams illustrating the formation of a lithography alignment pattern in a back-end-of-line process according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flowchart of a method for forming a lithographic alignment pattern in a back-end-of-line process according to an exemplary embodiment of the present application is shown, the method comprising:
Referring to fig. 3, a schematic cross-sectional view before a planarization process is performed is shown; referring to fig. 4, a cross-sectional view after a planarization process is performed is shown.
As shown in fig. 3 and 4, a dielectric layer 320 is formed on a substrate 310, a trench 301 is formed in the dielectric layer 320, a barrier layer 331 and a metal layer 332 are sequentially formed on the surfaces of the dielectric layer 320 and the trench 301, the metal layer 332 is thinned after planarization processing by a CMP process, the metal layer 332 outside the trench 301 is not completely removed, and a by-product 200 generated during the planarization processing is stuck in the trench 301.
The dielectric layer 320 is a low-k material (a material with a k less than 4, such as silicon dioxide), the metal layer 332 may include tungsten, and the barrier layer 331 may include titanium and/or titanium nitride.
Optionally, before step 201, the method further includes: forming a dielectric layer 320 on a substrate 310; forming a trench 301 in a dielectric layer 320; a barrier layer 331 and a metal layer 332 are sequentially formed. Wherein:
"forming dielectric layer 320 on substrate 310" includes, but is not limited to: a dielectric layer 320 is formed by depositing silicon dioxide on the substrate 310 by a CVD process.
"forming trenches 301 in dielectric layer 320" includes, but is not limited to: covering photoresist on the dielectric layer 320 in other regions except the target region by a photoetching process, wherein the target region is a region corresponding to the groove 301; etching is carried out until the substrate 310 of the target area is exposed; and removing the photoresist.
"sequentially forming barrier layer 331 and metal layer 332" includes, but is not limited to: depositing titanium and/or titanium nitride on the surfaces of the dielectric layer 320 and the trench 301 by a PVD (physical vapor deposition) process to form a barrier layer 331; a metal layer 332 is formed by depositing tungsten on the surface of the barrier layer 331 through a PVD process. The "depositing titanium and/or titanium nitride on the dielectric layer 320 and the surface of the trench 301 by PVD process to form the barrier layer 331" may be any of the following steps a, b, and c: a. depositing titanium on the dielectric layer 320 and the surface of the groove 301 by a PVD process to form a barrier layer 331; or, depositing titanium nitride on the dielectric layer 320 and the surface of the trench 301 by a PVD process to form a barrier layer 331; alternatively, the barrier layer 331 is formed by sequentially depositing titanium and titanium nitride on the dielectric layer 320 and the surface of the trench 301 through a PVD process.
In step 202, ashing is performed by a photoresist stripper to remove byproducts generated during the planarization process.
Referring to fig. 5, a schematic cross-sectional view after the ashing process is performed is shown. As shown in fig. 5, by-products 200 generated during the planarization process are removed after the ashing process.
And step 203, etching is carried out, and the dielectric layer and the barrier layer outside the groove are removed.
Referring to fig. 6, a schematic cross-sectional view of the etching is shown. As shown in fig. 6, after etching, the barrier layer 331 and the metal layer 332 outside the trench 301 are removed, and the barrier layer 331 and the metal layer 332 inside the trench 301 form an alignment pattern (shown by a dotted line in fig. 6).
In summary, in the embodiment of the present application, after the barrier layer and the metal layer are sequentially formed on the surface of the trench and the dielectric layer of the back-end structure, planarization is performed by a CMP process, the metal layer with a certain thickness is retained, ashing is performed by a photoresist remover to remove byproducts generated during the planarization process, the remaining barrier layer and the metal layer outside the trench are removed by an etching process, and the byproducts in the CMP process are removed by ashing, so that the problem that a subsequent photolithography process is affected by reaction byproducts existing in the trench in the related art is solved, and the photolithography alignment degree in the back-end process is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A method for forming a lithographic alignment pattern in a back-end process, comprising:
carrying out planarization treatment through a CMP (chemical mechanical polishing) process to remove a metal layer with a preset depth, wherein the metal layer is formed on a barrier layer, the barrier layer is formed on the surfaces of a dielectric layer and a groove, the dielectric layer is formed on a substrate, the groove is formed in the dielectric layer, and the groove corresponds to an alignment pattern in a photoetching process;
ashing treatment is carried out through a photoresist remover to remove byproducts generated in the planarization treatment process;
and etching to remove the dielectric layer and the barrier layer outside the groove.
2. The method of claim 1, wherein prior to the planarizing by the CMP process, further comprising:
forming the dielectric layer on the substrate;
forming the groove in the dielectric layer;
and sequentially forming the barrier layer and the metal layer.
3. The method of claim 2, wherein the dielectric layer comprises silicon dioxide.
4. The method of claim 3, wherein forming the dielectric layer on the substrate comprises:
and depositing silicon dioxide on the substrate by a CVD (chemical vapor deposition) process to form the dielectric layer.
5. The method of claim 2, wherein the barrier layer comprises titanium and/or titanium nitride.
6. The method of claim 5, wherein the metal layer comprises tungsten.
7. The method of claim 6, wherein said sequentially forming said barrier layer and said metal layer comprises:
depositing titanium and/or titanium nitride on the surfaces of the dielectric layer and the groove by a PVD (physical vapor deposition) process to form the barrier layer;
and depositing tungsten on the surface of the barrier layer by a PVD process to form the metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011295925.5A CN112420672A (en) | 2020-11-18 | 2020-11-18 | Method for forming photoetching alignment pattern in back-end process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011295925.5A CN112420672A (en) | 2020-11-18 | 2020-11-18 | Method for forming photoetching alignment pattern in back-end process |
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| Publication Number | Publication Date |
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| CN112420672A true CN112420672A (en) | 2021-02-26 |
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| CN202011295925.5A Pending CN112420672A (en) | 2020-11-18 | 2020-11-18 | Method for forming photoetching alignment pattern in back-end process |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000055794A (en) * | 1999-02-10 | 2000-09-15 | 윤종용 | Method of removing byproduct of chemical polishing process |
| US20020028528A1 (en) * | 2000-09-01 | 2002-03-07 | Shiro Ohtaka | Alignment marks and method of forming the same |
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2020
- 2020-11-18 CN CN202011295925.5A patent/CN112420672A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000055794A (en) * | 1999-02-10 | 2000-09-15 | 윤종용 | Method of removing byproduct of chemical polishing process |
| US20020028528A1 (en) * | 2000-09-01 | 2002-03-07 | Shiro Ohtaka | Alignment marks and method of forming the same |
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Application publication date: 20210226 |
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