CN115346910A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN115346910A CN115346910A CN202110520698.XA CN202110520698A CN115346910A CN 115346910 A CN115346910 A CN 115346910A CN 202110520698 A CN202110520698 A CN 202110520698A CN 115346910 A CN115346910 A CN 115346910A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
The invention provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: forming a shallow trench isolation structure with a recess on the surface in the peripheral area of the substrate; forming etching buffer layers on the array region and the peripheral region of the substrate, wherein the etching buffer layers fill the depressions; and removing part of the etching buffer layer of the peripheral region to expose the surface of the peripheral region, wherein the remained etching buffer layer is arranged in the recess. According to the manufacturing method of the semiconductor structure, the etching buffer layer is formed on the concave surface of the shallow trench isolation structure. When multi-step wet etching is subsequently carried out, the etching buffer layer can prevent the isolation medium in the shallow trench isolation structure from being excessively lost, and the problem of grid leakage is avoided.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor structure and a manufacturing method thereof.
Background
Shallow Trench Isolation (STI) is widely used in logic and memory chips to isolate adjacent device structures, especially adjacent active regions. In the process of forming the shallow trench isolation structure, a shallow trench is usually formed first, and then an isolation medium is filled into the trench. The existing isolation dielectric mostly adopts common silicon dioxide and silicon nitride.
During the fabrication of memory devices, there are several wet etching steps, such as in the high-k metal gate (HKMG) technique. Multiple wet etching steps may result in excessive silicon dioxide loss in the shallow trench isolation structure, resulting in gate leakage problems. At the same time, silicon dioxide impurities also diffuse into the gate, contaminating it.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem that silicon dioxide loss of a shallow trench isolation structure is excessive due to a plurality of wet etching steps.
The manufacturing method of the semiconductor structure of the embodiment of the invention comprises the following steps:
forming a shallow trench isolation structure with a recess on the surface in the peripheral area of the substrate;
forming etching buffer layers on the array region and the peripheral region of the substrate, wherein the etching buffer layers fill the depressions; and
and removing part of the etching buffer layer of the peripheral area to expose the surface of the peripheral area, wherein the remained etching buffer layer is arranged in the recess.
According to some embodiments of the invention, after removing a portion of the etch buffer layer in the peripheral region, the method further comprises:
an HKMG process is performed on the peripheral region.
According to some embodiments of the invention, the etch buffer layer comprises a first barrier layer and an insulating layer;
a step of forming an etch buffer layer on the array region and the peripheral region of the substrate, comprising:
forming a first barrier layer on the array region and the peripheral region of the substrate, wherein the first barrier layer is matched with the recess;
and forming the insulating layer on the surface of the first barrier layer, wherein part of the insulating layer is formed in the recess.
According to some embodiments of the invention, the first barrier layer comprises silicon nitride and the insulating layer comprises silicon oxide.
According to some embodiments of the invention, before forming the first barrier layer on the substrate, the method further comprises:
a second barrier layer is formed over the array region.
According to some embodiments of the present invention, removing a portion of the etching buffer layer in the peripheral region to expose a surface of the peripheral region, and the remaining etching buffer layer being disposed in the recess includes:
and sequentially removing part of the insulating layer and part of the first barrier layer by adopting a CMP (chemical mechanical polishing) process so as to expose the surfaces of the second barrier layer and the peripheral region, and filling the recess with the remained first barrier layer and the remained insulating layer.
According to some embodiments of the invention, the thickness of the first barrier layer remaining is less than or equal to 80nm.
According to some embodiments of the present invention, removing a portion of the etching buffer layer in the peripheral region to expose a surface of the peripheral region, and the remaining etching buffer layer being disposed in the recess includes:
removing part of the insulating layer and part of the first barrier layer on the peripheral area to expose the surface of the peripheral area, wherein the remained insulating layer and the remained first barrier layer fill the recess;
and removing the insulating layer on the array region, wherein the first barrier layer covers the array region.
According to some embodiments of the present invention, the insulating layer on the array region is removed, and the remaining insulating layer on the peripheral region is removed at the same time.
According to some embodiments of the invention, removing a portion of the insulating layer and a portion of the first barrier layer on the peripheral region to expose a surface of the peripheral region comprises:
forming a photoresist layer on the insulating layer of the array region and the peripheral region;
removing the photoresist layer on the insulating layer in the peripheral region;
removing a part of the insulating layer on the first barrier layer in the peripheral area by taking the photoresist layer on the array area as a mask;
removing the photoresist layer of the array region;
removing the first barrier layer on the surface of the substrate on the peripheral area to expose the surface of the peripheral area, wherein the first barrier layer is remained on the bottom wall surface of the recess and is provided with a sub-recess matched with the recess, and the concave curvature of the sub-recess is smaller than that of the recess;
and removing the insulating layer of the array region and the remaining insulating layer of the peripheral region.
According to some embodiments of the invention, removing a portion of the insulating layer and a portion of the first barrier layer on the peripheral region to expose a surface of the peripheral region comprises:
forming a photoresist layer on the insulating layer on the array region and the peripheral region;
removing the photoresist layer on the insulating layer in the peripheral region;
removing a part of the insulating layer on the first barrier layer of the peripheral region and the first barrier layer on the surface of the substrate by taking the photoresist layer on the array region as a mask so as to expose the surface of the peripheral region, wherein the remained first barrier layer is positioned on the bottom wall surface of the recess and is provided with a sub-recess matched with the recess, and the concave curvature of the sub-recess is smaller than that of the recess;
removing the photoresist layer of the array region;
and removing the insulating layer of the array region and the remaining insulating layer of the peripheral region.
The semiconductor structure of the embodiment of the invention comprises:
a substrate;
the shallow trench isolation structure is arranged in the peripheral area of the substrate, and a recess is formed in the surface of the shallow trench isolation structure; and
and the etching buffer layer is arranged in the recess.
According to some embodiments of the invention, the etch buffer layer fills the recess.
According to some embodiments of the invention, the etch buffer layer comprises a first barrier layer and an insulating layer; the first barrier layer is formed on the surface of the bottom wall of the recess, and the insulating layer is formed on the surface of the first barrier layer.
According to some embodiments of the invention, the first barrier layer comprises silicon nitride and the insulating layer comprises silicon oxide.
According to some embodiments of the invention, the first barrier layer and the insulating layer fill the recess.
According to some embodiments of the invention, the first barrier layer has a thickness of less than or equal to 80nm.
According to some embodiments of the present invention, the etching buffer layer includes a first barrier layer formed on the bottom wall surface of the recess and having sub-recesses adapted to the recess, and the concave curvature of the sub-recesses is smaller than that of the recess.
According to some embodiments of the invention, the first barrier layer comprises silicon nitride.
One embodiment of the above invention has the following advantages or benefits:
according to the manufacturing method of the semiconductor structure, the etching buffer layer is formed on the concave surface of the shallow trench isolation structure. When multi-step wet etching is subsequently carried out, the etching buffer layer can prevent the isolation medium in the shallow trench isolation structure from being excessively lost, and the problem of grid leakage is avoided.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Shown in fig. 1 is a top view of a semiconductor structure of an embodiment of the present invention.
Fig. 2A to 5B are sectional views showing process stages ofbase:Sub>A method of manufacturingbase:Sub>A semiconductor structure according tobase:Sub>A first embodiment of the present invention, in whichbase:Sub>A isbase:Sub>A sectional view ofbase:Sub>A-base:Sub>A before formingbase:Sub>A bit line in fig. 1, and B isbase:Sub>A sectional view of B-B before formingbase:Sub>A bit line in fig. 1.
Fig. 6A to 9B are sectional views showing process stages ofbase:Sub>A method of manufacturingbase:Sub>A semiconductor structure according tobase:Sub>A second embodiment of the present invention, in whichbase:Sub>A isbase:Sub>A sectional view ofbase:Sub>A-base:Sub>A before formingbase:Sub>A bit line in fig. 1, and B isbase:Sub>A sectional view of B-B before formingbase:Sub>A bit line in fig. 1.
Fig. 10A to 13B are sectional views showing process stages ofbase:Sub>A method of manufacturingbase:Sub>A semiconductor structure according tobase:Sub>A third embodiment of the present invention, in whichbase:Sub>A isbase:Sub>A sectional view ofbase:Sub>A-base:Sub>A before formingbase:Sub>A bit line in fig. 1, and B isbase:Sub>A sectional view of B-B before formingbase:Sub>A bit line in fig. 1.
Wherein the reference numerals are as follows:
100. substrate 110 and shallow trench isolation structure
111. Recess 200, etch buffer layer
210. First barrier layer 211, remaining first barrier layer
220. Insulating layer 221, remaining insulating layer
2211. Sub-recesses 310, second barrier layer
320. Photoresist layer 410, active region
420. Bit line 430, word line
AA. Array area PA and peripheral area
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a detailed description thereof will be omitted.
As shown in fig. 1, fig. 1 is a top view of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure includes an array area AA in which an active region 410, a bit line 420 and a word line 430 are disposed, and a peripheral area PA in which peripheral circuits are disposed.
As shown in fig. 2A to 12B, the method for manufacturing a semiconductor structure according to an embodiment of the present invention includes: forming a shallow trench isolation structure 110 with a recess 111 on the surface in the peripheral area PA of the substrate 100; forming an etching buffer layer 200 on the array area AA and the peripheral area PA of the substrate 100, the etching buffer layer 200 filling the recess 111; a portion of the etching buffer layer 200 in the peripheral area PA is removed to expose the surface of the peripheral area PA, and the remaining etching buffer layer 200 is disposed in the recess 111.
In the method for manufacturing a semiconductor structure according to the embodiment of the invention, the etching buffer layer 200 is formed on the surface of the recess 111 of the shallow trench isolation structure 110. When multi-step wet etching is performed subsequently, the etching buffer layer 200 can prevent the isolation dielectric loss in the shallow trench isolation structure 110 from being excessive, and avoid the problem of gate leakage.
Three embodiments of the method for manufacturing a semiconductor structure according to the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
First embodiment
As shown in fig. 2A and 2B, a shallow trench isolation structure 110 having a recess 111 on the surface is formed in the peripheral area PA of the substrate 100. It should be noted that, the shallow trench isolation structure 110 formed in the peripheral region PA may be formed by a process well known in the art, and will not be described in detail herein.
As an example, the material of the substrate 100 may be a silicon material, a germanium material or other commercially available materials, the most widely used substrate material in the semiconductor industry is silicon, and the production process of the silicon substrate is very mature, so the silicon substrate will be mainly used as an example in this embodiment, but not limited thereto.
It is understood that, when performing a Peripheral Nitride Removal (PNR) process, the barrier layer on the peripheral area PA of the substrate 100 needs to be removed, and the second barrier layer 310 on the array area AA remains. When the barrier layer on the peripheral area PA is removed, the wet removal process may also remove a portion of the isolation medium in the shallow trench isolation structure 110, that is, a recess 111 may be formed on the surface of the shallow trench isolation structure 110. If a multi-step wet etching process is continued in the subsequent process, the loss of the isolation medium is excessive, and the problem of gate leakage occurs.
As shown in fig. 3A and 3B, the first barrier layer 210 is formed on the array area AA and the peripheral area PA of the substrate 100, the first barrier layer 210 on the array area AA covers the second barrier layer 310, and the first barrier layer 210 on the peripheral area PA is adapted to the recess 111.
As an example, first barrier layer 210 may include silicon nitride. Since the silicon nitride is hard and not easy to be etched, the first barrier layer 210 is formed in the peripheral region PA, and the first barrier layer 210 is designed to be matched with the recess 111 of the shallow trench isolation structure 110, so that the first barrier layer 210 can effectively prevent the isolation medium in the shallow trench isolation structure 110 from being removed by a subsequent multi-step wet etching process.
As an example, the thickness of the first barrier layer 210 may be less than or equal to 80nm, for example, 20nm, 40nm, and 60nm. Of course, the present invention should not be limited thereto, and those skilled in the art can make corresponding adjustments according to actual design requirements.
Further, the step of forming first barrier layer 210 may employ an atomic layer deposition technique, so that the thickness of first barrier layer 210 may be precisely controlled.
As shown in fig. 3A, the materials of the first barrier layer 210 and the second barrier layer 310 may both include silicon nitride.
As shown in fig. 4A and 4B, an insulating layer 220 is formed on the surface of the first barrier layer 210, wherein, in the peripheral area PA, a part of the insulating layer 220 is formed in the recess 111.
As an example, the material of the insulating layer 220 may include silicon oxide. On one hand, silicon oxide can be used as an isolation material, and the remaining insulating layer 221 is filled in the recess 111, which can achieve an isolation effect. On the other hand, the hardness of the silicon oxide is smaller, and the fluidity is better, so that the insulating layer 220 can well fill the recess 111, and the process difficulty is reduced.
As shown in fig. 5A and 5B, a Chemical Mechanical Polishing (CMP) process is used to sequentially remove a portion of the insulating layer 220 and a portion of the first barrier layer 210 to expose the surfaces of the second barrier layer 310 and the peripheral region PA, and the remaining first barrier layer 211 and the remaining insulating layer 221 fill the recess 111.
In this step, the insulating layer 220 and the first barrier layer 210 of the array area AA are removed using a CMP process to expose the second barrier layer 310. In this way, the semiconductor structure shown in fig. 2A, i.e., the structure after the PNR process is completed, can be restored. At the same time, the first barrier layer 210 and a portion of the insulating layer 220 on the surface of the peripheral area PA are also removed by the CMP process, so that the remaining first barrier layer 211 and the remaining insulating layer 221 fill the recess 111. When the subsequent multi-step wet etching process is performed, the remaining first barrier layer 211 and the remaining insulating layer 221 can effectively prevent the loss of the isolation medium in the shallow trench isolation structure 110.
Although not shown in the drawings, it is understood that after removing a portion of the etching buffer layer 200 (i.e., a portion of the first barrier layer 210 and a portion of the insulating layer 220) in the peripheral area PA, the method of the embodiment of the present invention further includes: a high-k metal gate (HKMG) process is performed on the peripheral area PA.
Second embodiment
As shown in fig. 6A to 9B, removing a portion of the etching buffer layer 200 in the peripheral area PA to expose the surface of the peripheral area PA, and disposing the remaining etching buffer layer 200 in the recess 111 includes: removing part of the insulating layer 220 and part of the first barrier layer 210 on the peripheral area PA to expose the surface of the peripheral area PA, and filling the recess 111 with the remaining insulating layer 221 and the remaining first barrier layer 211; the insulating layer 220 on the array area AA is removed, and the first barrier layer 210 covers the array area AA.
In this embodiment, the PNR process is not performed, but the etching buffer layer 200 is directly formed on the array region AA and the peripheral region PA of the substrate 100, and a part of the etching buffer layer 200 is disposed in the recess 111 of the shallow trench isolation structure 110. Specifically, the method comprises the following steps:
as shown in fig. 6A and 6B, a first blocking layer 210 and an insulating layer 220 are sequentially formed on the array region AA and the peripheral region PA of the substrate 100 from bottom to top, and the first blocking layer 210 is adapted to the recess 111 of the shallow trench isolation structure 110.
As an example, first barrier layer 210 may include silicon nitride. The insulating layer 220 may include silicon oxide.
A photoresist layer 320 is formed on the insulating layer 220 of the array area AA and the peripheral area PA, and the photoresist layer 320 on the insulating layer 220 of the peripheral area PA is removed.
As shown in fig. 7A and 7B, a portion of the insulating layer 220 on the first barrier layer 210 in the peripheral area PA is removed by using the photoresist layer 320 on the array area AA as a mask.
As shown in fig. 8A and 8B, the photoresist layer 320 of the array area AA is removed. The first barrier layer 210 on the surface of the substrate 100 on the peripheral area PA is removed to expose the surface of the peripheral area PA, and the remaining first barrier layer 211 is located on the bottom wall surface of the recess 111 and has a sub-recess 2211 matching with the recess 111, and the concave curvature of the sub-recess 2211 is smaller than that of the recess 111.
As shown in fig. 9A and 9B, the insulating layer 220 on the array area AA is removed together with the remaining insulating layer 220 on the peripheral area PA.
As shown in fig. 9B, in the present embodiment, the surface of the recess 111 of the shallow trench isolation structure 110 has a first barrier layer 210. Since silicon nitride is hard and not easy to be etched, the first barrier layer 210 can effectively block the isolation medium in the shallow trench isolation structure 110 from being removed by a subsequent multi-step wet etching process by forming the first barrier layer 210 in the peripheral region PA.
In an example embodiment, the thickness of the first barrier layer 210 may be less than or equal to 80nm, for example, 20nm, 40nm, and 60nm. Of course, the present invention should not be limited thereto, and those skilled in the art can make corresponding adjustments according to actual design requirements.
It is worth mentioning that the thickness of the first barrier layer 210 in the second embodiment may be greater than or equal to the thickness of the first barrier layer 210 in the first embodiment.
It should be noted that the concave curvature of the concave 111 of the shallow trench isolation in the second embodiment is different from that of the concave 111 of the shallow trench isolation structure 110 in the first embodiment. Specifically, since the PNR process is performed before the etching buffer layer 200 is formed in the first embodiment, the PNR process may cause a portion of the isolation medium in the sti structure 110 to be further lost, so that the concavity of the recess 111 formed thereby is relatively large. Referring to the second embodiment, in the second embodiment, the PNR process is not performed, but the etching buffer layer 200 is directly formed on the array region AA and the peripheral region PA of the substrate 100, so that the recess 111 is formed only by the loss caused by the process steps before the PNR process, and the concave curvature of the recess 111 is smaller than that of the recess 111 in the first embodiment.
Third embodiment
As shown in fig. 10A to fig. 13B, in the present embodiment, the PNR process is not performed, but the etching buffer layer 200 is directly formed on the array region AA and the peripheral region PA of the substrate 100, and a part of the etching buffer layer 200 is disposed in the recess 111 of the shallow trench isolation structure 110.
As shown in fig. 10A and 10B, a first blocking layer 210 and an insulating layer 220 are sequentially formed on the array region AA and the peripheral region PA of the substrate 100 from bottom to top, and the first blocking layer 210 is adapted to the recess 111 of the shallow trench isolation structure 110.
As an example, first barrier layer 210 may include silicon nitride. The insulating layer 220 may include silicon oxide.
As shown in fig. 11A and 11B, a photoresist layer 320 is formed on the insulating layer 220 on the array area AA and the peripheral area PA. The photoresist layer 320 on the insulating layer 220 of the peripheral area PA is removed. Using the photoresist layer 320 on the array area AA as a mask, removing a portion of the insulating layer 220 on the first blocking layer 210 of the peripheral area PA and the first blocking layer 210 on the surface of the substrate 100 to expose the surface of the peripheral area PA, leaving the first blocking layer 211 on the bottom wall surface of the recess 111 and having a sub-recess 2211 adapted to the recess 111, where the concave curvature of the sub-recess 2211 is smaller than that of the recess 111, and the remaining insulating layer 221 fills the sub-recess 2211.
As shown in fig. 12A and 12B, the photoresist layer 320 of the array area AA is removed.
As shown in fig. 13A and 13B, the insulating layer 220 of the array area AA and the remaining insulating layer 221 of the peripheral area PA are removed.
Since the first blocking layer 210 is not easily etched, the first blocking layer 210 can effectively block the isolation dielectric in the shallow trench isolation structure 110 from being removed by a subsequent multi-step wet etching process by forming the first blocking layer 210 in the peripheral area PA.
In an example embodiment, the thickness of the first barrier layer 210 may be less than or equal to 80nm, for example, 20nm, 40nm, and 60nm. Of course, the present invention should not be limited thereto, and those skilled in the art can make corresponding adjustments according to actual design requirements.
It is worth mentioning that the thickness of the first barrier layer 210 in the third embodiment may be greater than or equal to the thickness of the first barrier layer 210 in the first embodiment.
It should be noted that the concave curvature of the concave 111 of the shallow trench isolation in the third embodiment is different from that of the concave 111 of the shallow trench isolation structure 110 in the first embodiment. Specifically, since the PNR process is performed before the etching buffer layer 200 is formed in the first embodiment, the PNR process may cause a portion of the isolation medium in the sti structure 110 to be further lost, so that the concavity of the recess 111 formed thereby is relatively large. Referring to the second embodiment, in the third embodiment, the PNR process is not performed, but the etching buffer layer 200 is directly formed on the array region AA and the peripheral region PA of the substrate 100, so that the recess 111 is formed only by the loss caused by the process steps before the PNR process, and the concave curvature of the recess 111 is smaller than that of the recess 111 in the first embodiment.
In another aspect of the present invention, there is also provided a semiconductor structure, including: the substrate comprises a substrate 100, a shallow trench isolation structure 110 and an etching buffer layer 200, wherein the shallow trench isolation structure 110 is arranged in a peripheral area PA of the substrate 100, and a recess 111 is formed in the surface of the shallow trench isolation structure 110; the etch buffer layer 200 is disposed in the recess 111.
It is understood that the exemplary semiconductor structures described herein may include a variety of other devices and structures, such as other types of devices, e.g., additional transistors, bjts, resistors, capacitors, inductors, diodes, fuses, srams, and/or other logic circuits.
In one embodiment, the etch buffer layer 200 fills the recess 111.
In one embodiment, the etch buffer layer 200 includes a first barrier layer 210 and an insulating layer 220; the first barrier layer 210 is formed on the bottom wall surface of the recess 111, and the insulating layer 220 is formed on the surface of the first barrier layer 210.
In one embodiment, the first barrier layer 210 comprises silicon nitride and the insulating layer 220 comprises silicon oxide. Since the silicon nitride is hard and is not easily etched, the first blocking layer 210 can effectively block the isolation dielectric in the shallow trench isolation structure 110 from being removed by the subsequent multi-step wet etching process. The silicon oxide has a low hardness and a good fluidity, so that the insulating layer 220 can fill the recess 111 well, thereby reducing the process difficulty.
In one embodiment, first barrier layer 210 and insulating layer 220 fill recess 111.
By way of example, the thickness of first barrier layer 210 is less than or equal to 80nm, and may be, for example, 20nm, 40nm, and 60nm. Of course, the present invention should not be limited thereto, and those skilled in the art can make corresponding adjustments according to actual design requirements.
In one embodiment, the etching buffer layer 200 includes a first barrier layer 210, the first barrier layer 210 is formed on the bottom wall surface of the recess 111 and has a sub-recess 2211 matching the recess 111, and the concave curvature of the sub-recess 2211 is smaller than that of the recess 111.
In summary, the semiconductor structure and the manufacturing method thereof according to the embodiments of the present invention have the following advantages:
in the semiconductor structure and the manufacturing method thereof according to the embodiment of the invention, the etching buffer layer 200 is formed on the surface of the recess 111 of the shallow trench isolation structure 110. When multi-step wet etching is performed, the etching buffer layer 200 can prevent the isolation dielectric loss in the shallow trench isolation structure 110 from being excessive, and avoid the problem of gate leakage.
In the embodiments of the invention, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless expressly limited otherwise. The terms "mounted," "connected," "fixed," and the like are to be construed broadly, and for example, "connected" may be a fixed connection, a removable connection, or an integral connection; "coupled" may be direct or indirect through an intermediary. Specific meanings of the above terms in the embodiments of the invention may be understood by those of ordinary skill in the art according to specific situations.
In the description of the embodiments of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the referred device or unit must have a specific direction, be configured and operated in a specific orientation, and thus, should not be construed as limiting the embodiments of the present invention.
In the description of the present specification, the description of "one embodiment," "some embodiments," "a specific embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an inventive embodiment. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the embodiments of the invention should be included in the protection scope of the embodiments of the invention.
Claims (19)
1. A method of fabricating a semiconductor structure, comprising:
forming a shallow trench isolation structure with a recess on the surface in the peripheral area of the substrate;
forming etching buffer layers on the array region and the peripheral region of the substrate, wherein the etching buffer layers fill the depressions; and
and removing part of the etching buffer layer of the peripheral area to expose the surface of the peripheral area, wherein the remained etching buffer layer is arranged in the recess.
2. The method of claim 1, wherein after removing a portion of the etch buffer layer in the peripheral region, the method further comprises:
an HKMG process is performed on the peripheral region.
3. The method of manufacturing a semiconductor structure according to claim 1 or 2, wherein the etching buffer layer includes a first barrier layer and an insulating layer;
a step of forming an etch buffer layer on the array region and the peripheral region of the substrate, comprising:
forming a first barrier layer on the array region and the peripheral region of the substrate, wherein the first barrier layer is matched with the recess;
and forming the insulating layer on the surface of the first barrier layer, wherein part of the insulating layer is formed in the recess.
4. The method of claim 3, wherein the first barrier layer comprises silicon nitride and the insulating layer comprises silicon oxide.
5. The method of claim 3, wherein prior to forming the first barrier layer on the substrate, the method further comprises:
a second barrier layer is formed over the array region.
6. The method of claim 5, wherein removing a portion of the etch buffer layer in the peripheral region to expose a surface of the peripheral region, and wherein the remaining etch buffer layer is disposed in the recess, comprises:
and sequentially removing part of the insulating layer and part of the first barrier layer by adopting a CMP (chemical mechanical polishing) process so as to expose the surfaces of the second barrier layer and the peripheral region, and filling the recess with the remained first barrier layer and the remained insulating layer.
7. The method of claim 6, wherein the thickness of the first barrier layer remaining is less than or equal to 80nm.
8. The method of claim 3, wherein removing a portion of the etch buffer layer in the peripheral region to expose a surface of the peripheral region, and wherein the remaining etch buffer layer is disposed in the recess, comprises:
removing part of the insulating layer and part of the first barrier layer on the peripheral area to expose the surface of the peripheral area, wherein the remained insulating layer and the remained first barrier layer fill the recess;
and removing the insulating layer on the array region, wherein the first barrier layer covers the array region.
9. The method as claimed in claim 8, wherein the insulating layer on the array region is removed and the remaining insulating layer on the peripheral region is removed.
10. The method of claim 8, wherein removing a portion of the insulating layer and a portion of the first barrier layer on the periphery region to expose a surface of the periphery region comprises:
forming a photoresist layer on the insulating layer of the array region and the peripheral region;
removing the photoresist layer on the insulating layer of the peripheral area;
removing part of the insulating layer on the first barrier layer in the peripheral area by taking the photoresist layer on the array area as a mask;
removing the photoresist layer of the array region;
removing the first barrier layer on the surface of the substrate on the peripheral area to expose the surface of the peripheral area, wherein the first barrier layer is remained on the bottom wall surface of the recess and is provided with a sub-recess matched with the recess, and the concave curvature of the sub-recess is smaller than that of the recess;
and removing the insulating layer of the array region and the remaining insulating layer of the peripheral region.
11. The method of claim 8, wherein removing a portion of the insulating layer and a portion of the first barrier layer on the periphery region to expose a surface of the periphery region comprises:
forming a photoresist layer on the insulating layer on the array region and the peripheral region;
removing the photoresist layer on the insulating layer in the peripheral region;
removing a part of the insulating layer on the first barrier layer of the peripheral region and the first barrier layer on the surface of the substrate by taking the photoresist layer on the array region as a mask so as to expose the surface of the peripheral region, wherein the remained first barrier layer is positioned on the bottom wall surface of the recess and is provided with a sub-recess matched with the recess, and the concave curvature of the sub-recess is smaller than that of the recess;
removing the photoresist layer of the array region;
and removing the insulating layer of the array region and the remaining insulating layer of the peripheral region.
12. A semiconductor structure, comprising:
a substrate;
the shallow trench isolation structure is arranged in the peripheral area of the substrate, and the surface of the shallow trench isolation structure is provided with a recess; and
and the etching buffer layer is arranged in the recess.
13. The semiconductor structure of claim 12, wherein the etch buffer fills the recess.
14. The semiconductor structure of claim 12, wherein the etch buffer layer comprises a first barrier layer and an insulating layer; the first barrier layer is formed on the surface of the bottom wall of the recess, and the insulating layer is formed on the surface of the first barrier layer.
15. The semiconductor structure of claim 14, wherein the first barrier layer comprises silicon nitride and the insulating layer comprises silicon oxide.
16. The semiconductor structure of claim 14, wherein the first barrier layer and the insulating layer fill the recess.
17. The semiconductor structure of claim 14, wherein the first barrier layer has a thickness of less than or equal to 80nm.
18. The semiconductor structure of claim 12, wherein the etch buffer layer comprises a first barrier layer formed on a bottom wall surface of the recess and having sub-recesses adapted to the recess, and a concave curvature of the sub-recesses is smaller than a concave curvature of the recess.
19. The semiconductor structure of claim 18, wherein the first barrier layer comprises silicon nitride.
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