JP2008066545A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique by which peeling of a low-dielectric constant film can be prevented and the chip area can be reduced. <P>SOLUTION: A semiconductor device has multilayer wiring which is composed of first to fourth layers of wiring which are covered with low-dielectric constant films 5a, 5b, 5c and 5d having specific inductive capacity equal to or lower than 3.0, for example, and fifth to eighth layers of wiring which are positioned in the upper part of the first to forth layers of wiring and are covered with insulating films having specific inductive capacity higher than 3.0. In this case, reinforcing patterns 6 are formed in the corners of a semiconductor chip by first to fourth layers of dummy wiring D1-D4 which are in the same layers as the first to fourth layers. Also, various mark patterns are formed in the region of the corners of the semiconductor chip where the reinforcing patterns 6 are formed by fifth to eighth layers of dummy wiring 7, 8, 9 and 10 which are in the same layers as the fifth to eighth layers of wiring. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a reinforcing pattern at a corner portion of a chip.

  For example, the alignment mark formed by the uppermost metal wiring layer is arranged along the dicing line at the corner portion of the chip to physically reinforce the corner portion of the chip, and is thin with a low dielectric constant interlayer insulating film. Japanese Patent Application Laid-Open No. 2005-109145 (see Patent Document 1) discloses a technique capable of suppressing peeling of a chip from a corner portion during dicing, which is likely to occur between a barrier film such as a SICN film.

  In addition, the outer surface of the wiring provided in the semiconductor chip is formed, the interface between the interlayer film and the upper layer of the interlayer film, the interface between the interlayer film and the lower layer of the interlayer film, or the surface of the portion where the interlayer film is removed Japanese Unexamined Patent Application Publication No. 2005-327875 (see Patent Document 2) discloses a technique for preventing film peeling of an interlayer film by forming an insulating film so as to cover the film.

  Further, in an LSI that employs a low-k film as an interlayer film, a reinforcement pattern for suppressing the occurrence of interlayer film peeling is arranged on the outer periphery of the LSI, thereby preventing the interlayer film from peeling off due to the reinforcing pattern. A technique capable of achieving this is disclosed in Japanese Patent Application Laid-Open No. 2004-172169 (see Patent Document 3).

  In addition, by connecting the metal for the second dummy wiring that is not used as a circuit to the first dummy wiring that is not used as a circuit via a via plug, the stress applied to the interlayer insulating film when the metal is polished is reduced. Japanese Unexamined Patent Application Publication No. 2005-142351 (see Patent Document 4) discloses a technique for preventing the insulating film from peeling off by dispersing.

  In addition, a pattern formed by a plurality of external connection electrode pads and wiring necessary for actual circuit operation for connecting the plurality of electrode pads on a predetermined area of the corner portion on the diagonal line of the LSI. Japanese Patent Publication No. 8-34226 (refer to Patent Document 5) describes an image recognition position detection pattern used for detecting the position of the image.

In addition, there is a technique for forming one or a plurality of identification symbols selected from the group consisting of numbers, characters, symbols, and figures by using an uneven portion of a laminated structure with a wiring layer and / or an insulating film in a bonding pad region. It describes in Unexamined-Japanese-Patent No. 11-135391 (refer patent document 6).
JP 2005-109145 A JP 2005-327875 A JP 2004-172169 A JP 2005-142351 A Japanese Patent Publication No. 8-34226 JP-A-11-135391

  In recent years, due to the reduction in wiring pitch accompanying the miniaturization of semiconductor elements, an increase in parasitic capacitance between wirings has hindered an increase in operating speed of semiconductor devices. Therefore, in order to reduce the parasitic capacitance between the wirings, a low dielectric constant film (low-k film) having a relative dielectric constant of 3.0 or less is used as an interlayer insulating film of the multilayer wiring. However, since the low dielectric constant film has low density and weak adhesion strength with the insulating film formed in the lower layer or the upper layer, the interface between the low dielectric constant film and the lower insulating film, or the low dielectric constant film There is a problem that peeling easily occurs at the interface with the upper insulating film. The peeling of the low dielectric constant film is likely to occur in the thermal cycle test performed in the inspection process of the semiconductor device. In particular, since the stress of the low dielectric constant film is the largest at the corner portion of the semiconductor chip, the peeling from the corner portion of the semiconductor chip. It occurs selectively. Therefore, by forming a reinforcing pattern at the corner portion of the semiconductor chip, the low dielectric constant film is prevented from peeling off or progressing. For example, in a semiconductor device having a multilayer wiring, a reinforcing pattern having a structure in which upper and lower dummy wirings are connected to each other by a plug has been proposed.

  By the way, in general, various mark patterns relating to a semiconductor device such as a logo mark and a model name are arranged in an empty space in a corner portion of a semiconductor chip. However, when the above-described reinforcing pattern is formed in an empty space in the corner portion of the semiconductor chip, various mark patterns and the reinforcing pattern cannot be formed in the same region by arranging them in a plane, and therefore the empty space in the corner portion of the semiconductor chip. There is a need to expand the space, which leads to an increase in chip area. Further, due to the demand for reducing the area where the input / output circuit of the semiconductor device is formed, the electrode pad and the input / output circuit are closer to the corner portion of the semiconductor chip, and the empty space at the corner portion of the semiconductor chip is reduced. In the direction. For this reason, it is difficult to form both the various mark patterns and the reinforcing pattern in the corner portion of the semiconductor chip.

  An object of the present invention is to provide a technique capable of preventing peeling of a low dielectric constant film and reducing the chip area.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a first wiring group composed of one or two or more wiring layers covered with a first insulating film having a low relative dielectric constant, and is positioned above the first wiring group and has a relative dielectric constant of A method of manufacturing a semiconductor device for forming a multilayer wiring of two or more layers constituted by a second wiring group consisting of one or two or more wirings covered with a high second insulating film, A reinforcing pattern is formed in a corner portion of the semiconductor chip by a first dummy wiring group consisting of one or two or more dummy wirings in the same layer as each wiring constituting the wiring group, and the reinforcing pattern of the corner portion of the semiconductor chip is formed. Various mark patterns are formed by the second dummy wiring group consisting of one or two or more layers of dummy wirings in the same layer as the respective wirings constituting the second wiring group in the region where is formed.

  The present invention is a fourth wiring group composed of one layer or two or more wiring layers covered with a first insulating film having a low relative dielectric constant, and is positioned above the fourth wiring group and has a relative dielectric constant of A semiconductor device manufacturing method for forming a multilayer wiring of two or more layers constituted by a fifth wiring group consisting of one or two or more wirings covered with a high second insulating film, comprising: A reinforcing pattern is formed at a corner portion of the semiconductor chip by a dummy wiring group consisting of one or two or more dummy wirings in the same layer as each wiring constituting the fifth wiring group, and the reinforcing pattern of the corner portion of the semiconductor chip is formed. In the region where is formed, various mark patterns are formed by dummy wiring groups in the same layer as the respective wirings constituting the fourth and fifth wiring groups, and dummy wirings constituting reinforcing patterns around the various mark patterns are formed. To remove Ri, it is to separate the the various marks pattern reinforcement pattern.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since various mark patterns and reinforcing patterns can be collectively arranged at the corner portion of the semiconductor chip, peeling of the low dielectric constant film can be prevented and at the same time the chip area can be reduced.

  In the present embodiment, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified, the case is clearly limited to a specific number in principle, etc. It is not limited to the specific number, and it may be more or less than the specific number. Further, in the present embodiment, it is needless to say that the constituent elements (including element steps and the like) are not necessarily indispensable, unless otherwise specified and clearly considered essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  Further, in the drawings used in this embodiment mode, hatching is given to make the drawings easy to see even if they are plan views. Further, in all drawings for explaining the present embodiment, parts having the same function are denoted by the same reference numerals, and repeated explanation thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
An arrangement area (hereinafter referred to as a mark pattern area) of various mark patterns according to the first embodiment will be described with reference to FIGS. FIG. 1 is an overall view of a semiconductor chip showing a mark pattern region according to the first embodiment, and FIG. 2 is an enlarged plan view of the mark pattern region according to the first embodiment.

  As shown in FIG. 1, a dicing line region 1 is arranged along each side of the semiconductor chip SC, and each of the four corners of the semiconductor chip SC has a position recognition (alignment) mark, a product type name, and a logo mark. A mark pattern region 2 in which various mark patterns such as are arranged is provided. A guard ring 4 is provided at the boundary between the dicing line region 1 and the mark pattern region 2 and the integrated circuit region 3, and the guard ring 4 causes cracks or the like at the end of the integrated circuit facing the dicing line in the dicing process. You can prevent damage. The width of the guard ring 4 is, for example, 10 μm or more.

  As shown in FIG. 2, the mark pattern region 2 in the corner portion of the semiconductor chip SC has a polygonal shape formed within an area of, for example, 150 μm × 150 μm. Further, in the mark pattern region 2 in the semiconductor device having two or more layers of multilayer wiring, the upper layer wiring (the uppermost layer wiring or the uppermost layer) covered with an insulating film having a relative dielectric constant higher than 3.0. A mark pattern (X mark in FIG. 2) 10 is formed using a dummy wiring in the same layer and two or more layers of wiring including a low dielectric constant film having a relative dielectric constant of 3.0 or less. For example, a stripe-shaped reinforcing pattern (shaded hatching in FIG. 2) 6 is formed by using a dummy wiring in the same layer as the lower layer wiring (one or more wirings). That is, the reinforcing pattern 6 is formed using a dummy wiring located below the dummy wiring constituting the mark pattern 10. This reinforcing pattern 6 is formed mainly to prevent peeling of the low dielectric constant film covering the wiring. Therefore, as will be described later, when the cross section of the mark pattern region 2 is viewed, a part of the upper dummy wiring constituting the mark pattern 10 and a part of the lower dummy wiring constituting the reinforcing pattern 6 are in the vertical direction. There are places that are placed in the same position.

  Next, an example of arrangement of various mark patterns and reinforcing patterns will be described with reference to FIG. FIGS. 3A, 3B, and 3C show a first arrangement example, a second arrangement example, and a second arrangement example of various mark patterns and reinforcing patterns formed in the semiconductor device having the multilayer wiring according to the first embodiment, respectively. It is sectional drawing which shows the example of 3 arrangement | positioning. Here, a semiconductor device having eight-layer wiring is illustrated, but the number of wiring layers is not limited to this, and the present invention can be applied to a semiconductor device having two or more layers of multilayer wiring.

  First, in the first arrangement example shown in FIG. 3A, the first layer wiring is formed by a copper wiring formed by a single damascene method, and the second to eighth layer wirings are formed by a dual damascene method. A low dielectric constant film having a relative dielectric constant film of 3.0 or less and a fifth layer to an eighth layer of wiring on an insulating film covering the first layer to fourth layer wiring. An insulating film having a relative dielectric constant higher than 3.0, such as a silicon oxide film, is used as the covering insulating film.

  In order to prevent peeling of the low dielectric constant films 5a, 5b, 5c, and 5d covering the first to fourth layer wirings (first wiring group), a reinforcing pattern 6 is formed in the mark pattern region. ing. A first-layer dummy wiring D1 constituting the reinforcing pattern 6 is formed using a copper film in the same layer as the first-layer wiring, and thereafter, a copper film in the same layer as the second-layer wiring is formed similarly. The dummy wiring D2 of the second layer constituting the reinforcing pattern 6 is formed, and the dummy wiring D3 of the third layer constituting the reinforcing pattern 6 is formed using a copper film in the same layer as the wiring of the third layer. A fourth-layer dummy wiring D4 that forms the reinforcing pattern 6 is formed using a copper film in the same layer as the fourth-layer wiring.

  Further, the first-layer dummy wiring D1 and the second-layer dummy wiring D2 are connected by a connecting member formed integrally with the second-layer dummy wiring D2, and the second-layer dummy wiring D2 is connected to the second-layer dummy wiring D2. The third-layer dummy wiring D3 is connected by a connecting member formed integrally with the third-layer dummy wiring D3, and the third-layer dummy wiring D3 and the fourth-layer dummy wiring D4 are connected to each other. They are connected by a connecting member formed integrally with the fourth-layer dummy wiring D4. Accordingly, the first to fourth dummy wirings D1, D2, D3, D4 (first dummy wiring group) formed to prevent the low dielectric constant films 5a, 5b, 5c, 5d from peeling off. The reinforcing pattern 6 made of all has a connected structure. The planar shape of the reinforcing pattern 6 is, for example, a plurality of stripes or a plurality of L-shapes.

  The fifth to eighth layer wirings (second wiring group) are wirings that are not easily affected by the parasitic capacitance between the wirings, and are, for example, power supply wirings. Therefore, since an insulating film having a relative dielectric constant higher than 3.0 can be used as the insulating film covering these wirings, the problem of peeling such as the low dielectric constant films 5a, 5b, 5c, and 5d hardly occurs. Formation of the reinforcing pattern 6 is not required. Therefore, using dummy wirings in the same layer as the fifth to eighth layer wirings, various mark patterns 7, 8,. 9 and 10 are formed. The mark patterns 7, 8, 9, and 10 can be freely arranged in the mark pattern region. Further, the fourth-layer dummy wiring D4 constituting the uppermost layer of the reinforcing pattern 6 and the lowermost mark pattern 7 may not be connected.

  Next, in the second arrangement example shown in FIG. 3B, as in the first arrangement example described above, the first layer wiring is a copper wiring formed by a single damascene method, and the second to eighth layers. The wiring of the layer is composed of a copper wiring formed by a dual damascene method, and a low dielectric constant film, a fifth layer to an eighth layer are formed on the insulating film covering the first layer to the fourth layer wiring. An insulating film having a relative dielectric constant higher than 3.0 is used as the insulating film covering the wiring.

  In order to prevent peeling of the low dielectric constant films 5a, 5b, 5c, and 5d covering the first to fourth layer wirings (first wiring group), the mark pattern region includes the first to second layers. A reinforcing pattern 6 constituted by the fourth-layer dummy wirings D1, D2, D3, D4 (first dummy wiring group) is formed. Further, a fifth-layer dummy wiring D5 (third dummy wiring group) is formed using a copper film in the same layer as the fifth-layer wiring (third wiring group). The dummy wiring D5 and the fourth-layer dummy wiring D4 are connected by a connecting member formed integrally with the fifth-layer dummy wiring D5. That is, the reinforcing effect of the reinforcing pattern 6 can be improved by additionally forming the fifth-layer dummy wiring D5 on the further lower layer of the low dielectric constant film 5d. The planar shape of the reinforcing pattern 6 is, for example, a plurality of stripes or a plurality of L-shapes.

  Therefore, using the dummy wirings (second dummy wiring group) in the same layer as the sixth to eighth layer wirings (second wiring group), in the mark pattern area, the position recognition mark, Various mark patterns 8, 9, 10 such as product type names and logo marks are formed. The mark patterns 8, 9, and 10 can be freely arranged in the mark pattern area. Further, the dummy wiring D5 of the fifth layer constituting the uppermost layer of the reinforcing pattern 6 and the mark pattern 8 of the lowermost layer may not be connected.

  Next, in the third arrangement example shown in FIG. 3C, as in the first arrangement example described above, the first layer wiring is a copper wiring formed by a single damascene method, and the second to eighth layers. The wiring of the layer is composed of a copper wiring formed by a dual damascene method, and a low dielectric constant film, a fifth layer to an eighth layer are formed on the insulating film covering the first layer to the fourth layer wiring. An insulating film having a relative dielectric constant higher than 3.0 is used as the insulating film covering the wiring.

  In order to prevent peeling of the low dielectric constant films 5a, 5b, 5c, and 5d covering the first to fourth layer wirings (first wiring group), the mark pattern region includes the first to second layers. A reinforcing pattern 6 constituted by the fourth-layer dummy wirings D1, D2, D3, D4 (first dummy wiring group) is formed. Furthermore, the fifth to seventh layer dummy wirings D5, D6 and D7 (third layer) are respectively formed using the same layer copper film as the fifth to seventh layer wirings (third wiring group). Dummy wiring group) is formed. The fourth-layer dummy wiring D4 and the fifth-layer dummy wiring D5 are connected by a connection member formed integrally with the fifth-layer dummy wiring D5, and the fifth-layer dummy wiring D5 is connected to the fifth-layer dummy wiring D5. The sixth-layer dummy wiring D6 is connected by a connecting member formed integrally with the sixth-layer dummy wiring D6, and the sixth-layer dummy wiring D6 and the seventh-layer dummy wiring D7 are: They are connected by a connecting member formed integrally with the seventh-layer dummy wiring D7. That is, the reinforcement effect of the reinforcement pattern 6 can be further improved by configuring the reinforcement pattern 6 with wirings other than the uppermost layer of the eighth layer. The planar shape of the reinforcing pattern 6 is, for example, a plurality of stripes or a plurality of L-shapes.

  Therefore, using the dummy wiring (second dummy wiring group) in the same layer as the eighth layer wiring (second wiring group), the mark pattern area has a position recognition mark, product model name, logo mark. Various mark patterns 10 are formed. The mark pattern 10 can be freely arranged in the mark pattern region. Further, the seventh-layer dummy wiring D7 constituting the uppermost layer of the reinforcing pattern 6 and the mark pattern 10 may not be connected.

  As described above, according to the first embodiment, the reinforcing pattern is formed in the mark pattern region by using at least the dummy wiring in the same layer as the wiring covered with the low dielectric constant film among the wirings in each layer constituting the multilayer wiring. The mark pattern is formed in the mark pattern region using dummy wirings in the same layer as the wiring not covered with the low dielectric constant film located in the upper layer of the wiring constituting the reinforcing pattern. As a result, the mark pattern and the reinforcing pattern can be collectively arranged in the mark pattern region, so that the chip area can be reduced at the same time as preventing the low dielectric constant film from peeling off.

  Next, the manufacturing method of the semiconductor device according to the first embodiment will be described in the order of steps with reference to FIGS. 4 to 12 are cross-sectional views showing the principal part of a CMOS (Complementary Metal Oxide Semiconductor) device having six-layer wiring and a method of manufacturing various mark patterns and reinforcement patterns according to the first embodiment. In the figure, area A indicates an integrated circuit formation area in which a CMOS device is formed, and area B indicates a mark pattern area in which various mark patterns and reinforcing patterns are formed. In addition, although the manufacturing method of the various mark patterns and reinforcement pattern of the 1st arrangement example mentioned above is demonstrated here, the various mark patterns and reinforcement pattern of the 2nd arrangement example or the 3rd arrangement example can be manufactured similarly. .

  First, as shown in FIG. 4, a semiconductor substrate (semiconductor plate having a substantially planar shape called a semiconductor wafer) 11 made of, for example, p-type single crystal silicon is prepared. Next, the element isolation region 12 is formed on the main surface of the semiconductor substrate 11. In the element isolation region 12, a groove having a depth of 0.35 μm is formed by etching the semiconductor substrate 11, and then an insulating film such as a silicon oxide film is formed on the main surface of the semiconductor substrate 11 by a CVD (Chemical Vapor Deposition) method. After the deposition, the silicon oxide film outside the trench is formed by removing by a CMP (Chemical Mechanical Polishing) method.

  Next, a p-type impurity, for example, boron (B) is ion-implanted into the nMIS formation region of the semiconductor substrate 11 to form a p-type well 13, and an n-type impurity, for example, phosphorus (P) is formed in the pMIS formation region of the semiconductor substrate 11. Are implanted to form an n-type well 14. Thereafter, an impurity for controlling the threshold value of nMIS or pMIS may be ion-implanted into the p-type well 13 or the n-type well 14.

  Next, after cleaning the surface of the semiconductor substrate 11 by wet etching using, for example, a hydrofluoric acid aqueous solution, the semiconductor substrate 11 is thermally oxidized, and, for example, a gate insulating film 15 having a thickness of 5 nm is formed on the surface of the semiconductor substrate 11 (p-type). Each surface is formed on the well 13 and the n-type well 14.

  Next, as shown in FIG. 5, a gate electrode conductor film having a thickness of, for example, 0.2 μm is formed on the gate insulating film 15, and then the gate electrode conductor film is formed by dry etching using a resist pattern as a mask. Are processed to form gate electrodes 16n and 16p made of a conductor film. The conductive film for the gate electrode is made of, for example, a polycrystalline silicon film formed by a CVD method, the gate electrode 16n is made of a polycrystalline silicon film into which an n-type impurity is introduced in the nMIS formation region, and p is formed in the pMIS formation region. A gate electrode 16p made of a polycrystalline silicon film doped with type impurities is formed.

Next, an n-type impurity such as arsenic (As) is ion-implanted into the p-type well 13 to form a relatively low concentration source / drain extension region 17 in a self-aligned manner with respect to the nMIS gate electrode 16n. Similarly, a p-type impurity, for example, boron fluoride (BF ₂ ) is ion-implanted into the n-type well 14 to form a relatively low concentration source / drain extension region 18 in a self-aligned manner with respect to the gate electrode 16p of the pMIS. Form.

  Next, as shown in FIG. 6, after a silicon oxide film 19 is deposited on the main surface of the semiconductor substrate 11 by a CVD method, a silicon nitride film is further deposited on the silicon oxide film 19 by a CVD method. Subsequently, the silicon nitride film is anisotropically etched by RIE (Reactive Ion Etching) to form sidewalls 20 on the respective sidewalls of the nMIS gate electrode 16n and the pMIS gate electrode 16p. Thereafter, an n-type impurity, for example, arsenic is ion-implanted into the p-type well 13 to form a source / drain diffusion region 21 having a relatively high concentration in a self-aligned manner with respect to the gate electrode 16n and the sidewall 20 of the nMIS. Similarly, a p-type impurity, such as boron fluoride, is ion-implanted into the n-type well 13 to form a relatively high concentration source / drain diffusion region 22 in a self-aligned manner with respect to the gate electrode 16p and the sidewall 20 of the pMIS. Form.

  Next, low resistance is applied to the surface of the nMIS gate electrode 16n and the source / drain diffusion region 21, the surface of the pMIS gate electrode 16p and the source / drain diffusion region 22, and the surface of the semiconductor substrate 11 in the mark pattern region by salicide technology. A nickel silicide (NiSi) layer 23 is formed. Although the nickel silicide layer 23 is illustrated here, other silicide layers such as a titanium silicide layer or a cobalt silicide layer may be formed.

  Next, as shown in FIG. 7, a silicon nitride film is deposited on the main surface of the semiconductor substrate 11 by a CVD method to form a first insulating film 24a. Subsequently, a TEOS (Tetra Ethyl Ortho Silicate) film is deposited on the first insulating film 24a by plasma CVD to form a second insulating film 24b, and an interlayer insulating film composed of the first and second insulating films 24a and 24b is formed. Form. Thereafter, the surface of the second insulating film 24b is polished by a CMP method. Even if an uneven shape is formed on the surface of the first insulating film 24a due to the base step, the interlayer insulating film whose surface is flattened by polishing the surface of the second insulating film 24b by CMP is obtained. can get.

  Next, the first and second insulating films 24a and 24b are etched using the resist pattern as a mask, and the connection holes 25 are formed at predetermined locations, for example, the nMIS gate electrode 16n and the source / drain diffusion regions 21, and the pMIS gate electrode 16p. And the first and second insulating films 24 a and 24 b located above the source / drain diffusion region 22. Further, the connection hole 25 is also formed in the mark pattern region.

  Next, after depositing a barrier metal film 26 on the main surface of the semiconductor substrate 11 including the inside of the connection hole 25, a tungsten film 27 is deposited on the main surface of the semiconductor substrate 11 including the inside of the connection hole 25 by the CVD method. Then, the barrier metal film 26 and the tungsten film 27 other than the connection hole 25 are removed by CMP, for example, so that the tungsten film 27 is embedded in the connection hole 25, and a plug using the tungsten film 27 as a main conductive material is formed. The barrier metal film 26 is, for example, a laminated film in which titanium nitride films are stacked on a titanium film.

  Next, the first layer wiring and the first layer dummy wiring constituting the reinforcing pattern are formed by a single damascene method. First, as shown in FIG. 8, a stopper insulating film 28 and a wiring forming insulating film 29 are sequentially formed on the main surface of the semiconductor substrate 11. The stopper insulating film 28 is a film that becomes an etching stopper when a groove is formed in the insulating film 29, and a material having an etching selectivity with respect to the insulating film 29 is used. The stopper insulating film 28 is a silicon nitride film formed by, for example, a plasma CVD method, and the insulating film 29 is a low dielectric constant film. For example, an organic silica glass (SiOC) insulating film containing carbon or hydrogen in silicon oxide is used. can do.

  Next, after forming a wiring groove 30 in a predetermined region of the stopper insulating film 28 and the insulating film 29 by dry etching using a resist pattern as a mask, a barrier metal film 31 is formed on the main surface of the semiconductor substrate 11. The barrier metal film 31 is, for example, a titanium nitride film, a tantalum nitride film, a stacked film in which a tantalum film is stacked on a tantalum nitride film, or a stacked film in which a ruthenium film is stacked on a tantalum nitride film. Subsequently, a copper seed layer is formed on the barrier metal film 31 by CVD or sputtering, and a copper plating film is further formed on the seed layer by electrolytic plating. The inside of the wiring groove 30 is embedded with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 31 in a region other than the wiring trench 30 are removed by CMP to form a first-layer wiring M1 and a dummy wiring D1 using the copper film as a main conductive material. .

  Next, a second layer wiring and a second layer dummy wiring constituting the reinforcing pattern are formed by a dual damascene method. First, as shown in FIG. 9, a cap insulating film 32 and an insulating film 33 are sequentially formed on the main surface of the semiconductor substrate 11. The cap insulating film 32 is made of a material having an etching selectivity with respect to the insulating film 33, and can be a silicon nitride film formed by, for example, a plasma CVD method. Further, the cap insulating film 32 has a function as a protective film for preventing diffusion of copper constituting the first layer wiring M1. The insulating film 33 is a low dielectric constant film, and can be, for example, an organic silica glass-based insulating film.

  Next, the insulating film 33 is processed by dry etching using a resist pattern for hole formation as a mask. At this time, the stopper insulating film 32 functions as an etching stopper. Further, the insulating film 33 is processed to a predetermined depth by dry etching using a resist pattern for forming a wiring trench as a mask. Subsequently, the exposed cap insulating film 32 is removed by dry etching, whereby a connection hole 34 and a wiring groove 35 are formed in the insulating film 33.

  Next, a barrier metal film 36 is formed on the main surface of the semiconductor substrate 11 including the insides of the connection holes 34 and the wiring grooves 35. The barrier metal film 36 is, for example, a titanium nitride film, a tantalum nitride film, a stacked film in which a tantalum film is stacked on a tantalum nitride film, or a stacked film in which a ruthenium film is stacked on a tantalum nitride film. Subsequently, a copper seed layer is formed on the barrier metal film 36 by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by an electrolytic plating method. The inside of the connection hole 34 and the wiring groove 35 is embedded with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 36 in the region other than the connection hole 34 and the wiring groove 35 are removed by CMP, and the second-layer wiring M2 and dummy wiring using the copper film as the main conductive material D2 is formed.

  Thereafter, as shown in FIG. 10, for example, the third layer and the fourth layer wirings M3 and M4 and the reinforcing pattern constituting the reinforcing pattern are formed by the same method as the above-described second layer wiring M2 and dummy wiring D2. Dummy wirings D3 and D4 for the third layer and the fourth layer are formed. Accordingly, the first to fourth layer wirings M1, M2, M3, and M4 are covered with the low dielectric constant insulating film, thereby insulating the wirings M1, M2, M3, and M4 of these layers from the low dielectric constant. Although there is a problem of peeling at the interface with the film, a reinforcing pattern composed of the first to fourth dummy wirings D1, D2, D3, and D4 is formed in the mark pattern region of the corner portion of the semiconductor chip. Therefore, the above problem of peeling can be solved.

  Next, wirings higher than the fourth layer, for example, fifth and sixth layer wirings are formed. These fifth-layer and sixth-layer wirings are, for example, power supply wirings, and an increase in parasitic capacitance between the wirings is not a big problem. Therefore, the fifth-layer wiring and the sixth-layer wiring are not used. It is not necessary to use a low dielectric constant film for the insulating film to be covered. Therefore, here, a silicon oxide film having a relative dielectric constant higher than 3.0 is mainly used as the insulating film covering the wiring.

  First, the fifth layer wiring and the dummy wiring constituting the mark pattern are formed by the dual damascene method. As shown in FIG. 11, a cap insulating film 37 and an insulating film 38 are sequentially formed on the main surface of the semiconductor substrate 11. The cap insulating film 37 is made of a material having an etching selectivity with respect to the insulating film 38, and can be a silicon nitride film formed by, for example, a plasma CVD method. Further, the cap insulating film 37 has a function as a protective film for preventing diffusion of copper constituting the fourth layer wiring M4. The insulating film 38 can be a TEOS film formed by, for example, a plasma CVD method.

  Next, the insulating film 38 is processed by dry etching using the resist pattern for hole formation as a mask. At this time, the stopper insulating film 37 functions as an etching stopper. Further, the insulating film 38 is processed to a predetermined depth by dry etching using the resist pattern for forming the wiring trench as a mask. Subsequently, the exposed cap insulating film 37 is removed by dry etching, whereby a connection hole 39 and a wiring groove 40 are formed in the insulating film 38.

  Next, a barrier metal film 41 is formed on the main surface of the semiconductor substrate 11 including the insides of the connection holes 39 and the wiring grooves 40. The barrier metal film 41 is, for example, a titanium nitride film, a tantalum film, or a tantalum nitride film. Subsequently, a copper seed layer is formed on the barrier metal film 41 by CVD or sputtering, and a copper plating film is further formed on the seed layer by electrolytic plating. The inside of the connection hole 39 and the wiring groove 40 is embedded with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 41 in regions other than the connection hole 34 and the wiring groove 35 are removed by CMP to form a fifth-layer wiring M5 and a dummy wiring D5.

  Then, as shown in FIG. 12, for example, the sixth-layer wiring M6 and the sixth-layer dummy wiring D6 constituting the mark pattern are formed by the same method as the fifth-layer wiring M5 and the dummy wiring D5 described above. Form. Subsequently, a silicon nitride film 42 is formed on the sixth-layer wiring M6 and the dummy wiring D6, and a silicon oxide film 43 is formed on the silicon nitride film 42. The silicon nitride film 42 and the silicon oxide film 43 function as a passivation film that prevents moisture and impurities from entering from the outside and suppresses the transmission of α rays.

  Next, the silicon nitride film 42 and the silicon oxide film 43 are processed by etching using the resist pattern as a mask to expose a part of the sixth-layer wiring M6 (bonding pad portion). Subsequently, a bump base electrode 44 made of a laminated film such as a gold film and a nickel film is formed on the exposed sixth-layer wiring M6, and a bump electrode 45 made of gold, solder, or the like is formed on the bump base electrode 44. As a result, the CMOS device having the six-layer wiring according to the first embodiment is almost completed. The bump electrode 45 serves as an external connection electrode. Thereafter, the semiconductor wafer is cut into individual semiconductor chips SC and mounted on a package substrate or the like to complete the semiconductor device, but the description thereof is omitted.

(Embodiment 2)
An arrangement example of various mark patterns and reinforcing patterns according to the second embodiment will be described with reference to FIGS. FIG. 13 is an enlarged plan view of a mark pattern region according to the second embodiment, and FIG. 14 is a cross-sectional view showing an arrangement example of various mark patterns and reinforcing patterns formed on a semiconductor device having a multilayer wiring according to the second embodiment. is there. Here, a semiconductor device having eight-layer wiring is illustrated, but the number of wiring layers is not limited to this, and the present invention can be applied to a semiconductor device having two or more layers of multilayer wiring.

  The difference between the second embodiment and the first embodiment described above is that various mark patterns and reinforcing patterns formed in the mark pattern region are formed by wirings in the same layer. That is, in the above-described first embodiment, the dummy wirings constituting the various mark patterns and the dummy wirings constituting the reinforcing pattern are different layers. However, in the second embodiment, as shown in FIG. 13, a part of the reinforcing pattern (shaded hatching in FIG. 13) formed in the mark pattern region is deleted, and the dummy used for the reinforcing pattern 6 is used. A mark pattern (marked X in FIG. 13) 10 is formed in the reinforcing pattern 6 using a dummy wiring in the same layer as the wiring. The planar shape of the reinforcing pattern 6 is, for example, a plurality of stripes or a plurality of L-shapes, and deletion of dummy wirings around the mark pattern 10 is performed, for example, by a graphic calculation process in the design process. Accordingly, when the cross section of the mark pattern region is viewed, the dummy wirings constituting the mark pattern and the dummy wirings constituting the reinforcing pattern are not arranged at the same position in the vertical direction. As a result, the mark pattern and the reinforcing pattern can be arranged in the mark pattern area without increasing the area of the mark pattern area, and the mark pattern can also have an effect of preventing the low dielectric constant film from peeling off. .

  The multilayer wiring according to the second embodiment is the same as the eight-layer wiring according to the first embodiment described above. That is, the first layer wiring is constituted by a copper wiring formed by a single damascene method, the second layer to the eighth layer wiring is constituted by a copper wiring formed by a dual damascene method, and the first layer to the first layer wiring are formed. Low dielectric constant film whose relative dielectric constant film is 3.0 or less, insulating film covering fourth layer wiring (fourth wiring group), fifth layer to eighth layer wiring (fifth wiring group) An insulating film having a relative dielectric constant higher than 3.0, such as a silicon oxide film, is used as the insulating film covering the film.

  As shown in FIG. 14, in order to prevent peeling of the low dielectric constant films 5a, 5b, 5c, and 5d covering the first to fourth wiring layers, the mark pattern region includes the first to fourth layers. Reinforcing patterns 6 composed of eighth-layer dummy wirings D1 to D8 are formed. A first-layer dummy wiring D1 constituting the reinforcing pattern 6 is formed using a copper film in the same layer as the first-layer wiring, and thereafter, a copper film in the same layer as the second-layer wiring is formed similarly. The dummy wiring D2 of the second layer constituting the reinforcing pattern 6 is formed, and the dummy wiring D3 of the third layer constituting the reinforcing pattern 6 is formed using a copper film in the same layer as the wiring of the third layer. A fourth-layer dummy wiring D4 that forms the reinforcing pattern 6 is formed using a copper film in the same layer as the fourth-layer wiring, and a copper film in the same layer as the fifth-layer wiring is used. The fifth-layer dummy wiring D5 constituting the reinforcement pattern 6 is formed, and the sixth-layer dummy wiring D6 constituting the reinforcement pattern 6 is formed using a copper film in the same layer as the sixth-layer wiring. The seventh-layer dummy wiring D7 constituting the reinforcing pattern 6 is formed using a copper film in the same layer as the seventh-layer wiring. , Eighth-layer dummy wiring D8 that constitute the reinforcement pattern 6 with a copper film of the eighth layer wiring in the same layer are formed.

  Further, the first-layer dummy wiring D1 and the second-layer dummy wiring D2 are connected by a connecting member formed integrally with the second-layer dummy wiring D2, and the second-layer dummy wiring D2 is connected to the second-layer dummy wiring D2. The third-layer dummy wiring D3 is connected by a connecting member formed integrally with the third-layer dummy wiring D3, and the third-layer dummy wiring D3 and the fourth-layer dummy wiring D4 are connected to each other. The fourth-layer dummy wiring D4 and the fifth-layer dummy wiring D5 are integrally formed with the fifth-layer dummy wiring D5. The fifth-layer dummy wiring D5 and the sixth-layer dummy wiring D6 are connected to each other by a connection member formed integrally with the sixth-layer dummy wiring D6. Dummy wiring D6 for the eye and dummy wiring D for the seventh layer Are connected by a connecting member formed integrally with the seventh-layer dummy wiring D7, and the seventh-layer dummy wiring D7 and the eighth-layer dummy wiring D8 are connected to the eighth-layer dummy wiring D8. They are connected by a connecting member formed integrally. Accordingly, all the reinforcing patterns 6 composed of the first to eighth layer dummy wirings D1 to D8 (dummy wiring group) formed to prevent the low dielectric constant films 5a, 5b, 5c and 5d from peeling off. It has a connected structure.

  The mark pattern 50 can also be formed in the mark pattern region in the same manner as the reinforcing pattern 6 by using the first to eighth layer dummy wirings D1 to D8. The mark pattern 50 is a position recognition mark, a product model name, a logo mark, or the like. The mark pattern 50 shown in FIG. 14 is configured using dummy wirings D1 to D8 in the same layer as the wirings in all layers (first to eighth layer wirings). It is not necessary to configure, and the mark pattern 50 can be configured without including some layers. However, if a part of the layers is removed, the reinforcing effect of the mark pattern 50 is reduced. Therefore, it is desirable that the mark pattern 50 is composed of all layers.

  As described above, according to the second embodiment, a part of the reinforcing pattern 6 formed in the mark pattern region is deleted, and the reinforcing pattern 6 is formed using the dummy wiring of the same layer as the dummy wiring used for the reinforcing pattern 6. A mark pattern 50 is formed therein. Thereby, the mark pattern 50 and the reinforcing pattern 6 can be collectively arranged in the mark pattern region, so that the chip area can be reduced at the same time as the peeling of the low dielectric constant film is prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, all the multilayer wirings are damascene copper wirings, but the invention is not limited to this. For example, a semiconductor having wirings formed by lithography and etching using an aluminum alloy film as a wiring material. It can also be applied to devices.

  The present invention can be applied to a semiconductor device provided with a reinforcing pattern at a corner portion of a semiconductor chip.

1 is an overall view of a semiconductor chip showing a mark pattern region according to a first embodiment. FIG. 6 is an enlarged plan view of a mark pattern region according to the first embodiment. (A), (b), and (c) are a first arrangement example, a second arrangement example, and a third arrangement of various mark patterns and reinforcing patterns formed in the semiconductor device having the multilayer wiring according to the first embodiment, respectively. It is sectional drawing which shows an example. 6 is a cross-sectional view of a principal part showing the method of manufacturing a semiconductor device according to the first embodiment. FIG. 5 is a fragmentary cross-sectional view of the same portion as that of FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the same portion as that of FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the same portion as that of FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the same place as that in FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the same portion as that of FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 8; FIG. 10 is an essential part cross-sectional view of the same portion as that of FIG. 4 of the semiconductor device during a manufacturing step following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the same portion as that of FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the same portion as that of FIG. 4 during the manufacturing process of the semiconductor device following that of FIG. 11; It is an enlarged plan view of a mark pattern area according to the second embodiment. It is sectional drawing which shows the example of arrangement | positioning of the various mark patterns and reinforcement pattern which were formed in the semiconductor device which has the multilayer wiring by this Embodiment 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Dicing line area | region 2 Mark pattern area | region 3 Integrated circuit area | region 4 Guard ring 5a, 5b, 5c, 5d Low dielectric constant film | membrane 6 Reinforcement pattern 7, 8, 9, 10 Mark pattern 11 Semiconductor substrate 12 Element isolation area 13 P-type well 14 n-type well 15 gate insulating film 16n, 16p gate electrode 17 source / drain extension region 18 source / drain extension region 19 silicon oxide film 20 sidewall 21 source / drain diffusion region 22 source / drain diffusion region 23 nickel silicide layer 24a first Insulating film 24b Second insulating film 25 Connecting hole 26 Barrier metal film 27 Tungsten film 28 Stopper insulating film 29 Insulating film 30 Wiring groove 31 Barrier metal film 32 Cap insulating film 33 Insulating film 34 Connecting hole 35 Wiring groove 36 Barrier metal film 37 Cap Insulating film 38 Enmaku 39 connecting holes 40 interconnect groove 41 a barrier metal film 42 a silicon film 43 a silicon oxynitride film 44 bump electrode 45 bump electrode 50 mark pattern D1~D8 dummy wiring M1~M6 wiring SC semiconductor chip

Claims (5)

A first wiring group consisting of one layer or two or more wiring layers covered with a first insulating film, and positioned higher than the first wiring group and having a higher relative dielectric constant than the first insulating film A method of manufacturing a semiconductor device for forming a multilayer wiring of two or more layers constituted by a second wiring group composed of one or two or more wirings covered with a second insulating film,
A reinforcing pattern is formed at a corner portion of the semiconductor chip by a first dummy wiring group consisting of one or two or more layers of dummy wirings in the same layer as each wiring constituting the first wiring group, A mark pattern is formed by a second dummy wiring group consisting of one or more dummy wirings in the same layer as each wiring constituting the second wiring group in a region where the reinforcing pattern of the corner portion is formed. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. A first wiring group consisting of one layer or two or more wiring layers covered with a first insulating film, and positioned higher than the first wiring group and having a higher relative dielectric constant than the first insulating film A third wiring group composed of one layer or two or more wiring layers covered with a second insulating film, and a third insulating film that is located above the third wiring group and has a high relative dielectric constant. A method for manufacturing a semiconductor device, wherein a multilayer wiring having three or more layers constituted by a second wiring group composed of one or two or more wirings is formed.
The first dummy wiring group consisting of one or more dummy wirings in the same layer as the respective wirings constituting the first wiring group and the same wiring as the respective wirings constituting the third wiring group A reinforcing pattern is formed in a corner portion of the semiconductor chip by a third dummy wiring group consisting of one layer or two or more layers of dummy wiring, and the second pattern is formed in a region where the reinforcing pattern is formed in the corner portion of the semiconductor chip. A method of manufacturing a semiconductor device, wherein a mark pattern is formed by a second dummy wiring group consisting of one or two or more dummy wirings in the same layer as each wiring constituting the wiring group. A fourth wiring group consisting of one layer or two or more wiring layers covered with the first insulating film, and located above the fourth wiring group and having a relative dielectric constant higher than that of the first insulating film A method of manufacturing a semiconductor device for forming a multilayer wiring of two or more layers constituted by a fifth wiring group composed of one layer or two or more wirings covered with a second insulating film,
A reinforcing pattern is formed in a corner portion of the semiconductor chip by a dummy wiring group including one or two or more layers of dummy wirings in the same layer as the respective wirings constituting the fourth and fifth wiring groups, and the corner of the semiconductor chip is formed. Various mark patterns are formed by a dummy wiring group consisting of one or two or more layers of dummy wirings in the same layer as the respective wirings constituting the fourth and fifth wiring groups in the region where the reinforcing pattern is formed Then, the mark pattern and the reinforcing pattern are separated by removing the dummy wiring that constitutes the reinforcing pattern around the various mark patterns.   4. The method for manufacturing a semiconductor device according to claim 1, wherein the first dielectric film has a relative dielectric constant of 3.0 or less.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the mark pattern is a position recognition mark, a product type name, or a logo mark.

Images