JPH1050956A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high integration in a semiconductor integrated circuit device. SOLUTION: A silicon oxide film 17 positioned at a memory-cell array portion is processed, and a recessed pattern through which the upper end of a plug 16 is exposed for electrical connection between its lower end and a source/drain region comprising an n-type semiconductor region 8, is formed at the bottom of the silicon oxide film 17. A thin titanium nitride film 19 and a thick platinum film 20 are deposited on the entire silicon oxide film 17 including the inside of the recessed pattern, then the titanium nitride film 19 and the platinum film 20 are flattened by CMP(Chemical Mechanical Polishing). Then, a lower capacitive storage electrode 20a, electrically connected via the plug 16 to the source/ drain region, is formed by being isolated inside the recess pattern by removing the titanium nitride film 19 until the silicon oxide film 17 is exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a DRAM (Dynamic Random Access Memory).
Access Memory), FRAM (Ferroelectric Random Ac)
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device having a cess memory or the like.

[0002]

2. Description of the Related Art In one of semiconductor integrated circuit devices, a memory cell is a memory cell selecting MISFET (Metal Insulator).
There are a DRAM and an FRAM formed by a semiconductor field effect transistor) and an information storage capacitor. However, DRAMs and FRAMs have a problem that the memory cell structure is miniaturized with the increase in capacity and the amount of charge stored in the information storage capacitor element is reduced.

Therefore, in a DRAM of 256 Mbit or more, the amount of stored charge is increased by using a high dielectric constant film or a ferroelectric film as a capacitance storage film. However, in order to form a high-dielectric-constant film or a ferroelectric film without deteriorating characteristics or the like, it is necessary to select a base electrode material. For example, as described in Science Forum Co., Ltd., June 30, 1995, 1st edition, 4th printing, “Ferroelectric Thin Film Memory”, P252 to P260, etc., as a base electrode material, It is necessary to use a chemically stable noble metal that does not easily oxidize the electrode surface during dielectric film formation.

[0004]

However, when a noble metal is used as a base electrode material, dry etching becomes difficult.

The present inventor has proposed a DRA using a high dielectric constant film.
In developing an FRAM using M and a ferroelectric film, the following technical problems were found.

That is, when a noble metal is used as the material of the capacitance storage electrode, it is difficult to perform fine processing because no optimum etching conditions have been found. For this reason, it is necessary to design the processing dimensions of the capacitance storage electrode larger than necessary.
This is one factor that reduces the degree of integration.

[0007] In addition, when a chemically stable precious metal is etched, there is a concern that the processing time is increased and the yield is reduced due to specialization of the etching process.
There is also a technical problem.

An object of the present invention is to provide a technique capable of realizing high integration of a semiconductor integrated circuit device using a noble metal as a capacitance storage electrode.

Another object of the present invention is to provide a technique capable of improving the yield and throughput in the manufacturing process of a semiconductor integrated circuit device using a noble metal as a capacitance storage electrode.

Another object of the present invention is to provide a technique capable of realizing high integration in a DRAM or FRAM having a laminated information storage capacitor using a high dielectric constant film or a ferroelectric film. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor integrated circuit device of the present invention, at least one of the first and second capacitance storage electrodes sandwiching the capacitance insulating film is formed by using a damascene method. More specifically, as an example, a fine concave pattern is formed in an oxide film by etching, a conductive film made of a noble metal or the like is embedded, and then a CMP (Chemical Mec.
By removing the conductive film deposited outside the concave pattern using the hanical polishing method, a fine conductive film is selectively left inside the concave pattern as a lower capacitance storage electrode. After that, a high dielectric constant film or a ferroelectric film is deposited as a capacitance insulating film, and a conductor film for an upper capacitance storage electrode made of a noble metal or the like is further deposited to form a capacitance storage structure having a fine capacitance storage electrode. It is a method of forming.

As an example, a fine concave pattern having a desired size is formed in an oxide film by etching, and a lower electrode material, a ferroelectric film,
The upper electrode material is overlaid and embedded, and then the extra portion other than the inside of the concave pattern is removed by the CMP method, so that the capacitor composed of the lower capacitance storage electrode, the ferroelectric film, and the upper capacitance storage electrode is formed inside the concave pattern. This is to form the storage structure all together.

According to the above means, the electrode material made of a noble metal or the like, which is difficult to etch, is not subjected to fine processing by etching or the like, and the minimum processing of an oxide film such as silicon oxide, whose processing conditions are well known, is performed. It is possible to form a lower capacity storage electrode, a capacity storage structure, and the like as fine as the size equal to the size, and it is possible to achieve high integration of a semiconductor integrated circuit device by miniaturizing the capacity storage structure.

In particular, for example, when the capacitance storage structure is a DRAM
When used as a capacitor for storing information in a semiconductor memory device such as a semiconductor memory device or an FRAM, the information storage capacity of the semiconductor memory device can be increased.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the following embodiments, components having the same function are denoted by the same reference numerals, and duplicate description thereof will be omitted.

(Embodiment 1) FIGS. 1, 2, 3 and 3 show an example in which a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention is applied to a method of manufacturing an FRAM. This will be described with reference to FIGS. 4, 5, 6, 6, 7, 8, and 9.

First, after a LOCOS (Local Oxidation of Silicon) oxide film 2 is formed on a semiconductor substrate 1 by a known method, a P-type well 3, an n-type well (not shown), and a gate insulating film are formed by a known method. Then, a polycrystalline silicon film 5 and a silicon oxide film 6 are sequentially deposited on the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method,
The gate electrode of the MISFET is formed by etching.

Next, a sidewall film 7 is formed by depositing and etching a silicon oxide film. Next, a memory cell selecting MISFET is formed by a known method.
N-type semiconductor regions 8 (source and drain regions) are formed.

Next, as shown in FIG. 2, after depositing a silicon oxide film 9 on the semiconductor substrate 1 by the CVD method, the surface of the silicon oxide film 9 is flattened by the CMP method. Next, the silicon oxide film 9 is etched using a patterned photoresist (not shown) as a mask to form a contact hole 10 reaching one n-type semiconductor region 8 of the memory cell selecting MISFET in the memory cell array portion. Thereafter, a polycrystalline silicon film (not shown) is deposited on the semiconductor substrate 1, and then the polycrystalline silicon is etched using a photoresist (not shown) as a mask to form bit lines 11.

Next, as shown in FIG. 3, after a silicon oxide film 12 is formed on the semiconductor substrate 1, the surface of the silicon oxide film 12 is flattened by a CMP method. Next, a silicon nitride film 13 and a silicon oxide film 14 are deposited by a CVD method.

Next, as shown in FIG. 4, the silicon oxide film 14, the silicon nitride film 13, and the silicon oxide film 12 are etched using a photoresist (not shown) as a mask to select a memory cell selecting MISFE.
A contact hole 15 reaching one n-type semiconductor region 8 of T is formed.

Next, as shown in FIG. 5, a plug 16 is formed by depositing a polycrystalline silicon film on the semiconductor substrate 1 and etching it back.

Next, as shown in FIG. 6, a silicon oxide film 17 is deposited, and the silicon oxide film 17 is etched using a photoresist 18 as a mask to form a concave pattern 17a to be a lower capacitance storage electrode region (FIG. 6). First step). Here, since the etching conditions of the silicon oxide film 17 are well known in a semiconductor manufacturing process, the width dimension and the like of the concave pattern 17a in the lower capacitance storage electrode region can be easily, finely and precisely adjusted to a required dimension. It is possible to form.

Next, as shown in FIG.
A thin titanium nitride film 19 and a platinum film 20 are sequentially deposited on the entire region including the inside of “a” (second step).

Next, as shown in FIG. 8, the surface of the platinum film 20 is flattened by the CMP method, and the surface of the titanium nitride film 19 is removed by the CMP method until the silicon oxide film 17 is exposed. Thereby, the region of the lower capacitance storage electrode 20a is formed separately (third step).

Next, as shown in FIG. 9, a PZT film 21 as a ferroelectric and a platinum film 22 for forming an upper capacitance storage electrode are deposited (fourth step; fifth step).
The PZT film 21 and the platinum film 22 are etched using a photoresist (not shown) as a mask to form an upper capacitance storage electrode 22a, and then covered with a silicon oxide film 23. Thereby, the lower capacitance storage electrode 20a and the PZT film 2
1. A capacitance storage structure (capacitor) including the upper capacitance storage electrode 22a is configured.

Next, the silicon oxide film 2 on the semiconductor substrate 1
After forming a not-shown through-hole reaching the upper capacitance storage electrode 22a and a conductive plug filling the through-hole at a predetermined position in FIG.
After depositing a metal film (not shown) made of an aluminum alloy or tungsten silicide, the metal film is processed using a patterned photoresist (not shown) as a mask, thereby forming a metal wiring layer connected to the plug. (Not shown), and finally, the surface of the semiconductor substrate 1 is covered with a passivation film (not shown) to complete the FRAM of the present embodiment.

As described above, according to the first embodiment, the platinum film 20 and the like are selectively embedded by the damascene method in the concave pattern 17a formed by etching the silicon oxide film 17, thereby lowering the capacitance. Since the storage electrode 20a is formed, the lower capacitance storage electrode 20a made of a hard-to-etch noble metal or the like is not directly processed by dry etching, so that the processing dimensions are not affected by the etching performance, and the processing conditions are well known. Since the film 17 can be formed finely and with high precision to the extent of the etching process size, the lower capacitance storage electrode 20a does not need to be made unnecessarily large, so that the degree of integration can be improved and the yield can be improved.

(Embodiment 2) FIGS. 10, 11, and 1 show an example in which a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention is applied to a method of manufacturing an FRAM.
This will be described with reference to FIG. First, similarly to the method of manufacturing the FRAM illustrated in the first embodiment, the concave pattern 17a for the silicon oxide film 17 illustrated in FIG.
(A first step).

Next, as shown in FIG.
7a, the titanium nitride film 24, the platinum film 2
5 (second step), a PZT film 26 is further deposited (third step), and a platinum film 27 is further deposited (fourth step).
Process).

Next, as shown in FIG. 11, the titanium nitride film 24, the platinum film 25, and the PZT film 2 are formed by the CMP method.
6. By flattening the platinum film 27 and exposing the silicon oxide film 17, a capacitance storage structure (capacitor) composed of the lower capacitance storage electrode 25a and the upper capacitance storage electrode 27a sandwiching the capacitance insulating film 26a is formed (fifth). Process).

Next, as shown in FIG. 12, a silicon oxide film 28 is deposited.

Next, as shown in FIG. 13, a contact hole 29 is formed on the upper capacitance storage electrode 27a by processing the silicon oxide film 28 using a patterned photoresist (not shown) as a mask. , A titanium film 30, and a metal film 31 made of an aluminum alloy or tungsten silicide, and then processing the metal film 31 using a patterned photoresist (not shown) as a mask to form a contact hole 2
9, a metal wiring layer 31a is formed to be electrically connected to the upper capacitance storage electrode 27a.
The FRAM according to the embodiment is completed.

As described above, in the second embodiment, the lower capacitance storage electrode 25 made of a noble metal or the like which is difficult to etch
Since a is not directly processed by dry etching, the processing size is not affected by the etching performance. That is, it is possible to easily finely process the lower capacitance storage electrode 25a or the like made of a noble metal or the like which is difficult to etch to the fine processing dimensions of the concave pattern 17a by etching the silicon oxide film 17 whose processing conditions and the like are well known. This makes it possible to improve the degree of integration.

Further, since the lower capacitance storage electrode 25a, the upper capacitance storage electrode 27a, etc., which constitute the capacitor with the capacitance insulating film 26a interposed therebetween, can be processed by one CMP processing, the number of steps can be reduced, and the yield and the yield can be reduced. An improvement in throughput can be realized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is.

For example, in each of the above-described embodiments, the capacitor for arranging the information storage capacitance element above the bit line is used.
Capacitor Over Bitline (C)
Although the method of manufacturing the FRAM having the memory cell of the OB) structure has been described, the present invention is also applicable to an FRAM having a memory cell in which a bit line is arranged above an information storage capacitor.

In each of the above embodiments, the FRAM
Has been described, but the present invention is also applicable to a DRAM.
In each of the above embodiments, the etching stopper,
Although the case where a silicon nitride film is used for the purpose of preventing impurity diffusion and preventing oxidation of a silicon substrate has been described, a dielectric film such as a tantalum oxide film may be used.

Further, in the embodiments described above, it is used a PZT film on the capacitor insulating film of the information storage capacitor, B _a T
high dielectric such as _i O ₃ film film or may be a stacked film of these films.

In each of the above embodiments, the PZT film is used as the capacitance insulating film of the information storage capacitance element.
When applied to M, a dielectric film such as a tantalum oxide film or a silicon nitride film or a laminated film of these films may be used.

In each of the above embodiments, the titanium nitride film is used for the purpose of preventing impurity diffusion and preventing oxidation of the plug and the silicon substrate. However, a conductor film such as a titanium film or a laminated film of these films is used. May be used.

The material of the capacitance storage electrode is not limited to platinum. For example, ruthenium (R _u ), ruthenium oxide (R _u O), iridium (I _r ), iridium oxide (I
_r O ₂₎ or the like, can be any noble metals and their compounds.

[0046]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, there is an effect that high integration of a semiconductor integrated circuit device using a noble metal as a capacitance storage electrode can be realized.

Further, the yield and throughput in the manufacturing process of a semiconductor integrated circuit device using a noble metal as the capacitance storage electrode can be improved.

Further, in a DRAM or FRAM having a stacked information storage capacitor using a high dielectric constant film or a ferroelectric film, an effect of achieving high integration can be obtained.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a manufacturing process of an FRAM according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing process of the FRAM according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the second embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the second embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the FRAM according to the second embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 LOCOS oxide film 3 p-type well 4 gate insulating film 5 polycrystalline silicon film 6 silicon oxide film 7 sidewall film 8 n-type semiconductor region (source, drain region) 9 silicon oxide film 10 contact hole 11 bit line 12 Silicon oxide film 13 silicon nitride film 14 silicon oxide film 15 contact hole 16 plug 17 silicon oxide film (insulating film) 17a concave pattern 18 photoresist 19 titanium nitride film (underlying thin film) 20 platinum film (conductor film) 20a lower capacitance storage electrode ( First capacitance storage electrode) 21 PZT film (capacitive insulating film) 22 Platinum film (conductor film) 22a Upper capacitance storage electrode (second capacitance storage electrode) 23 Silicon oxide film 24 Titanium nitride film (underlying thin film) 25 Platinum film (Conductor film) 25a Lower capacitance storage electrode (first capacitance storage electrode) ) 26 PZT film (capacitor insulating film) 27 a platinum film (conductive film) 27a upper storage capacitor electrode (second storage capacitor electrode) 28 a silicon oxide film 29 contact hole 30 a titanium nitride film 31 a metal film 31a metal interconnect layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 21/822 H01L 27/10 621Z 27/10 451 29/78 371 21/8247 29/788 29 / 792

Claims (10)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device, wherein at least one of a first and a second capacitance storage electrode sandwiching a capacitance insulating film is formed by using a damascene method. 2. a first step of forming a concave pattern in an insulating film; a second step of forming a conductive film serving as a first capacitance storage electrode on a surface of the insulating film including the concave pattern; A third step of selectively removing the conductor film inside the concave pattern to form the first capacitance storage electrode by removing the conductor film flat until the surface of the insulating film is exposed; A fourth step of forming a capacitor insulating film on the insulating film and the first capacitor storage electrode; and a fifth step of forming a conductor film to be a second capacitor storage electrode on the capacitor insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising: 3. The semiconductor integrated circuit device according to claim 1, wherein said first and second capacitance storage electrodes are made of a noble metal or a compound containing a noble metal. Manufacturing method. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said capacitor insulating film is made of a high dielectric constant film or a ferroelectric film. . 5. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein after the first step and prior to the second step, the surface of the insulating film is formed along the shape of the concave pattern. Forming a base thin film of silicon nitride or the like on a semiconductor integrated circuit device. 6. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a capacitance storage structure by using a damascene method after depositing a lower capacitance storage electrode film, a capacitance insulating film, and an upper capacitance storage electrode film. 7. A first step of forming a concave pattern on an insulating film, and a second step of forming a thin lower capacitance storage electrode film on the surface of the insulating film so as to reflect the surface shape of the concave pattern. A third step of forming a thin capacitive insulating film on the lower capacitive storage electrode film so as to reflect the surface shape of the concave pattern; and forming a thin capacitive insulating film on the capacitive insulating film so as to embed the concave pattern. A fourth step of forming an upper capacitance storage electrode film; and removing the upper capacitance storage electrode film, the capacitance insulating film and the lower capacitance storage electrode film flat so that the surface of the insulating film is exposed, A fifth step of forming a capacitance storage structure having a laminated structure of the lower capacitance storage electrode film, the capacitance insulating film, and the upper capacitance storage electrode film inside the concave pattern. Semiconductor integrated circuit device Manufacturing method. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the lower capacitance storage electrode film and the upper capacitance storage electrode film are made of a noble metal or a compound containing a noble metal. A method for manufacturing a circuit device. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said capacitor insulating film is made of a high dielectric constant film or a ferroelectric film. . 10. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein after said first step and prior to said second step, said concave pattern is formed on a surface of said insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising: forming an underlying thin film of silicon nitride or the like along the line.